JPS61177540A - Control circuit for string data - Google Patents

Abstract

PURPOSE:To easily uniform the digits of even data which is not at a word boundary and to easily perform arithmetic on word-width basis by operating a byte ring shifter by using information of the low-order digit bits of the address of the date. CONSTITUTION:The function of the byte ring shifter 6 is set to a 2-byte exchange mode by a function determining block 7 on the basis of the two least significant digit bits of AS1 and AS2 stored in the 1st data register 3 and then the byte ring shifter 6 operates as a shifter which exchanges two bytes. Then, the starting 1-byte data A1 of data A is stored in the 1st data register 3 and its contents are further stored in the 2nd data register 4 through the byte ring shifter 6. When the starting 4-byte data B1 of data B is read in the 1st data register 3, an arithmetic block 11 performs arithmetic as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a string data control circuit in a microprocessor, and particularly to a string data control circuit for processing large byte string data at word boundaries.

(Prior Art) In a data processing device, when processing byte string data stored in an external storage device that can be accessed in units of words consisting of multiple bytes, a microprocessor is used to process byte string data in units of words. Even if data is read for processing, if the data is not defined by word boundaries, the byte positions of the two word data read in one hour may be shifted, so the data digits must be aligned. I had to. However, since controlling data digit alignment is complex, conventionally data has generally had to be accessed and processed in byte units.

(Problems to be Solved by the Invention) As explained above, according to the prior art, data access and operations are executed one byte at a time, so many steps need to be executed, especially when the data is long. The disadvantage was that the processing speed was slow.

The object of the present invention is to perform a byte-by-byte shift in a word width consisting of multiple bytes, store a lower part of the address of two byte string data, and determine a byte ring shift function from the stored information. In addition, the above disadvantages are solved by temporarily storing byte string data in word width, and then merging according to the byte ring shift function, and the sling data is configured so that operations can be performed in word width. The purpose is to provide a control circuit.

(Means for Solving the Problems) According to the present invention, the IJ song output control circuit includes a byte ring shifter, a pair of address registers, a function determination block, first to third data registers,
It is configured with a calculation block.

This is used to perform a byte-by-byte shift in a byte ring shifter with a word width consisting of multiple bytes.

The pair of address registers are for storing part of the lower addresses of the pair of byte string data.

The function determination block is for determining the function of the byte ring shifter from the information stored in the pair of address registers.

The first data register has a size equal to the word width and is for temporarily storing byte string data.

The second data register is for temporarily storing the result after the contents of the first data register are shifted by the byte ring shifter.

The third data register stores the result obtained by shifting the contents of the first data register by the byte ring shifter and the data obtained by merging the contents of the second data register according to the function of the byte ring shifter. It is the ninth one.

The calculation block is for calculating the contents of the first and third data registers in word width.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a string data control circuit according to the present invention. In FIG. 1, 1 is a microprocessor to which the present invention is applied, 2 is an external storage device for storing byte string data, and 3 to 5 are 4-byte wide storage devices for temporarily storing byte string data. 1 to 3rd data registers, 6 a byte ring shifter, 7 a function determination block for determining the function of the byte ring shifter 6;
8.9 is an address register for storing the lowest two bits of each address of two byte string data, 1G is an address generation block for generating the address of byte string data, and 11 is a 4-byte wide calculation block. , 20 is a 4-byte wide data bus from the external storage device 2, and 21 is an address for giving the address generated by the address generation block 10 to the external storage device 2.

FIG. 2 is an explanatory diagram showing two byte string data used in this embodiment. The data shown in FIG. 2 is stored in the external storage device 2, A81 represents the address of the data person, AS2 represents the address of the data B, and the lowest two bits of each are 11 and 01, and Al-A3
．． B1-83 is a 4-byte boundary (4-byte width) data unit that is accessed at one time.

FIG. 3 is an explanatory diagram showing the types of functions of the bite ring shifter 6, their operations, and how the functions are determined by a combination of two data stored in the register 8.9. .

FIG. 4 is an explanatory diagram showing the process of processing the data in FIG. 2 in this embodiment. Next, the operation of this embodiment will be explained according to FIG. In Figure 4, Phase 1)
Now, the ASI and AS stored in the first data register 3
2, the function determination block 7 sets the function of the biting ring shifter 6 to the 2-byte exchange mode according to FIG. make it work. Thereafter, the first 4 bytes of data A1 of the data person are stored in the first data register 3, and the contents are further stored in the second data register 4 through the byte ring shifter 6.

Next, in phase 11), after storing the next 4 bytes of data A2 in the register 3, its contents are combined with the data obtained through the byte ring shifter 6, and in phase 1)
The data stored in the second data register 4 is merged with the data stored in the third data register 5. This method of merging also follows the function determined by the function determination block. Thereafter, the output data of the bite ring shifter 6 is stored in the second data register 4.

Since the third data register 5 stores the data whose digits are aligned with the data B, the phase 111)
When the first 4 bytes of data Bl of data B are read into the first data register 3, the arithmetic block 11 reads the first 4 bytes of data Bl.
Can perform calculations.

Similarly, in phase IV), the next 4 bytes of data A3 after data A are read, and the second data register 4 is first read.
The data is merged with the data previously stored in the data register 5 and stored in the third data register 5, and new contents are set in the second data register 4. Then, in phase V), when the next 4 bytes of data Bl of data B are read, the second operation data is set in the first data register 3 and the third data register 5, and the operation block 11 sets the second operation data. Perform the second calculation. The last byte d remaining in the second data register 4 as shown in phase vl)
After transferring l' to the third data register 5, the last 4 bytes of data B3 of data B can be read into the first data register 3 in phase (wit), and the final calculation can be performed in the calculation block 11. .

In this embodiment, an example in which one word consists of 4 bytes has been explained, but the present invention is not limited to 4 bytes, and even when one word consists of 2 bytes or 8 bytes, the same method can be applied. Can perform digit alignment and calculations.

(Effects of the Invention) As explained above, in the present invention, by operating the byte ring shifter using the information of the lower bits of the data address, data digit alignment can be easily performed even for data that is not a word boundary. This has the advantage that word-width operations can be easily executed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a string data control circuit according to the present invention. FIG. 2 is an explanatory diagram showing the status of two byte string data in this embodiment. FIG. 3 is an explanatory diagram showing the types of functions of the bite ring shifter, their operations, and conditions for determining the functions. FIG. 4 is an explanatory diagram showing the operation process of this embodiment. 1...Microprocessor 2...External storage device 3
~5,8.9... Register 6... Byte ring shifter 7... Shift function determination block lO...
Data address generation block 11... operation block
20.21...Bus As1. A82...Address Al-A3. B1-B5... Data patent applicant NEC Co., Ltd. agent Patent attorney Inoro Jusai 1 figure 2 meters Figure 3 figure 4

Claims (1)

[Claims] a byte ring shifter for performing a byte-by-byte shift in a word width consisting of multiple bytes; a pair of address registers for storing part of the lower address of a pair of byte string data; a function determination block for determining a function of the biting shifter from the information;
a first data register having a size equal to a word width and for temporarily storing the byte string data; and a first data register having a size equal to a word width and for temporarily storing the byte string data; and a second data register for storing the contents of the first data register by the byte ring shifter, and a result obtained by shifting the contents of the first data register by the byte ring shifter and the contents of the second data register according to the function of the byte ring shifter. and a third data register for storing the data obtained by merging the first and second data registers, and a calculation block for calculating the contents of the first and third data registers in word width. Characteristic string data control circuit.