JPH0778723B2 - Information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention inserts a second decimal operand in a packed format on a memory by inserting zero digits into the upper order by the number specified by an instruction word. The present invention relates to an information processing device that processes an instruction to be transferred to a 1-operand position, and particularly to an information processing device that detects a decimal overflow exception.

[Conventional technology]

As shown in FIG. 4 (b), a general-purpose computer of a certain type:
The packed second decimal operand of (l ₂ +1) bytes in memory is inserted into the upper digit of v ₁ zero digit and transferred to the first operand position of (l ₁ +1) bytes in memory There is an instruction (hereinafter referred to as ZAVL instruction). At the time of data transfer by this ZAVL instruction, the code of the second operand is transferred to the least significant digit of the first operand. When the digits of the second operand are insufficient in the transfer of numbers, the digits of zero value are packed in the lower order of the first operand excluding the sign digit,
When the number of digits of the operand is large, the number of the surplus second operand is truncated without being transferred. At this time, if the truncated digits have significant digits, the decimal overflow mask bit in the program status word (PSW) is 1
If so, it becomes a decimal overflow exception and causes a prozram interrupt.

Conventionally, the execution of this type of ZAVL instruction has been processed in 1-byte units when performance is not required. In detail, first v ₁ digit zero is transferred to the upper part of the first operand in 1-byte units, then the second operand is read sequentially from the upper part in 1-byte units from the memory, and the first operand position where the zero was transferred first Transfer to the lower part of. In this transfer, the second
When there are not enough operands, they will be transferred after being filled with zeros. Conversely, if the second operand is left over, then the extra digits are not transferred to the first operand position, but are sequentially checked for containing significant digits. If it contains a significant digit, a decimal overflow exception is detected when the decimal overflow mask bit is 1. The sign of the second operand is put in the lower digit of the last byte of the transfer, and is transferred as the sign of the first operand.

On the other hand, when performance is required, all the second operands are read from the memory in units of multiple bytes, for example, 8 bytes, and aligned (shifted) so that they are right-justified in the arithmetic circuit.
And supply it to the arithmetic circuit, which is (v ₁ + 2l ₂
-2l ₁ ) Shift right by digit and obtain right-justified data in the arithmetic circuit as the first operand. Here, v ₁ , l ₁ and l ₂ are the offsets given by the instruction word of the ZAVL instruction shown in FIG. 4 (a), (the byte length of the first operand-1) and (the byte length of the second operand, respectively). -1). In addition, when (v ₁ + 2l ₂ −2l ₁ ) is negative, − (v ₁ +
2l ₂ −2l ₁ ) digits are shifted left. (V ₁ + 2l ₂ −2l ₁ )
If 1 is 1 or more, significant digits may be truncated by the above right shift. Therefore, check whether significant digits are included in the lower (v ₁ + 2l ₂ −2l ₁ ) digits of the second operand before shifting. To check. For this reason, in the arithmetic circuit, a circuit for detecting the zero of the value of each digit, a circuit for counting the number m of zero digits connected in the lower order based on the output of this circuit, and this number m and the above (v ₁ + 2l ₂ −2l ₁ ) and a circuit for comparing with. In the comparison by this comparison circuit, m <(v ₁
+ 2l ₂ −2l ₁ ) indicates that there is a significant digit to be truncated, and if the decimal overflow mask bit is 1, it is a decimal overflow exception. The right-shifted data has a code corresponding to the code of the second operand embedded in the least significant digit (provided that the plus sign is used when the value of the first operand is zero without truncation of significant digits), and The data is aligned according to the address of one operand and stored in the memory.

[Problems to be Solved by the Invention]

In the above-described conventional information processing apparatus, when processing in the former byte unit, the processing is executed in 1-byte units, so that there is a drawback in that speeding up of the processing cannot be expected.

In the latter case, when processing multiple bytes at the same time, ZAVL
For the instruction only, a circuit for detecting the number of digits whose value is zero, which is connected to the lower order of the second operand, is required, and the amount of hardware increases. Since it is necessary to check whether or not is zero, there is a disadvantage that the processing time for that increases.

In view of the above points, an object of the present invention is to process the ZAVL instruction overflow detection in the same manner as other decimal instruction overflow detection, thereby enabling the ZAVL instruction to be processed at a high speed with a small amount of metal. It is to provide the information processing device.

[Means for Solving the Problems]

The information processing apparatus according to the present invention inserts the second operand of a packed decimal number having a code digit in the least significant digit into the upper digit by the number specified by the instruction word, and inserts the digit into the upper operand. In an information processing device that processes an instruction to be transferred, an aligning unit that aligns the second operand read from the memory so that it is right-justified in an arithmetic circuit, and a code digit of the second operand that is aligned by the aligning unit. The masking means for masking to zero, and the data masked by the masking means are right-justified in the arithmetic circuit as the first operand according to the number of digits designated by the instruction word and the number of digits of the first operand and the second operand. Rotation shift means for performing rotation shift so that the value of each digit of the data rotated by this rotation shift means is zero. First digit zero detecting means for detecting whether or not the number of digits in the upper-order value of zero is detected from the output of the first digit zero detecting means, and the effective digit number of the data rotation-shifted by the rotation shift means. Effective digit number obtaining means, second digit zero detecting means for detecting the least significant digit zero of the data rotation-shifted by the rotation shift means, and the effective digit number obtained by the effective digit number obtaining means. And a number of digits of the first operand, an output of the comparing means, an output of the first digit zero detecting means, an output of the second digit zero detecting means, and a sign of the second operand. Generate a condition code in response to the binary overflow mask bit
Overflow exception detecting means for detecting a decimal overflow exception, result code embedding means for embedding a result code in the least significant digit of data rotated by the rotation shift means, and result code embedding by the result code embedding means Storage means for aligning the data according to the address of the first operand and storing the data in the memory for the length of the first operand.

[Action]

In the information processing apparatus of the present invention, the aligning means aligns the second operands read from the memory so that they are right-justified in the arithmetic circuit, and the masking means aligns the second operands.
An arithmetic circuit as a first operand according to the number of digits designated by the instruction word for the data masked by the masking means by the rotation shift means and the number of digits of the first operand and the second operand. The first digit zero detecting means detects whether the value of each digit of the data rotation-shifted by the rotation shifting means is zero, and the second digit zero detecting means The rotation shift means detects the lowest digit zero of the rotation-shifted data, and the effective digit number obtaining means obtains the number of digits having a value of zero from the output of the first digit zero detecting means to the rotation shift means. The effective digit number of the rotation-shifted data is obtained by the The effective digit number and the digit number of the first operand are compared, and the overflow exception detecting means outputs the output of the comparing means, the output of the first digit zero detecting means, the output of the second digit zero detecting means, and the second operand. In response to the sign and the decimal overflow mask bit to detect a decimal overflow exception, and the result code embedding means embeds the result code in the least significant digit of the data rotation-shifted by the rotation shift means. The storage unit aligns the data in which the result code is embedded by the result code embedding unit according to the address of the first operand, and first
Store only the length of the operand in memory.

EXAMPLES Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing a configuration of an arithmetic circuit in an information processing apparatus according to an embodiment of the present invention. This arithmetic circuit includes a memory 1, a control circuit 2, an aligner 3, a length register 4, a sign register 5, data registers 6 to 8, a shift amount register 9, and a length decoder 10.
A digit zero detection circuit 11 and 12, an adder 13, a digit shifter 14, a comparison circuit 15, a write mask register 16, an OR circuit 17, a data register 18, a shift circuit 19,
It is composed of a condition code generation circuit 20, an aligner 21, and a result code embedding circuit 22.

The memory 1 stores instruction words and operands that form a program.

The control circuit 2 controls the entire arithmetic circuit based on a ZAVL instruction or the like.

The aligner 3 aligns the operands read from the memory 1 at a position convenient for the subsequent calculation according to the operand address, and masks a portion unnecessary for the calculation to zero. In the case of the ZAVL instruction, the 8-byte second operand read from the memory 1 is shifted right justified by the aligner 3, and the non-second operand portion of the 8-byte data (including the sign digit) is zero. Is embedded.

The length register 4 is a register that holds the byte length of the operand. The byte length is supplied from the control circuit 2.

The code register 5 holds the code of decimal data, and is used for creating a code for operation and a condition code. In the case of the ZAVL instruction, the second operand is from the aligner 3 to the data register 6
The code is taken into the code register 5 at the timing of being transferred to the data registers 7 and 7, and at the same time, the data in which the code digit is replaced with zero is transferred to the data registers 6 and 7.

The data registers 6 to 8 are 8-byte data registers for calculation, and are input registers of the adder 13 and the digit shifter 14.

The shift amount register 9 holds the shift amount of the digit shifter 14. In the case of the ZAVL instruction, the value of (2l ₁ −2l ₂ −v ₁ ) as the shift amount of the digit shifter 14 is supplied from the control circuit 2 to the shift amount register 9.

The adder 13 is an adder circuit that adds the contents of the data registers 6 and 7 in decimal.

The digit shifter 14 is a shift circuit that shifts the contents of the data register 8 by the number of digits (2l ₁ −2l ₂ −v ₁ ) designated by the shift amount register 9. When the shift amount (2l ₁ −2l ₂ −v ₁ ) is positive, left shift is performed, and when it is negative, right shift is performed, and the output is 8 bytes. Further, the digit shifter 14 can selectively execute rotation shift and simple shift according to an instruction from the control circuit 2. In the case of rotation shift, the digit spilled by the shift becomes shift-in data from the opposite side. In the case of simple shift, the shift-in data is zero. Not only the ZAVL instruction but also the decimal instruction, the operation data right-justified in the operation circuit is digit shifter 14 and adder 13
The calculation is performed by and, and the right-justified calculation result is obtained. In the case of the ZAVL instruction, as shown in FIG. 2, the processing differs depending on the values of (operand byte length-1) l ₁ and l ₂ and the offset v ₁ . In FIG. 2, an 8-byte rotation shift / simple shift is a rotation shift / simple shift performed by the digit shifter 14, and a 16-byte rotation shift / simple shift is a 16-byte second operand (second operand). Is less than 16 bytes, it is a 16-byte rotation shift / simple shift performed by using the digit shifter 14 and the adder 13 to add 16 to the upper byte to make 16 bytes. In Fig. 2, (2l
_{When 1} −2l ₂ −v ₁ ) <0 and l ₁ > 7 and l ₂ > 7, the data of the part to be truncated by the right shift is separately obtained in the same manner as in the prior art to detect overflow, We have to check if the value is zero.

The digit zero detection circuit 11 is a digit zero signal Z _i that indicates whether the value of each digit of 16 bytes of decimal data, which is obtained by concatenating the 8 bytes of decimal data held in the data registers 6 and 7, is zero. (I = 0 to 31) is detected. Furthermore, the digit zero signal value continuous from the digit zero signal Z ₀ at the beginning the higher is 1 Z _i
Count and output. For example, Z ₀ Z ₁ Z ₂ ... Z ₃₁ = 11110 ...
When set to 1, 4 is output because it is 4 which is the number of consecutive 1s starting from Z ₀ .

The digit zero detection circuit 12 detects the least significant digit zero of the data register 7. The output of the digit zero detection circuit 12 matches the digit zero signal Z ₃₁ described above.

The comparison circuit 15 doubles the byte length of the first operand in the length register 4, that is, the number of digits (l ₁ +1) of the first operand, and 32 minus the output of the digit zero detection circuit 11, That is, the number of significant digits of 16-byte data in the data registers 6 and 7 is compared. When the number of digits of the first operand is smaller than the number of significant digits of 16-byte data, there is a possibility that a decimal digit overflow exception may occur due to truncation of significant digits when storing, so the comparator circuit 15 sets 1 to 1. Output, and 0 otherwise.

The OR circuit 17 includes the output of the comparison circuit 15 and the digit zero detection circuit 12
OR with the output of. In the case of the ZAVL instruction, significant digits to be truncated may be included in the least significant code digit when the right rotation shift is performed.
The digit zero signal of the least significant digit must also be seen as a condition for overflow occurrence.

The condition code generation circuit 20 uses the operation result obtained from the comparison circuit 15, the logical sum circuit 17, the sign register 5, the digit zero detection circuit 11 and the decimal overflow mask bit in the data registers 6 and 7 as the first operand. Generates a condition code and stores an exception when storing in the. That is, the digit zero signal Z _i (i
= 0 to 31) are all 1, the operation result is zero, so the condition code 0 indicating that is generated. On the other hand, when the overflow does not occur and at least one digit zero signal Z _i is not 1, the condition code is generated according to the positive or negative value indicated by the sign register 5 (2 if positive, 1 if negative). Further, when the occurrence of overflow is detected by the comparison circuit 15 or the OR circuit 17, the condition code 3 is generated, and when the decimal overflow mask bit is 1, a decimal overflow exception is further generated. The output of the OR circuit 17 is used only for the ZAVL instruction, and for the other decimal instructions, only the output of the comparison circuit 15 is used for detecting the overflow.

The length decoder 10 decodes the content of the length register 4 (byte length of the operand), and outputs 16-bit data in which 1 is consecutive from the right end by the number of contents of the length register 4. For example, if the content of the length register 4 is 3
In the case of, "0000000000000111" is output. this is,
Inside the operation circuit, the operation result is treated as 16 bytes by extending the upper zero with 0. Therefore, even if the operation result can fit in the data register 7 within 8 bytes, put the zero data in the data register 6 and combine it. This is because overflow is detected as a result of the operation of 16 bytes. The output of the length decoder 10 indicates the byte position stored in the memory 1 as the first operand of the right-justified data obtained by the operation. For example, the above “000000
In the case of 0000000111 ", it indicates that the rightmost 3 bytes are stored.

The write mask register 16 holds the output of the length decoder 10.

The result code embedding circuit 22 is a circuit for embedding the result code in the least significant digit of the store data that is rotation-shifted by the digit shifter 14 and output from the adder 13.

The data register 18 is a register that holds the store data obtained by the calculation.

Aligner 21 is the first right-justified first in data register 18.
It is a circuit that shifts the store data, which is an operand, to the left to match the first operand address. this is,
A shift amount is given by the control circuit 2 and controlled.

The shift circuit 19 is controlled in the same manner as the aligner 21, and shifts the contents of the write mask register 16 according to the data shifted by the aligner 21 so that the 8 bytes of data sent to the memory 1 are actually transferred. Indicates the byte position to be written in memory 1. Therefore, when the 8-byte data sent to the memory 1 is the lower 8 bytes of the operation result, the lower 8 bits of the output of the shift circuit 19 are sent to the memory 1 as the write mask information, while the upper result of the operation result is higher. 8 bytes, shift circuit
The upper 8 bits of the output of 19 are sent to the memory 1 as write mask information.

The memory 1 receives 8-byte store data and 8-bit write mask information, and stores only the byte corresponding to the bit for which 1 is set in the write mask information in its storage element.

Next, the operation of the information processing apparatus of this embodiment having the above configuration will be described with reference to the specific example shown in FIG.

In the specific example shown in FIG. 3, the ZAVL instruction is a 4-byte second
Operand (l ₂ = 3) is placed in the upper 8 digits of zero (v ₁ =
8) is inserted and the 6-byte first operand position (l ₁ =
Transfer to 5). Further, the values of the lower 3 bits of the second and first operand addresses (indicating the leading byte position (zero origin) for storing significant figures) are 1 and 2, respectively. From the values of l ₁ , l ₂ and v ₁ , this case is
Shown in 1. This corresponds to the case of (i).

The second operand read from the memory 1 is 4 bytes starting from the 2nd byte of the 8-byte data as shown in FIG. 3 (i). The lowest digit S represents a code. This second operand is right-justified by the aligner 3 and is padded with zeros in the code digit to obtain the third operand.
It becomes as shown in Figure (ii).

Next, the value of (2l ₁ −2l ₂ −v ₁ ) is calculated by the control circuit 2, and in this case, −4 (= 2 × 5-2 × 3-8) is obtained. This becomes the shift amount of the digit shifter 14, and when the data of FIG. 3 (ii) is rotated right by four digits, it becomes as shown in FIG. 3 (iii).

The comparator circuit 15 compares the number of significant digits (= 16) of this data with a value obtained by doubling the byte length (= 6) of the first operand in the length register 4. In this case, since the former is larger, there is a possibility of overflow, and when the decimal overflow mask bit is 1, a decimal overflow exception is generated.

Next, the result code embedding circuit 22 embeds the result code S in the least significant digit of the data, as shown in FIG. 3 (iv). In this case, since the data is not zero, the code corresponding to the code of the second operand is embedded.

On the other hand, in order to specify the write byte, the length decoder 10 sets a 16-bit pattern obtained by decoding the byte length (= 6) of the first operand, which is the content of the length register 4, in the write mask register 16 (third part). Figure (iv)
reference).

Subsequently, the operation result and the write mask information right-justified by the aligner 21 and the shift circuit 19 are shifted to the address position of the first operand, as shown in FIG. 3 (v).

The data and the write mask information thus shifted are sent to the memory 1, and only the byte corresponding to the bit having the write mask information of 1 is stored in the memory 1 as the first operand.

〔The invention's effect〕

As described above, according to the present invention, in the processing of the ZAVL instruction, the right rotation is performed when the right shift is performed in order to obtain the right-justified first operand from the right-justified second operand in the arithmetic circuit. By performing a shift and comparing the number of significant digits of the rotation-shifted data with the number of digits of the first operand to be stored, the occurrence of overflow due to the truncation of the significant digits is detected, and the least significant digit of the rotation-shifted data is detected. The ZAVL instruction can be processed in the same way as the detection of the overflow of any other decimal instruction by detecting the overflow due to the fact that the significant digit to be truncated is entered in the least significant sign digit by checking the digit zero. The effect that ZAVL command overflow can be detected at high speed with a small increase in the amount of metal A.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an arithmetic circuit in an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining case classification of ZAVL instruction processing by the information processing apparatus according to the present embodiment. FIG. 3 is a diagram for explaining the processing of a ZAVL instruction by the information processing apparatus of this embodiment, and FIGS. 4 (a) and 4 (b) are diagrams for explaining the format and operation of the ZAVL instruction. In the figure, 1 ... memory, 2 ... control circuit, 3,21 ... aligner, 4 ... length register, 5 ... sign register, 6-8,18 ... data register, 9 ... shift amount register, 10 …… length decoder, 11,12 …… digit zero detection circuit, 13 …… adder circuit, 14 …… digit shifter, 15 …… comparison circuit, 16 …… write mask register, 17 …… OR circuit, 19… ... shift circuit, 20 ... condition code generation circuit, 22 ... result code embedding circuit.

Claims (1)

[Claims] 1. A packed format 10 having a code digit in the least significant digit.
In an information processing device that processes an instruction that inserts a zero-valued number of digits into the first operand position by the number specified by the instruction word, the second operand of the base number is read from the memory. Aligning means for aligning to the right in the arithmetic circuit, masking means for masking the code digits of the second operand aligned by this aligning means to zero, and data masked by this masking means by an instruction word. Rotation shift means for performing rotation shift so that the first operand is right-justified in the arithmetic circuit according to the number of digits to be designated and the number of digits of the first operand and the second operand, and the rotation shift means performs rotation shift. A first digit zero detecting means for detecting whether the value of each digit of the data is zero, and the first digit zero Effective digit number acquisition means for obtaining the number of significant digits of the data rotation-shifted by the rotation shift means by obtaining the number of zero digits in the upper order from the output of the output means, and the data rotation-shifted by the rotation shift means. Second digit zero detecting means for detecting the least significant digit zero of, and comparing means for comparing the effective digit number obtained by the effective digit number obtaining means with the digit number of the first operand; A condition code is generated in response to the output, the output of the first digit zero detecting means, the output of the second digit zero detecting means, the sign of the second operand, and the decimal overflow mask bit, and a decimal overflow exception is generated. The overflow exception detecting means for detecting is connected to the lowest digit of the data rotation-shifted by the rotation shift means. And a result code embedding unit for embedding a code, and a storage unit for aligning the data in which the result code is embedded by the result code embedding unit according to the address of the first operand and storing the data in the memory for the length of the first operand. An information processing device characterized by: