JPH02230320A - Data processor - Google Patents

Abstract

PURPOSE:To generate an operation flag which is independent on the size of data by setting the second size of data to be the half or the quarter of a first size having the same data width as that of registers and using the high-order side of the registers when the registers are used as data of the second size. CONSTITUTION:A data processor 700 is constituted of the registers 711-713, a barrel shifter 720, a computing element 730, data length correction mask circuits 731 and 732, a memory data register 740, a memory data aligner 741, a memory bus 742 and data buses 751-753. When data is used as integer type data smaller than register 32 bits, the high-order side among the registers having the width of 32 bits is used. When integer type data smaller than 32 bits are operated, data are drawn to left and '0' is supplemented on a right side to execute an operation. Thus, the size of data can be easily converted by a shift instruction, and the generation circuit of the operation flag is eliminated from giving at every size of data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention mainly relates to a method for generating arithmetic flags in a microprocessor (MPU) and a bit numbering rule in a register. Multiple types of sizes are defined. 1) Concerning the generation method of arithmetic flags suitable for U and the bit numbering rules in registers. [Prior Art] In a microprocessor with a word length of 16 bits or more. In addition to word size, 1 byte (8 bits) is also required as the size of data to be processed. Therefore, even a single instruction has several variations depending on its size. For example, T R O N Th
e Real-Time Operating System
Hitachi's 32-bit microprocessor Gmiero, which complies with the Em Nucleus) specification, has three types of data length for integer data: word (32 bits), halfword (16 bits), and byte (8 bits). Data length is available. For detailed specifications of this Hitachi 32-bit Microprocessor H32
/200 programming manual. In H32/200, 32 bits (4
Byte) When handling integer type data, the smaller address corresponds to the upper part of the data, and the larger address corresponds to the lower part of the data. Furthermore, the bit numbers in the data are assigned such that the most significant bit is 0 and the bit numbers increase as they go to the lower part. on the other hand,
The H32/200 has registers with a width of 32 bits. When this register is used for integer type data 4-bit smaller than 32 bits, for example, byte or halfword integer type data, the lower (right side) part of the 32 bit register is used. [Illllfl to be solved by the invention] As mentioned above, in conventional 32-bit microprocessors, when handling integer type data that is shorter than the register size, the lower side (right side) part of the register is used. When generating flags for the result (? flag, negative flag, carry flag, etc.), it was necessary to generate all flags corresponding to each size and select the one that matched the size from among them. ．． As a result, the flag generation circuit in the arithmetic circuit became complicated, and the circuit size became larger than when only handling single-sized integer type data. In addition, in H32/200, the bit numbers of data are assigned such that the most significant bit is O and the bit numbers increase as they go to the lower part, so there is an inconvenience that the bit number of the register changes depending on the size. There was a point. In other words, the Oth bit of the byte size corresponds to the 8th bit when it is a halfword, and corresponds to the 24th bit when it is a word. Therefore, different bit numbers must be specified depending on the size to indicate the same position, which requires special care from the program's perspective. Therefore, the purpose of the present invention is to: (1) To provide a method of generating an operation flag and a generation circuit that does not depend on the size of data. (2) To provide a method of specifying a bit number of a register that does not depend on the size of data. (Means for Solving the Problems) The above objectives are as follows: (1) The registers are integer type data smaller than 32 bits.
For example, when using byte or halfword data, use the upper (left) part of the 32-bit wide register; (2) Integer type data smaller than 32 bits, such as byte or halfword data. This is achieved by aligning the data to the left and padding it with zeros on the right when performing calculations. [Operation] When using a register for data smaller than 32 bits, such as byte or halfword data, by using the upper (left side) part of the 32-bit register, the 0th bit of the byte size can be set as half-word data. It also corresponds to the O-th bit when it is a word. Therefore, even if the sizes are different, the same bit number indicates the same position, and no special precautions are required from the programmer's perspective. In addition, integer type data smaller than 32 bits, for example,
When calculating byte or halfword data, the data is justified to the left and O is added to the right side. If flags are generated for word size, they can be applied to all sizes.

In other words, a zero flag is zero for all 32 bits, and a negative flag is zero.
The bit value and carry flag can be applied to all sizes as long as a carry from the 0th bit is detected. As a result, there is no need to generate all flags corresponding to each size, so the flag generation circuit in the arithmetic circuit becomes simpler and the circuit size becomes smaller. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a register of a data processing device that is an embodiment of the present invention. Register 1/00 is 32
It has a data width of bits. In the data processing device of this embodiment, the data width of 32 bits is called word size, and the data width of half 16 bits is called halfword size.
The 8-bit data width is called the byte size. register 1
00 has a data width of 1 word. register 1
When storing halfword size data or byte size data in 00, it is stored in the upper part (left side) of the register as shown in Figure 1. Each bit in the register can be accessed one by one using the bit number. As shown in FIG. 1, the bit numbers are assigned such that the most significant bit 101 on the left is the 0th bit, and the bit numbers increase as they go to the lower bits on the right. Therefore, by storing halfword size or byte size data in the register as described above, even if the Oth bit of word size is accessed in halfword or byte size, it will always be
This is the 0th bit. Figure 2 is a diagram when accessing data in memory. Addresses are assigned to each byte of memory. When dealing with word-sized or half-word-sized data in memory, it becomes as shown in Figure 2, and the byte corresponding to the smaller address becomes the upper part of the data. For example, $2
When accessing halfword size data at address 0008, the contents at address $2000 become the upper part of the data,
The contents of address $2001 become the lower part of the data. Also.
When you access the word size data at address $2000, the contents from address $2000 to $2003 will be
As shown in Figure 2, it is treated as data. In the data processing device of this embodiment, there is a BTST instruction as one of the instructions for manipulating bits. The BTST instruction specifies the bit number to be processed and the location where that bit is stored as operands. The BTST instruction is an instruction that tests 0 or 1 of a specified bit and reflects it in the operation flag. The following three types of instructions BTST #O, ($2000). wBTST $
0. ($2000). hBTST SO, ($
2000). b is an instruction to test the 0th bit of data of word size, halfword size, and byte size, respectively, starting from address $2000 in the memory. Since the bit number for each instruction is O, as shown in Figure 2, the same bit (leftmost bit) 20
This is an instruction to test 1.

On the other hand, the following three types of instructions B 'rS 'rn O, R 1 . wBTST
$0, R1. h BTST #0. Rl. b is an instruction to test the 0th bit of the first register as data of word size, halfword size, and byte size, respectively. Since the bit number of each instruction is O, as shown in FIG. 1, each instruction tests the same bit (leftmost bit) 101. Figure 3 is a diagram showing the registers of a conventional data processing device. Conventionally, when storing data shorter than the register size in a register, the lower side (right side) of the register
It was packed and stored. Therefore, when a bit manipulation instruction like the one described above is executed, the bit position pointed to by the same bit number changes depending on the data size. For example, if we consider the case where the above BTST instruction is executed, BTST 110, Rl. w targets the Oth bit 301, which is the most significant bit of the register, but BTST #O, Rl. h targets the 16th bit 302 of the register,
Also, BTST #O, Rl. b targets the 24th bit 303 of the register. As described above, the conventional data storage method has the problem that the bit number of the data stored in the register changes depending on the size of the data. According to the data storage method of this embodiment, short data is packed on the left side of the register, so when accessing data by bit number like a bit test instruction, the bit position of the same bit number changes depending on the size. Never. Therefore, when creating a program, there is no need to be aware of the bit number deviation due to size, making it easier to create a program and preventing errors from occurring.

FIG. 4 is a diagram showing a calculation flag generation method of a data processing device according to an embodiment of the present invention. The calculation flags of this data processing device include a carry (carry.C) flag indicating a carry from the most significant bit during calculation, and
There is a negative (N) flag indicating whether the operation result is positive or negative, and a zero (Z) flag indicating the operation result is zero or non-zero. Figure 4(a) shows a method for generating operation flags in addition of word-sized integer type data. C flag is 0
Carry from bit 401, N flag detects bit 0 value 402, Z flag detects all O's in all 32 bits (
403) L, reflect. FIG. 4(b) shows a method for generating calculation flags in addition of halfword-sized integer type data. Prior to the calculation, the input data is left-justified as shown in the figure, and the remaining portion on the left side is filled with 0's. In this case, since O on the left side is not involved in the calculation, the C flag is a carry from the 0th bit, 401. The N flag should be reflected in the value 402 of bit 0, and the 2 flag should be reflected by detecting all O's in all 32 bits (403). Figure 4(c) shows the method for generating calculation flags in addition of byte-sized integer type data. Figure 4(b)
Similarly, prior to calculation, the human data is calculated as shown in the figure.
It is left-justified, and the remaining part on the left side is filled with O's. In this case as well, since the O on the right side is not involved in the calculation, the C flag detects the carry from the O-th bit, 401, the N flag detects the value of bit O, 402, and the Z flag detects all O's in all 32 bits. (403) L, just reflect it. FIG. 5 shows a method for generating calculation flags in a conventional data processing device that performs calculations by right-aligning data. FIG. 5(a) shows a method for generating operation flags in addition of word-sized integer type data. C flag is O
Carry from bit 501. The N flag is the value of bit O, 502. The Z flag detects all O's in all 32 bits (
503) Reflect L/te. This case is the same as the embodiment of the present invention. FIG. 5(b) shows a method for generating operation flags in addition of halfword-sized integer type data. The C flag is the carry value 511 from the 16th bit of the register, and the N flag is the value 512 from the 16th bit, and 2
The flag detects all O's in the lower 16 bits (513) L
It is necessary to reflect this. Figure 5(a) shows a method for generating calculation flags in addition of byte-sized integer type data. The C flag is a carry from the 24th bit, 521.
, the N flag needs to have the 16th bit value 522, and the 2nd flag needs to detect all 0s in the lower 8 bits (523) and reflect it. As described above, according to the embodiment of the present invention, there is no need to have a calculation flag generation circuit for each data size.
The calculation flag generation circuit can be simplified. In addition, in the above explanation, we have explained the case of addition as the operation, but it is clear that there is no problem even in the case of subtraction or logical operations such as AND/OR, by adding O to the right side. .

Figure 6 shows the size conversion of integer type data in registers. Figure 6(a) shows how byte-sized data is converted to word-sized data. Byte-sized data is stored left-justified in the register, so if you want to expand it to word-sized data, just shift it 24 bits to the right. Here, if you want to consider the data as an unsigned binary number, just shift in 0 from the left side. Also, if you consider the data to be a signed binary number, just shift in the same value as the most significant bit from the left. Figure 6(b) shows how halfword size data is converted to word size. As with the case from byte size to word size, halfword size data is stored left-justified in the register, so if you want to expand it to word size, just shift it 16 bits to the right. Figure 6(c) shows how byte size data is converted to halfword size. In this case as well, byte-sized data is stored left-justified in the register, so if you want to expand it to half-word size, just shift it 8 bits to the right. As mentioned above, if you want to treat the data as an unsigned binary number, you can shift in O, and if you want to treat the data as a signed binary number, you can shift in the sign. These processes can be easily realized using the basic microprocessor instructions, the logical right shift instruction and the arithmetic right shift instruction. Conversely, if you want to convert long size data to short size data, just shift it to the left. In other words, when converting from word size to halfword size, all you have to do is shift in 0 from the right side and shift 16 bits to the left. Similarly, when converting from word size to byte size, shift to the left by 24 bits, and when converting from halfword size to byte size, shift to the left by 8 bits. Note that when increasing the data size as described above, the value shifted in from the left may always be O, regardless of whether the data is signed or unsigned. Therefore, this process also
This can be easily achieved using the left shift instruction, which is a basic microprocessor instruction. As described above, in the data processing device of the present invention, data size conversion can be easily realized using a shift command. In conventional data processing devices, it was necessary to specially provide a dedicated instruction for size conversion, but according to the present invention, it can be easily realized using basic shift instructions, so it is not necessary to provide a special instruction. There is no need to provide one, and the command system can be simplified. FIG. 7 is a block diagram of a data processing device which is an embodiment of the present invention described above. Data processing device 700
are registers Rl (711), R2 (712), R3
(713). It consists of a barrel shifter 720, an arithmetic unit 730, data length correction mask circuits 731, 732, a memory data register 740, a memory data aligner 741, a memory bus 742, and data buses 751, 752, 753.

Registers 711, 712, 713, 740, data buses 751, 752, 753, 742, and arithmetic units (7
20,730) has 32 bits (4 bytes), which is called the word size. Memory data register 740 is used as a buffer during data transfer to and from memory. The memory data aligner 741 is used to adjust the position of data when handling memory data that is not on 4-byte boundaries. The arithmetic unit 730 adds and subtracts left-justified data, and
Performs a logical operation and outputs the operation result and operation flag 760. The data length correction mask circuits 731 and 732 are circuits for inserting 0 into parts other than the left-justified data when calculating data of a size smaller than the word size. Note that in this embodiment, as described above, O is inserted using the data length correction mask circuits 731 and 732, but (1) when storing the calculation result in the register, the O on the right side is also written. (2) When reading short data from the memory, the data length correction mask circuit 7 can be
31,732 can also be omitted. Barrel shifter 720 is a circuit that executes processing corresponding to a shift command in one cycle.

Next, the operation of this embodiment will be explained using an example. Halfword size signed integer data stored in register 711 and byte size signed integer data stored in register 712 are added and stored in register 713 as halfword size signed integer data. Consider the case of storing. (1) The byte-sized signed integer data in register 712 is arithmetic shifted to the right by 8 bits using barrel shifter 720, and the result is transferred to register 712. Store it in . (2) The contents of registers 711 and 712 are input to an arithmetic unit 730 via buses 751 and 752, respectively, and added. At this time, the input data is processed by data length correction mask circuits 731 and 732 to 32
The right 16 bits of the bit data width are masked to 0 before calculation is performed. (3) Store the calculation result of the calculation unit 730 in the register 713. At the same time, the carry from the 0th bit of the operation result is set as a carry flag, the value of the 0th bit is set as a negative flag, and all O's of the entire 32 bits are detected and set as a zero flag. As described above, according to the embodiments of the present invention, data smaller than the data width of the arithmetic unit or register can be easily processed. [Effects of the Invention] As described above, according to the present invention, the register bit number does not change depending on the data size, so it can be treated in the same way as a memory bit number, and when creating a program, special This eliminates the need for caution and has the effect of reducing the probability that programming errors will occur. Furthermore, since the calculation flag generation circuit is not affected by the data size, the generation circuit can be simplified, reducing the circuit size and improving operating speed. Further, according to the present invention, even when the data size is further expanded, the bit numbering method can be easily expanded, and the calculation flag generation circuit does not need to be changed, so that the data size can be expanded. data. This has the effect of making it easier to migrate processing equipment.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a register of a data processing device which is an embodiment of the present invention, FIG. 2 is a diagram of a memory as well, FIG. 3 is a diagram of a register of a conventional data processing device, and FIG. 4 is a diagram of a register of a data processing device of the present invention. FIG. 5 is a diagram showing a calculation flag generation method in a data processing device that is an embodiment of the present invention. FIG. 6 is a diagram showing a calculation flag generation method in a conventional data processing device. FIG. 7, which is a diagram showing a data size conversion method in a processing device, is a block diagram of a data processing device that is an embodiment of the present invention. 100...Register, 700...Data processing device,
711, 712, 713... register, 720...
Barrel shifter, 730...Arithmetic unit. 731,732・
・・Mask circuit for data length correction, 740 ・・Memory data register, 741 ・・Memory data aligner, 7
42...Memory data bus, 751, 752, 753
...Data bus. No. ■ (α th mouth (b) 4 o 3 32 bis, toyotai ii (shi 11 = 4 now jl 2, ← 1 - 11 11 no V itto 1st half word mouth broom concave / DO register / o + ftr Itachibinoto 201 Saitabi 7th Homoku (α) 1st Horoscope (Siri No. S mouth (C) 6th mouth (α) Paito Ward 6th diagram (G) Half 7-Dou Ward 6th mouth (C ) No Vite - Half-Ward

Claims (1)

[Claims] 1. In a data processing device capable of processing data of multiple types of sizes as integer type data, the first size of the data is the same as the data width of a register in the processor. , the second size of the data is half the first size
, or one-fourth the size, and when the register is used as data of the second size, the upper side (left side) of the register is used. 2. In the data processing device according to claim 1, the bit numbers of the data are set such that the most significant bit is the 0th bit, and the bit numbers increase sequentially as the bits go to the lower (right side) side. A data processing device characterized by associating bit numbers. 3. In a data processing device capable of processing data of multiple sizes as integer type data, the first size of the data is the same as the data width of the arithmetic unit in the processor; The second size is half of the first size.
, or 1/4 the size, and when calculating data of the second size, data processing is characterized in that the data is left-justified and the calculation is performed using the upper side of the calculating unit. Device. 4. The data processing apparatus according to claim 3, wherein when the data of the second size is left-aligned and arithmetic is performed, 0 is inserted into the remaining part on the right side. 5. In the data processing device according to claim 3, when calculating data of the second size, the leftmost most significant bit of the calculation result of the calculation unit is set as a negative flag of the data calculation of the second size. A data processing device characterized by: 6. In the data processing device according to claim 3, when calculating the data of the second size, a carry from the leftmost most significant bit of the calculation result of the calculation unit is used as the data of the second size. A data processing device characterized by using a carry flag for calculation. 7. In the data processing device according to claim 4, when calculating the data of the second size, detecting zeros in all bits of the calculation result of the calculation unit, and calculating the data of the second size. A data processing device characterized in that a zero flag is set.