JP3043861B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly, to a microprocessor or the like which issues an instruction for moving a digit of data according to a specified data size, direction, and a specified number of bits smaller than the data size. The present invention relates to a data processing device provided.

[0002]

2. Description of the Related Art In recent years, with the advance of the technology for increasing the degree of integration of semiconductor integrated circuits, the functions of even small-sized instruction processors such as microprocessors have become more abundant. For example, Zilog's Z80 has a rich instruction set despite being an 8-bit microprocessor. Here, the Z80 is taken as an example, and a BCD type digit shift instruction, RLD instruction, and RRD instruction in 4-bit units, which are one of the instruction sets of the Z80, are referred to, and problems are pointed out.

The RLD instruction and the RRD instruction move right and left four bits at a time, and act on the contents of addresses in the memory indicated by the A register and the HL pair register, and are effective in operating BCD type data. It is.
The operation of these instructions is summarized in FIGS. 8 (1) and (2). That is, the lower 4 bits of the 8-bit A register are the upper group, the upper 4 bits and the lower 4 bits of the 8-bit data of the address indicated by the HL pair register are the lower group, and the upper group and the lower group are connected. Rotate right and left in 4-bit units. At this time, the data size of the data of the A register and the data of the address indicated by the HL pair register is fixed at 8 bits, and the number of bits to be rotated is also fixed at a unit of 4 bits.

For example, suppose that octal data is stored in a memory from address n to address n + m.
Assume that the data up to the address + m is shifted by 3 bits as a whole by the instruction of Z80.

As described above, since the rotate instruction is in units of 4 bits, first, an SLA (arithmetic shift) instruction is executed to shift "0" from the least significant bit of the 8-bit data at address n, whereby the A register The data shifted out from the seventh bit is stored in the carry flag. next,
An RL (left rotate) instruction is executed to rotate the carry flag concatenated to the uppermost position of the 8-bit data at the address (n + 1). As a result, the carry flag has n
The most significant bit of 8-bit data at address +1 is shifted and stored. Next, the one obtained by connecting the carry flag to the uppermost position of the address n + 2 by the RL instruction is rotated to the left again. By repeating the above procedure up to the address n + m, the data from the address n to the address n + m is shifted by one bit as a whole. Therefore, in order to shift by three bits, the above operation must be repeated three times, which requires a large number of instructions and cycles.

[0006]

As described above, the conventional data processing apparatus requires a large number of instructions and cycles when moving consecutive data by an arbitrary number of bits. However, there was a drawback that it took.

The present invention solves the above problems,
The purpose is to prepare an instruction to move the digit of data according to the specified data size, direction, and the specified number of bits smaller than the data size, and to speed up the operation to shift the digit of continuous data by an arbitrary number of bits. To provide a data processing device for processing.

[0008]

In order to solve the above-mentioned problems, a feature of the present invention is that, as shown in FIG. 1, first data storage means 1 having a width of n bits (n is an arbitrary positive integer); Second data storage means 3 having a width of m bits (m is an arbitrary positive integer)
An instruction register 5 for holding an instruction word, control means 7 for decoding and controlling the execution of the instruction in the instruction register 5, and an operation means 9 for executing the instruction.
When a predetermined instruction is decoded, the lower k bits of the first data storage unit 1 are set to an upper group according to the number of bits k (k is an arbitrary positive integer) and direction specified by the instruction word information, and the second All the bits of the data storage means 3 of the
The data obtained by concatenating the upper group and the lower group is shifted by k bits in the above direction, the upper k bits of the result are replaced with the lower k bits of the first data storage unit 1, and the remaining lower bits of the result are replaced with the second k bits. Is stored in the data storage means 3.

A second feature of the present invention is that in the data processing device according to the first aspect, the data processing device is realized on one chip.

[0010]

In the data processing device of the present invention, the instruction register 5
When the predetermined instruction is set in the first data storage unit 1, the control unit 7 sets the lower k bits of the first data storage unit 1 in accordance with the number of bits k (k is an arbitrary positive integer) and direction specified by the instruction word information.
Bits are defined as an upper group, and all bits of the second data storage means 3 are defined as a lower group. Data obtained by connecting the upper group and the lower group is shifted by k bits in the above-mentioned direction, and the upper k bits of the result are converted into the above-mentioned k bits. The remaining lower bits of the result are stored in the second data storage unit 3 in the lower k bits of the first data storage unit 1.

Thus, an instruction for shifting the digit of data is prepared according to the number of bits k and direction specified by the instruction word information, and the operation of shifting the digit of continuous data by an arbitrary number of bits is processed at high speed. can do.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a configuration diagram of a data processing apparatus according to one embodiment of the present invention.

The data processing apparatus of this embodiment comprises a 16-bit microprocessor 10 (hereinafter abbreviated as MPU) and a 16-bit memory 30 with one word connected thereto via a data bus 27 and an address bus 29. ing.

The MPU 10 manages an interface with the memory 30, and includes a data latch DR, an address latch AR,
And a bus interface unit 13 including temporary registers TR0 and TR1 (hereinafter abbreviated as BIU)
An instruction register group 5 including four instruction registers IR1 to IR4, an instruction decoder 6 for decoding instructions from the instruction register group 5, a bank pointer BP, various stack pointers SP, and register groups R0 to R15. A general-purpose register group 11, a constant ROM 15 for holding constants used in operations and the like, an operation unit 9 for executing various operations, a shift register SR1 connected to the input side of the operation unit 9 and used for a digit shift instruction and the like. SR2, and each component exchanges data via an X bus 21, a Y bus 23, and a Z bus 25. In FIG. 2, thick lines indicate signal lines for exchanging buses or data, and thin lines indicate signal lines for control signals and the like.

In the data processing device of the present embodiment, each instruction is executed as follows.

First, an instruction is fetched from the memory 30 to the data latch DR in the BIU 13 via the data bus 27. Next, the fetched instruction is fetched into a queue of the instruction register 5. Here, the instruction register group 5 is 4
A queue is formed by the instruction registers IR1 to IR4. This is to speed up data processing by prefetching an instruction and taking it into the queue when there is no bus access. Next, the instruction decoder 6 sequentially fetches instructions from the queue of the instruction register group 5, decodes the instructions, and sends the information to the control unit 7. The control unit 7 sends a control signal to each component based on the information to execute the command. The control unit 7 receives signals from the arithmetic unit 9, the BIU 13, and other components, and returns a control signal to each component. X bus 21, Y bus 2
3 and a program status word (P) including a condition code (CC) via the Z bus 25.
SW) and the like.

Next, the specification of the digit shift instruction executed in this embodiment will be described with reference to FIG.

First, as for the RML (Rotate Multibit Left) instruction, assuming that the digit shift bit width specified by the instruction word is k bits, the general data register Rn is used as the first data storage means 1.
(N = 0 to 15) and the lower k bits of the general-purpose register Rn and the general-purpose register using the general-purpose register Rm (m = 0 to 15) or a specific address of the memory 30 as the second data storage means 3, respectively. Rm or all bits of the memory 30 are concatenated and rotated to the left by k bits. The specific address of the memory 30 is, for example, a general-purpose register Rj (j =
0 to 15; j ≠ n).

Further, RMR (Rotate Multibit Right)
The instruction rotates the specified k bits to the right, similarly to the RML instruction.

The manner in which the RML or RMR instruction is executed will be described with reference to FIG. FIG.
If the data storage means 1 is a general-purpose register R0 and the second data storage means 3 is a specific address (address m) of a memory, the shift registers SR1 and SR2 when executing the RML instruction (10-bit shift). FIG. 6 is a diagram for explaining the transition of the calculation and the state of the arithmetic processing of the arithmetic unit 9.

First, the data of the general-purpose register R0 is transferred to the shift register SR1 via the X bus 21 (FIG. 4).
(See (1)). At the same time, data corresponding to the address m output from the address latch AR is transferred to the shift register SR2 via the data bus 27 and the Y bus 23 (see FIG. 4 (2)). Next, the data of the shift register SR1 is shifted rightward by 10 bits as shown in FIG.
After shifting to the left by 0 bits, the contents of the shift registers SR1 and SR2 are as shown in FIGS. 4 (4) and (5). The data in the shift registers SR1 and SR2 are transferred to temporary registers TR0 and TR1 in BIU 13, respectively.
To store temporarily.

Next, from the constant ROM 15, data of the designated bit width in which the lower 10 bits are "1" and the remaining upper bits are "0" and the data of the general-purpose register R0 are transferred to the arithmetic unit 9, and As shown in FIG. 4 (6), the logical product (AND) of them is obtained. Further, as shown in FIG. 4 (7), the logical sum (O) of the result of this logical product and the data of the shift register SR2 temporarily stored in the temporary register TR1
Take R).

The result of the logical sum is stored at address m of the memory 30, and the data of the shift register SR1 temporarily stored in the temporary register TR0 is transferred to the general-purpose register R0.

The RML instruction is executed by the above operation, and the same is applied to the case of the RMR instruction.

Next, an application example when the data processing device of the present embodiment is used specifically will be described.

FIG. 5 shows a first application example, in which the first data storage means 1 is a general-purpose register Rn, the second data storage means 3 is a memory 30, and the lower 10 bits of the data at address m in the memory 30. The lower 10 bits of data of the general-purpose register Rn are inserted into the bits, the upper 10 bits of the address m are moved to the lower 10 bits of the address m + 2, and the subsequent addresses are sequentially shifted.

First, in FIG. 5A, the general-purpose register R
n (data A is stored in lower 10 bits) and m
The data at the address is rotated to the left by 10 bits using an RML instruction. The general register Rn contains the top 10
Bit data B is stored, as shown in FIG. Next, the general-purpose register Rn and the data at address m + 2 are rotated to the left by 10 bits using an RML instruction.
At this time, the data C of the upper 10 bits of the address m + 2 is stored in the general-purpose register Rn, as shown in FIG.
Similarly, the general-purpose register Rn and the data at address m + 4 are set to RM
Using the L instruction to rotate 10 bits to the left, FIG.
As shown in (4), the upper 10 bits of data D at address m + 4 are stored in the general-purpose register Rn. Finally, the general-purpose register Rn and the data at address m + 6 are rotated 10 bits to the left using an RML instruction, and the final state shown in FIG. As described above, successive digit shifting operations can be performed only by repeating the same command.

FIG. 6 is a diagram for explaining the operation of the second application example. In this example, the first data storage unit 1 is a general-purpose register Rn, the second data storage unit 3 is a memory 30,
And the lower 10 bits of the data at address m + 6 of the memory 30 are stored in the lower 10 bits of the general-purpose register Rn.
In this process, the lower 10 bits of the data at address m + 6 are moved to the upper 10 bits at address m + 4 and sequentially shifted to the immediately preceding address.

This is the same as the first application example, except that rotation is performed to the right by 10 bits using the RMR instruction. Thus, the RMR instruction is effective when data is moved from a lower address to an upper address.

Next, FIG. 7 is a diagram for explaining the operation of the third application example. In the present example, the first data storage means 1 is a general-purpose register Rn, the second data storage means 3 is a continuous general-purpose register Rm to Rm + 3, and the lower 10 bits of the general-purpose register Rm are replaced with the lower 10 bits of the general-purpose register Rn. , The data of the upper 10 bits of the general-purpose register Rm is moved to the lower 10 bits of the general-purpose register Rm + 1, and the subsequent general-purpose registers are sequentially shifted.

In FIG. 7A, when lower 10 bits of data A of the general-purpose register Rn and data of the general-purpose register Rm are rotated to the left by 10 bits using an RML instruction, as shown in FIG. The general-purpose register Rn includes:
The upper 10-bit data B of the general-purpose register Rm is stored. Next, the data B of the general-purpose register Rn and the data of the general-purpose register Rm + 1 are rotated to the left by 10 bits using an RML instruction. At this time, the higher-order 10-bit data C of the general-purpose register Rm + 1 is stored in the general-purpose register Rn, as shown in FIG. Similarly, data C of general-purpose register Rn and data of general-purpose register Rm + 2 are represented by R
Using the ML instruction to rotate 10 bits to the left, FIG.
As shown in (4), the higher-order 10-bit data D of the general-purpose register Rm + 2 is stored in the general-purpose register Rn. Finally, the data of the general-purpose register Rn and the general-purpose register Rm + 3 is rotated to the left by 10 bits using an RML instruction, and the final state shown in FIG.

As in the case of the second application example, it is also possible to perform a digit shift operation of a continuous general-purpose register by using an RMR instruction.

As described above, in the data processing apparatus of the present embodiment, in the digit shifting operation between the first and second data storage means 1 and 3, the second data storage is performed in the case of right rotation. In the case of the left rotation, the data of the lower bits corresponding to the specified number of digit shifts of the means 3 is replaced with the first data of the upper bit corresponding to the specified number of digit shifts of the second data storage means 3. Since the data is stored in the lower part of the storage means 1 and can be used as shift data in the next rotate instruction, the digit shift operation of the data in the continuous memory or general-purpose register can be performed only by repeating the same instruction. For example, in a document processing such as a word processor, when performing a lexical insertion operation or the like, an operation as in the application example described above is performed at the assembler instruction level, but conventionally, a large number of instructions and cycles are required. Can be processed at high speed with a small number of instructions.

The data size can be set arbitrarily, and the number of bits for digit shift can be arbitrarily specified as long as the number of bits is smaller than the data size.

[0036]

As described above, according to the present invention, according to the number of bits k and the direction specified by the instruction word information, the lower k bits of the first data storage means are set to the upper group, and the second data storage means is set. , And the concatenated data is shifted by k bits in the designated direction, the upper k bits of the result are stored in the lower k bits of the first data storage means, and the remaining lower bits are stored in the second data storage means. Since the instruction to be stored in the means is prepared in the instruction set, the digit can be shifted in an arbitrary direction in an arbitrary bit unit, and the data can be processed at a high speed, such as an operation of shifting consecutive data by an arbitrary number of bits. A processing device can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a configuration diagram of a data processing device according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a specification of a digit shift instruction in the embodiment of the present invention.

FIG. 4 shows an RML instruction or RM according to an embodiment of the present invention.
FIG. 9 is a diagram for explaining an execution process of an R instruction.

FIG. 5 is an operation explanatory diagram illustrating a first application example of the embodiment of the present invention.

FIG. 6 is an operation explanatory diagram illustrating a second application example of the embodiment of the present invention.

FIG. 7 is an operation explanatory diagram illustrating a third application example of the embodiment of the present invention.

FIG. 8 is an explanatory diagram of a specification of a digit shift instruction in a conventional microprocessor (Z80).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st data storage means 3 2nd data storage means 5 Instruction register (instruction register group) 6 Instruction decoder 7 Control means (control part) 9 Operation means (arithmetic unit) 10 Microprocessor (MPU) 11 General-purpose register group 13 Bus interface unit (BIU) 15 Constant ROM 21 X bus 23 Y bus 25 Z bus 27 Data bus 29 Address bus 30 Memory DR Data latch AR Address latch TR0, TR1 Temporary register IR1 to IR4 Instruction register BP Bank pointer SP Various stack pointer R0 To R15 General-purpose register SR1, SR2 Shift register

Continuation of front page (56) References JP-A-64-81033 (JP, A) JP-A-62-93729 (JP, A) JP-A-53-76721 (JP, A) JP-A-62-58338 (JP, A) , A) "Z8000 User's Manual [1] CPU / MMU Edition", 1st edition, Sharp Corporation, July 1983, p. 1-173, 1-177 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 9/30-9/355 G06F 7/00

Claims (2)

(57) [Claims] 1. A first bit having a width of n bits (n is an arbitrary positive integer)
A second data storage unit having a width of m bits (m is an arbitrary positive integer), an instruction register for holding an instruction word, and a control unit for decoding and controlling the execution of the instruction in the instruction register. And an arithmetic unit for executing an instruction. The control unit, when decoding a predetermined instruction, sets the first data according to the number of bits k (k is an arbitrary positive integer) and direction specified by the instruction word information. The lower k bits of the storage means are defined as an upper group, all the bits of the second data storage means are defined as a lower group, and the data obtained by connecting the upper group and the lower group is shifted by k bits in the above direction. A data processing apparatus, wherein bits are stored in the lower k bits of the first data storage means, and the remaining lower bits of the result are stored in the second data storage means. 2. The data processing device according to claim 1, wherein the data processing device is realized on one chip.