JPS58178464A - Parallel arithmetic processing unit - Google Patents

Abstract

PURPOSE:To eliminate the need for restoring operation and to eliminate a decrease in processing speed due to the restoration, by providing every arithmetic device with a register for storing its arithmetic result temporarily, and performing writing to a storage device in the order of general conception. CONSTITUTION:An instruction number generator 4 generates an instruction number which indicates general order for every instruction decoded by an instruction decoder 2. The decoded information and instruction number of an instruction word from an instruction control unit and a corresponding operand from a storage device 5 are set up in an arithmetic unit 6 or 9. Its arithmetic result is stored in a result register 13 or 16. When the arithmetic result is stored in the register 13 or 16, a order control circuit 20 decides in the writing order of the general conception and sends out a writing indication command for the arithmetic result in the register 13 or 16 through signal line 38 and 39.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to computers, such as so-called general-purpose computers, which conceptually process instructions one by one. This paper relates to a control method that is important in realizing a method for calculating.

Among computers that conceptually process instructions one by one, this is one of the conventional examples of computers that operate on multiple instructions in parallel using multiple arithmetic units.

There is Cray 1 from Cray Research in the United States. In Cray 1, two conceptually ordered instructions can be operated on different arithmetic units, so the writing order of the results may be the opposite of the conceptual order.

In IBM's 370 architecture.

When the reversal of the writing order of results occurs, as occurs in Cray 1, several problems arise. This problem is
Conceptually, when writing the result of the preceding instruction, that is, when execution is complete, it becomes necessary to interrupt the processing of the succeeding instruction, and at the time of execution, the result of the succeeding instruction has already been written to the storage device.

This arises from the fact that according to the specifications of this architecture, the storage device must be restored to the state immediately before being changed by a subsequent instruction. To do this, save the data in the field that would be lost due to the #''t1 write if result omitting may be disabled, and then
If it is necessary to restore to the previous state, it will take nine operations to save and rewrite the friend data.

There are cases where this kind of operation itself is performed in conventional models for other reasons, but the control becomes complicated,
This method has several drawbacks, such as an increase in the number of hardware items and the time required for restoration, which slows down the processing speed if restoration occurs frequently. In a system that performs parallel operations and allows the reversal of the writing order of results, the restoration operation described above is necessary.

When an interrupt occurs, a predicted instruction on a stream is processed before a one-branch decision is made in a branch instruction.

Although it is thought that interrupts occur less frequently, branch instructions occur very frequently, and if the above-mentioned restoring operation is required at this time, the reduction in processing speed cannot be ignored and becomes a problem.

The present invention eliminates the need for the above-described restoration operation in order to improve processing speed through parallel computation.

Therefore, easier to control and less hardware.

Another object of the present invention is to provide a computer in which the processing speed does not decrease due to restoration operations.

The principle of the present invention is to eliminate the inversion of the resulting writing order itself, which would require a restoration operation. That is, a register is provided for each of a plurality of arithmetic units to temporarily store the results of the arithmetic operations, and the registers are made to wait for their turn to be written to the storage device. Writing to storage follows a conceptual order.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of an instruction processing device in a computer to which a parallel arithmetic processing method according to the present invention is applied.

Reference numeral 1 denotes an instruction control unit that decodes instruction words, reads operands, etc., and includes an instruction decoder 2, an operand reading device 3, an instruction number generator 4, and the like. This is a 5Vi storage device in which instructions, operands, etc. are stored. 6 is an arithmetic unit that performs nine operations specified by a command word, and arithmetic units 7. It consists of 8 registers. 9 is also an arithmetic unit similar to 6, and consists of an arithmetic unit 10 and a register 11. 1
2 is an order control unit that controls the writing order of performance results. 12 are result registers 13 and 161 instruction number registers 14 and 17 . Valid flags 15 and 18,
Selector 19. It consists of a sequence control circuit 20.

The nine instruction words read from the storage device 5 are input to the instruction decoder 2 via the signal line 21 and decoded. The operands required for the operation specified by the instruction word are retrieved from the storage device 5 by the operand reading device 3 sending an operand read request to the storage device 5 via the signal line 22.
is read from. The nine operands read from the storage device 5 are sent to the arithmetic unit 7 or 10 via the signal line 23. Among the information obtained as a result of decoding the instruction word by the instruction decoder 2, the information necessary for the execution of the operation is transmitted to the signal line 24.
The signal is sent to the arithmetic unit 7 or 1o via.

The instruction number generator 4 indicates the conceptual order of each instruction decoded by the instruction decoder 2. An instruction number is generated and sent to the register 8 or 11 via the signal line 25. The instruction number generator 4 initially sets the value 1 as the instruction number for the first instruction to be executed by the instruction processing device, and thereafter increases the value by 1 each time one instruction is decoded. Number. However, in order to represent the instruction number with a finite number of digits, if it is transferred to an appropriate foot N.

Assume that the next instruction number is returned to the value 1. By selecting a value larger than the maximum number of instructions that may be continuously decoded for any given instruction as the number of legs N, the number of instructions given the same instruction number can be set to 2. It is possible to prevent more than one tongue 11 instar from being processed.

C is necessary to ensure the order of writing of the calculation results using the % postage number.

In this implementation, the computing unit 7. It is assumed that all IOs are configured so that they can execute all instructions. Therefore, either n of arithmetic unit 6 or 9
If one of the units is empty (not executing an operation), the command control unit 1 will send the command to the appropriate unit. The word decoding information, the instruction number, and the corresponding operand are set up from memory &5. If we consider an embodiment in which the configurations of the arithmetic units 7.10 are not the same, and only one of the arithmetic units can execute the derivation of a 1% step instruction.

The set-up of such an instruction decoded by the instruction control unit 1 must be configured to be performed on the arithmetic unit after the arithmetic unit capable of executing the instruction becomes free. .

Assuming that an instruction is set up for the arithmetic unit 6, the arithmetic unit 7 executes the operation specified by the instruction word. During this time, the instruction number of the instruction is held in the register 8.

When the execution of the calculation is completed and the valid flag 15 shows the value 0, the calculation result is sent out from the y4 calculator 7 via the signal line 26 and stored in the result register 13.

The instruction number is sent from register 8 via signal @27.
, are stored in the instruction number register 14, and furthermore, the arithmetic unit 7
A calculation result sending command is sent from the signal line 28, thereby setting the value of the effective 7 lag 15 to 1. The valid 7 lag 15 indicates whether or not the result register 13 stores an operation result that has not yet been written.When the value is 0, it means that no operation result that has not yet been written is stored. When the value is 1, it means that it is stored. When the calculation result is stored in the result register 13,
The arithmetic unit 6 becomes vacant.

Furthermore, if instructions are set up for the arithmetic unit 9, the arithmetic unit 10 executes the arithmetic operation specified by the instruction word. During this time, the instruction number of the instruction is held in the register 11.

When the calculation execution is completed and the valid flag 18 shows @0, the signal ! from the calculation unit 10 is sent. The execution result is sent out via 29t and stored in the result register 16, and the instruction number is sent out from the register 11 via the signal @30 and stored in the instruction number register 17.

Furthermore, a calculation result sending command is sent from the calculation unit 10 via the signal line 31, thereby setting the effective slug 18 to the value ti. The valid flag 18 is set to f1 in the result register 16.
! This indicates whether or not an uncompleted operation result is stored, and the meaning of the value is the same as that of the valid flag 15. When the calculation result is stored in the result register 16, the calculation unit 9 becomes vacant.

The contents of result registers 13 and 16 are stored on signal line 3, respectively.
2 and 33 to the selector 19. Also,
The contents of instruction number registers 14 and 17 are further transmitted to valid flags 15 and 1 via signal lines 34 and 35, respectively.
The values of 8 are input to the sequence control circuit 20 via signals @36 and 37, respectively.

When an operation result is stored in the result register 13 or 14, the order control circuit 20 determines the writing order by a method described later, and stores the operation result in the result register 13 or 16 via signal lines 38 and 39, respectively. Sends a result write instruction command.

When a command to write the operation result in the result register 13 is issued, it is sent to the valid 7 lag 15 via the signal line 38, this value is set to O, and it is also sent to the selector 19, so that the contents of the result register 13 are written. Force output. Also, when a command to write the calculation result in the result register 16 is issued, it is sent to the valid flag 18 via the signal line 39, this value is set to O, and it is also sent to the selector 19.
The contents of the result register 16 are output. Since writing is performed according to a conceptual order, the order control circuit is configured so that write instruction commands are not issued on both signal lines 38 and 39 at the same time. When a scan instruction command is issued on either of the signal lines 38 and 39, at the same time, a write instruction command for the calculation result is sent to the storage device 5 via the signal line 40, and at this time, the selector 19 The calculation results that should be collected from the output are sent to the storage device 5 via the signal line 41. In the storage device i15, when a write instruction command is sent via the signal +i14 (l), the calculation result sent via the signal line 41 is written.

FIG. 2 shows one embodiment of the order control circuit 20.

100 is a write instruction number circuit, which initially sets the value 1 as the write instruction number for the first instruction to be executed in the instruction processing device, and thereafter sets the value 1 by 1 every time one instruction is committed. The incremented number is generated as the input instruction number.

However, when the above-mentioned constant N giving the upper limit of the instruction number is reached, the primary write instruction number is returned to the value 1.

The write command number is sent to the comparator 102 via the signal line 101.
, 103. The instruction number in the instruction number register 14 is inputted to the instruction number register 102 via the signal line 34, compared with the write instruction number, and the comparison result is sent to the AND gate 105 via the signal line 104. If the comparison results match, the value of 104 is 1. If there is a mismatch, the value is set to 0.

The value of the valid flag is input to the AND gate 105 by the signal @36.
f, and the logical AND with the comparison result of the comparator 102 is output on the signal line 38.

In other words, the signal line 38 takes the value 1 when the result register 13 stores an operation result that has not been written yet, and the instruction number stored in the register 14 matches the write instruction number. be.

Similarly, the instruction number in the instruction number register 17 is inputted to 103 via the signal line 35, compared with the write instruction number, and the comparison result is sent to the AND gate 103 via the signal line 106.
Send on 07. If the comparison results in a match, the value Vii is set to 106, and if they do not match, the value is set to O. AND gate 10
7, the value of the valid flag is input manually via the signal line 37, and the logical product with the upper self comparison result of the comparator 103 is output as the signal @3.
It is output on 9. In other words, the reason why the signal ff1A39 takes the value 1 is because the result register 16 stores the unwritten fi4 result, and the instruction number stored in 17 matches the write instruction number. This is the case.

A write instruction command for the contents of the result register 13 and 16 is input to the OR gate 108 via signal lines 38 and 39, and the logical sum of these is output onto the signal line 40. The signal line 40 is.

As mentioned above, the command is for sending the write instruction command of the calculation result to the storage device 5, but furthermore,
It is also connected to the pledge instruction number circuit 100. When a write instruction command is issued to the storage device 5, writing of the instruction having the instruction number equal to the value indicated by the write instruction number circuit 100 is deemed to have been completed, and the write instruction number is incremented by 1 as described above. However, as described above, if the value after increase exceeds N, the value is set to 1.

By configuring the order control circuit 20 as described above, even if the order in which the operation results are stored in the result registers 13 and 16 is different from the conceptual order, writing to the memory device ft5 is performed according to the conceptual order. Can be done in order.

According to the present invention, while achieving a reduction in execution unit overhead through parallel operations, it is possible to prevent erroneous writes to the storage device that may occur when branch instruction prediction failures or interrupts occur, and to prevent erroneous writes from occurring when erroneous writes occur. This eliminates the need for a restore operation of the storage device that otherwise would have been necessary, and ultimately prevents a decrease in processing speed due to such a restore operation.

In other words, in a computer that implements an architecture that executes instructions and instructions sequentially, such as the IBM System 370, the above processing becomes a problem when introducing a parallel operation method to improve processing speed. This is effective in eliminating factors that reduce speed and ensuring improved performance through parallel computing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer instruction processing device implementing a parallel operation method according to the present invention. FIG. 2 shows an embodiment of the order control circuit 20 in FIG. 1... Instruction control unit, 4... Instruction number generator,
5...Storage device, 6.9...Arithmetic unit, 12.
...Sequence control unit, 13.16...Result register, 14°17...Instruction number register, 40...Sequence control circuit.

Claims (1)

[Claims] 1. Conceptually, each instruction is processed one by one, and the result is conceptually 1/
In a data processing device in which data is sequentially written into a storage device, there is provided an instruction control means for decoding instructions and reading operands, a plurality of arithmetic means capable of performing instructions S in parallel, and each an operation result storage means for writing the operation result obtained by the enactment means into a storage device and storing it in a storage device; 1. A parallel arithmetic processing device, comprising a write order control means for writing to the device. 2. In the parallel arithmetic processing device, an instruction number representing a conceptual order is assigned to each instruction, and the instruction number is stacked at 1 where the instruction is written in the arithmetic result storage means, and the writing order is determined by The control means has means for identifying an instruction number given to the conceptually earliest instruction among a plurality of instruction numbers stacked in the control means as a write instruction number, and the write instruction number K is an instruction corresponding to a matching instruction number. 2. The parallel processing device according to item 1, wherein when a calculation result exists in the calculation result storage means, it is read out and written to a storage device, thereby realizing writing according to a conceptual order.