JP3153906B2 - Computer distributed pipeline control apparatus and method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates generally to computers and, more particularly, to efficient pipeline control of computers.

A single-cycle implementation of a complex instruction set computer (CISC) architecture requires a deep pipeline. CI
The complexities of the complex privilege and protection checks and powerful memory management systems directly supported by the SC architecture, combined with ordinary pipeline technology, are extremely complex.
With current technology, the pipeline must include the effects of multiple chip boundary crossings. High levels of VLSI integration have been chosen to eliminate as much of these intersections as possible.
If the system contains only a relatively small number of devices,
There are not enough signal pins to run a dedicated bus for all purposes. This means that the bus must be used for multiple purposes, thus greatly increasing the complexity of the central control and scheduling mechanism design process.

SUMMARY OF THE INVENTION The present invention provides a pipeline control system distributed across functional units in a processor. Each unit defines its own interlock and pipeline timing. This timing is not accurately monitored in the centralized controller. Because the functional units are autonomous, there is no need to know exactly how all other units process each instruction, and complex simulations of pipeline timing are greatly reduced. The present invention allows for backout of changes to machine state that must not occur,
Support distributed control of pipeline. The present invention uses generalized techniques rather than complex special pipeline control logic, thereby making the correct operation of the pipeline more promising. Distributed control combined with the ability to back out unwanted changes can provide significant advantages in performance in the area of out-of-order execution, penalty cycles, and parallel processing of instructions within and between functional units. The additional cost and complexity of implementing these capabilities is very low.

Specifically, the decoder logic issues pseudo-operations (p-ops or p-ops), each having an associated tag, to a plurality of functional units that can independently perform p-ops. At any time, up to n p-ops can be outstanding. Tags are issued sequentially so that the relative age (time) of the two outstanding p-ops can be determined.
In certain embodiments, tags are issued and recycled over a range of at least 2n. This range is sufficient to make the relative age determinable by simple subtraction. In this embodiment, 16 tags are issued and 7p-op
s is allowed to be outstanding.

Unpaid p-ops retire in their issuance order. p-ops
Can be retired only when it has been completed, ie normally only when it has been terminated by all relevant functional units. In some cases, completed p-ops, which would otherwise be eligible for retirement, are held open until one or more adjacent young p-ops are also completed. Since the oldest unfinished p-ops tag is communicated to the functional unit,
Each unit can determine when the state of the machine can be irrevocably changed.

Unpaid p-ops are aborted if they are abnormally terminated by a functional unit. Old p-ops
If their retirement is conditioned on the successful completion of the abnormally terminated p-op, it can be aborted. The oldest unpaid p-op tag to be aborted is communicated to the functional unit. This allows for unexpected program detours and abort execution if the machine is returned to the detour point.

In the case of an instruction set architecture in which there are m programmer-visible (virtual) registers and up to n register modification p-ops are allowed, at least (m + n) physical registers are provided. . A mechanism is provided for mapping a virtual register into a physical register. This mapping is modified to use the previously unused physical register as the destination of each p-op that changes the virtual register, so that the value of the old virtual register is stored in the physical register to which it was previously mapped. Can be held. If the physical registers replaced in the mapping are reused in order, the p-ops mapped to certain virtual registers will be retired or aborted until some physical registers must be reused. There are enough physical registers to guarantee that. Since a set of pointers and a list of available registers that define the virtual-to-physical mapping are maintained for each of the n most recently issued p-ops, any outstanding p-ops are truncated and data is transferred between registers. The virtual register can be returned to the previous value without being moved.

Another technique that allows returning the state of a processor requires the use of write queues. At least outgoing p-op (p-op for generating address and data)
During the period during which the write reservation is pending, the write reservation queue buffer writes to the memory or data cache. Processing is
The write reservation queue entry is output to the memory only when the memory write has passed a point that may need to be backed out. If the outgoing p-op is aborted, the queue entry is removed from the queue. Young read p-
When the op searches for access to the memory location written by the pending write p-op, the data stored in the write reservation queue is provided to the read p-op. If write p-op retires, read p
-Op obtains correct data without waiting for retirement. Conversely, if the write p-op is aborted, the young read p-op is also aborted and the machine state is successfully returned to the point before the write.

A better understanding of the nature and advantages of the present invention will be realized by reference to the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a computer system incorporating the present invention; FIG. 2 is a high level block diagram of a decoder (DEC); FIG. 3 is a detailed block diagram of DEC; 5 is a detailed block diagram of DEC, FIG. 5 is a detailed block diagram of DEC, FIG. 6A-B is a block diagram showing tracking of a specific sequence, and FIG. 7A-B also shows tracking of a specific sequence. FIG. 8 is a schematic diagram showing register reallocation, FIG. 9 is a block diagram of a memory and cache controller (MCC), and FIG. 10 is a block diagram of an integer execution unit (IEU).

FIG. 11 is a continuation of the block diagram of the integer execution unit (IEU) of FIG.

BRIEF DESCRIPTION OF THE TABLES Table 1 shows a p-op bus format, Table 2 shows a physical address bus (PAdeBus) format, Table 3 shows a data cache bus (DIOBus) format, and Table 4 shows a data exchange bus (DXBus) format. Table 5 shows the IEU termination bus format, Table 6 shows the AP termination bus format, and Table 7 shows the sequence of the p-op issue and termination.

FIG. 1 is a block diagram of a CPU 10 incorporating the present invention. The CPU, sometimes called the F86, comes from Intel Corporation of Santa Clara, California, 19
It is designed to execute an instruction set (macro instruction) that is compatible with the Intel 80386 instruction set described in the Intel 80386 Programmer's Reference Manual published in 1986. Each block in the figure generally corresponds to a separate integrated circuit chip or group of chips as currently embodied. The CPU communicates via the system bus 11 with external devices such as memory controllers, I / O devices, and possibly other CPUs. Reference numbers at the bottom of the functional units should be understood to mean those elements within CPU 10 that are not these external devices.

An instruction decoder (DEC) 12 performs instruction fetch, instruction decoding, and pipeline control. DEC 12 optionally interleaves instruction prefetching for up to three simultaneous instruction streams. DEC 12 includes a fully associative branch prediction cache (BPC) 13. The BPC has an integrated structure, and includes branch history data, a physical branch target address, and a branch target buffer for each cache memory. When a branch instruction is decoded, the BPC looks up information about the branch.
Regardless of the predicted direction, the branch is executed during a single cycle and does not create a pipeline bubble.

Each cycle, a macro instruction is selected from one of three instruction buffers or branch target buffers in the BPC. This macro instruction is decoded, and the pseudo-op (p-op)
Or internal 96, sometimes called an instruction or operation
Assembled into bit-decoded instructions and dispatched to various functional units. Instruction decoding generally proceeds at a single cycle rate. Each p-op issued by DEC 12 is given a tag that uniquely identifies each p-op currently outstanding in the machine. The tags are issued in ascending order so that the relative age of any two tags can be easily determined. Bus transactions between chips include the tag of the originating p-op. The functional unit pairs a p-op, an address, and an operand with these tags.

DEC 12 is also responsible for tracking the status of outstanding p-ops, controlling the pipeline, and invoking exception handling as needed.

An address preparation unit (AP) 15 calculates the execution address, performs segment relocation, and implements a memory management system that is paged on demand. The AP includes a translation lookaside buffer (TLB).

Integer execution unit (IEU) 17 performs single cycle execution of most integer instructions. The IEU contains 8x32 multiplier and accumulator arrays, as well as microcode for multiply and divide instructions. The pipeline control architecture is IEU
And / or out-of-order execution of integer instructions.

A numerical processor (NP) 20 can optionally be included in the CPU. This implements the IEEE floating point standard with high performance. NPs are integrated in the pipeline and do not impose any special overhead on instruction and operand transfers. Integer (IEU) and floating point (NP) instructions are performed simultaneously.

The memory and cache controller (MCC) 25 is responsible for controlling the instruction and data cache and implements a cache coherency protocol. The MCC controls the interface to the system bus 11 to support high speed single and block mode transfers between cache and memory. As described below, the MCC also includes a write reservation table for integer, floating point, and system writes, and includes a read-after-write short circuit path.

The instruction cache subsystem uses a tag RAM chip (ITA
G) 27 and a cache RAM chip (ICACHE) 30. IT
Each entry in AG 27 includes an address tag, a valid bit, and an attention bit for the corresponding line in ICACHE 30. The attention bit indicates that the DEC chip can also have data from this line cached in the BPC. ITAG 27 also includes a set of instruction stream address registers 31, each register containing a fetch address associated with each of the three possibly outstanding streams.

The data cache subsystem uses a tag RAM chip (D
TAG) 32 and a cache RAM chip (DCACHE) 35.
DTAG 32 includes an address tag and line status bits for each line in DCACHE 35. Possible line states are missing,
Shared read, owned clean, and owned dirty, write-back multiprocessor cache coherency protocol (modified once write)
To help. Tag RAM is dual ported, allowing both the CPU and the bus to snoop cache lookups during a single cycle. Data cache interface (DCI) chip 37 is DCACHE 35
To the system bus 11.

Each functional unit is a custom ceramic PG containing power and ground planes and associated decoupling capacitors.
Packaged in A. Almost 25% of the pins are dedicated to power and ground. For 0.8 micron to 1.2 micron processes, the I / O delay is comparable to the on-chip critical path. The chip-to-chip I / O does not add cycle time to the machine because it is built into the pipeline. ICACHE 30 and DCACHE 35 use ordinary static RAM.

Communication between the various functional units is performed via a number of internal buses. These include a 64-bit IF for fetching instructions
ETCH_DATA bus 50, 104-bit p-op bus 52 for communicating issued p-ops to AP, IEU, MCC and NP, 5-bit tag status bus for communicating pending p-ops information to AP, IEU, MCC and NP 53, 32-bit physical address bus (PAdrBus) 55 for communicating physical addresses, 64-bit data cache transfer (32 bits in each direction) data cache bus (DIOBus)
s), 32-bit data exchange bus (DXBus) for chip-to-chip exchange
58, 64-bit bus for cache / memory updates, and multiple end buses (ie, APs from each functional unit to DEC 12)
End bus 60, IEU end bus 62, NP end bus 63, and MCC end bus 65) are included. Some of these busses are full width and some are half width (time multiplexed). In general, interaction between functional units is limited to well-defined transactions on the internal processor bus.

The details of the plurality of these buses will be described later. standard
According to the method of using the CMOS style time multiplexed I / O, the transfer is performed in phase 1 (φ1) and phase 2 of the system clock.
(Φ2).
φ2 transfer requires that the transmitting chip prepare valid data for its I / O driver before the end of φ1. Valid data is provided by the I / O receiver of the receiving chip during the following φ2. φ1 transfer is just the opposite timing.

Tables 1 to 6 respectively show a p-op bus 52, a PAdrBus 55, and a DIO
The bus formats of the Bus 57, DXBus 58, IEU end bus 62, and AP end bus 60 are shown.

Overview of the Pipeline Control System The pipeline control of the processor is distributed across the functional units described above. No centralized scheduling or scoreboarding of the pipeline is performed.
DEC 12 observes some overall resource constraints in the architecture and timely delays issuing p-ops that violate resource limits. Each functional unit is responsible for scheduling its own internal operations. Interlock checking is performed at the local level.

In deeply pipelined machines, exception detection at various stages of the pipeline introduces significant control difficulties. Each stage must be careful in delaying the change of state while the other stages can still detect the exception to the preceding instruction. Dedicated control logic is common and pipeline simulation must be performed carefully.

Processors handle this complexity using several techniques that are simple, general and powerful. DEC 12 issues decoded instructions (p-ops), and the functional unit processes addresses and operands regardless of the result of detecting an exception by another functional unit. As described above, each p-op is assigned a tag by DEC 12 when it is issued, and DEC uses this tag to track the p-op.

DEC 12 is responsible for determining when execution has progressed past the point of exception. DEC using the techniques described below
Restores the state of the machine to the point immediately before (the fault exception) or the point after (the trouble exception) the p-op that caused the exception.

As described above, each functional unit has an end bus returning to DEC 12. Signals on these buses indicate when the p-op has completed (by the tag) and what exceptions (if any) were detected by the unit. DEC uses this information to keep track of which p-ops are outstanding in the machine, track resource constraints, and determine when exception handling must begin.

In response to the abend, DEC 12 returns the state of the machine to the point of the exception and calls an exception handler to begin issuing either a different instruction stream or a sequence of microinstructions.
The processor uses one or more of five general mechanisms to allow the machine to return to a particular state as part of the DEC's response to the abend. These are issuing abort cycles, reassigning registers, using a write reservation table, using a history stack, and functional unit serialization.

The abort cycle is issued by DEC when an instruction issued by DEC 12 must be cleaned from the machine. During the abort cycle, tags are provided to all functional units that identify the boundary between instructions that should be completed and instructions that must be expelled from the machine.

Register reallocation is used to restore the state of the general and segment register files and to flush out changes made for instructions that must be aborted. A functional unit has more physically available registers than the instruction set specifies. DEC 12 maintains a set of pointers that map programmer visible (or virtual) registers to physical registers. In assembling the decoded instruction, DEC replaces the appropriate physical register number with a register designation field.

When changing a virtual register, DEC first allocates a new physical register, changes the pointer set, and uses the assigned register number as the destination register. Even after execution of the instruction, the old physical register still contains the changed value of the virtual register. To back out register changes, DEC must restore the pointer set to its pre-instruction value.

Freed physical registers are placed at the end of the free list long enough that they do not appear at the beginning of the free list until after they no longer need the contents of the physical registers. DEC maintains a history stack of pointer values, as described below.

The write reservation table is used in the MCC 25 to wait for a data write until it is known that the write should not be aborted. The MCC receives the address and operand on the internal data bus, matches them by tag, and performs an irreversible write if it is safe to do so.

The history stack is used to save and restore miscellaneous machine states such as register reallocation pointers, flag registers, and program counters.

For machine states that change infrequently, the cost of the value history stack is ignored. In these cases, the functional unit performing the change (and only that unit) stops processing, and the tag of the oldest outstanding instruction in the machine (supplied by DEC) is examined in each cycle and all Are determined when the old instruction has been successfully completed. At this point, it is no longer necessary to reserve the old value of the machine state, and the functional unit makes an irreversible change of the machine state.

A distributed pipeline control scheme, combined with the ability to back out state changes, allows for many performance optimizations.

Each functional unit can receive all p-ops, but actually requires processing in that unit. p-ops
Just handle. This is in contrast to a normal pipeline where instructions flow through all stages, whether or not the stages perform useful work.

Further, each unit performs operations as soon as all input operands are available. The p-ops that are not ready for immediate execution are stored in the unit's p-op queue. Upon completion, the result is passed to the next stage for further processing and the next operation is examined.
A stage stops executing only if the stage has nothing available to execute.

This behavior allows execution in any order between functional units. For example, in the case of a memory write with an address generation interlock, the AP will not be able to calculate the memory address. But the IEU can supply the data, do it immediately, and then continue to the next instruction. The AP interlock does not need to create pipeline bubbles in other pipeline stages. At a later time, the IEU may delay performing the multiplication or wait for a memory operand. At this point the AP has the opportunity to catch up with the IEU.

This is not a complicated concept from the point of view of a particular functional unit. The functional unit makes the decision locally and is completely unaware that it may be completely out of order. The pipeline control mechanism is
Ensures that changes made by instructions executed out of order can be drained. Functional units do not perform any special checks.

Out-of-order execution between functional units is free to occur as a result of distributed decisions made within the processor. Even within one functional unit, the instructions can be executed safely and out of order. IEU17 provides an example of this out-of-order execution. The IEU looks at the head of the instruction queue to see if it is ready to execute. If the data interlock prevents immediate execution, the IEU examines the next younger instruction to see if it is ready to execute. This process continues until an executable instruction is found. The IEU pays a data interlock penalty only if no available instructions are ready to execute.

Even if the IEU pays the interlock penalty, that does not mean that the processor has lost one cycle as a whole. Even if the IEU is delayed, it can catch up later when an instruction that does not require the IEU is issued. Finally, one or more penalty cycles can overlap with one or more penalty cycles from AP15.

A special case of a functional unit that chooses to execute instructions out of order is the parallel execution of instructions within the functional unit. That is, this concept applies to instructions that require multiple cycles. Parallel execution of other single cycle instructions allows multi-cycle instructions to have an effective throughput of one cycle.

DCache misses usually halt the pipeline due to a full cache miss penalty. Cache miss penalty is reduced to the extent that functional units can find operations that can be performed without using cache data. This is true for mistakes in the TLB of the AP chip. In these cases, the number of penalty cycles is usually quite high, unlike other cases where it is difficult to completely overlap them with useful work.

Pseudo-Op bus format Table 1 shows the format of the p-op bus 52. This bus is 52 bits wide and is a time multiplexed bus. DE
C12 drives this bus alone to convert p-ops to AP, IEU,
And NP. Bus is standard CMOS style time multiplexed
Use I / O.

Typically, one 386/387 macro instruction is translated into one p-op issued by DEC to the relevant functional unit. In some cases, one macro instruction is issued p-op
yields a sequence of s. This p-op issue sequence is atomic, i.e., the issuance of p-ops of one macro instruction is not interleaved with the issuance of p-ops of another macro instruction (or exception handling sequence). .

In the case of a typical macro instruction, one p-op contains enough information to allow all relevant functional units to perform the necessary operations of the macro instruction. This includes memory operand address calculations and segments, outgoing and destination operand registers, ALU operations, operand sizes, operand routing, status flag changes, and p-op tags, and associated displacement and / or immediate data values. Including the specification of. NP p-ops also specify a microaddress.

Most p-ops are transferred on the p-op bus using both clock phases (φ1 and φ2) during one clock cycle. φ1 is used to transfer almost all control information contained in the p-op, φ2 is used to transfer displacement and / or immediate (with a few extra bits of control information) Is done. In some cases of p-ops that include both displacement and immediate (cannot be packed into 52 bits), a second clock cycle is used to transfer the immediate. This second cycle always immediately follows the first clock cycle. The displacement is transferred to φ2 in the first cycle, and the immediate value is transferred to φ2 in the second cycle.

DEC 12 drives the p-op bus during every clock cycle. Normally this is a normal p-op, but during cycles where DEC is not ready or cannot issue a normal p-op, DEC sends an empty p-op instead.

The philosophy of encoding information in a P-op is first and foremost to provide control information in a form that is not encoded as early as possible within a clock cycle or that can be quickly decoded. This is especially true for the start of speed critical operations in each functional unit, and for the extraction of displacements and immediates and the derivation of the appropriate address and data operands. Only less critical control information is transferred during φ2, but typically during φ2 each functional unit assembles / fetches operands from both registers and p-ops and Each functional unit should be able to start internal calculations.

As mentioned above, most macro instructions are translated into a single p-op. This includes some more complex microinstructions,
This complexity must be handled in one of the functional units via microinstructions (eg IEU, multiplication in POPA in AP). However, where possible, complex macro-instructions are converted into p-op sequences that are executed independently by functional units without being aware of the overall sequence. In some cases, for example, multiple register reallocations (only one per p-op is allowed), multiple p-op tags required by the AP for proper memory request generation, or multiple registers by the AP And, due to the amount or nature of the control information that needs to communicate the flag updates to the AP, a p-op sequence is essentially needed.

For some complex macro instructions, the above combinations may also occur. That is, a sequence of p-ops is issued and one of the functional units goes into the microcode to execute the core portion or all of the macro instruction with the subsequent p-ops. For example, the first p-op of the sequence is processed by the AP and the IEU, while the AP goes into the microcode to perform further operations. These further operations correspond to subsequent p-ops issued. Conceptually, the p-ops of the sequence are performed independently by the functional units, in which case this is literally true for the IEU. However, due to the nature of macro instructions, the AP needs to know the p-op sequence globally. Thus, in this case, the AP goes into the microcode and simply synchronizes with subsequent p-ops. In appearance, the AP executes and terminates each p-op independently, but internally the AP uses only the p-op tag and one or two fields of each p-op.

Two additional explanations of the general nature of the issuance and recognition of p-ops by functional units are provided. First,
Most p-ops have their p by all functional units
-Op Do not wait in the input queue. As a result, each functional unit does not see all p-ops, does not process or consumes time. In the general case, p-
op is recognized by AP and IEU, or by AP and NP. Some p-ops need only be seen by the AP, one or two p-ops are recognized by all three functional units. Only the AP sees all p-ops.

Second, if there is some reason for DEC to enter exception handling, DEC will do so, and the pending predecessor p which may need to abort the newer exception handling associated with p-ops.
-Ops is still present, but the associated p-ops
Issue In general, DEC performs the minimum necessary restraint in issuing p-ops so as to ensure proper operation from the viewpoint of macro instructions.

The relevant point is that, from a microscopic point of view (ie, at the level of individual p-ops), there are very few apparent constraints on the p-op sequences that DEC can issue, or on the timing of their issuance. Exist, and therefore the functional units can make a few assumptions. This is especially true for p-
Applies to the fact that a few assumptions can be made regarding the truncation of ops. Only the most basic constraints, such as the maximum total number of open p-ops allowed and the maximum number of open NP p-ops allowed, and assurance as to which p-ops may be active / open at any given time are evident. It is.

There is one aspect worth simply explaining about ensuring proper macro instruction execution. Some p-
ops change programmer visibility that does not support the ability of the F86 microarchitecture to back out after modification by p-op. Conceptually, this makes the execution of the p-ops permanent before all of the p-ops are executed.
Requires a certain degree of quiescence of the functional units, as C can guarantee. This is not done with the general technique that DEC delays issuing its p-op (and all subsequent p-ops) until all functional units have reached a quiescent state. Instead, it is done on a localized (functional unit) basis with only each unit requiring static for a given p-op. The DEC can issue this and subsequent p-ops while performing the required degree of quiescence by the associated functional unit. In addition, units not included in the quiesce can continue to fully execute subsequent p-ops.

DEC Overview, Pseudo-Op Tracking, and Issuance Control As each pseudo-op (p-op) is issued from DEC onto the P-Op bus, it is queued by the appropriate functional unit (AP, IEU, NP). Each functional unit then processes the p-op stream loosely coupled to the other units,
When each p-op is completed, the end is notified to DEC 12. FIG.
The DEC 12 shown in the block diagram includes a front end 100, a decoder 102, and a back end 105. 3 shows a DEC front end, FIG. 4 shows a DEC decoder, and FIG. 4 shows a DEC back end.

The DEC front end 100 is responsible for fetching instruction bytes and supplying them to the decoder. Instruction from BPC 13 or I
Supplied from one of the three instruction buffers provided by FETCH_DATA bus 50. Instruction byte, PC instruction
(Program counter) Supplied to rotation / shift movement logic 110 that aligns based on information from register 112 (24 bytes at a time). Eight bytes are provided to the decoder 102, which determines the instruction length and passes it to the PC logic 112.
Communicate to. If the instruction is longer than 8 bytes, 8 bytes are communicated in one cycle, and the instruction exceeding 8 bytes is communicated in the next cycle.

Front end logic 115 controls the flow stack 117,
Supply the stream address to ITAG 27. There can be up to two open branches, and thus three open streams. The control logic sends an instruction request that specifies which flow to take
It issues to the instruction stream address register 31 in the AG 27 and receives a valid bit identifying the stream. When the ITAG supplies an address, it causes the appropriate address register to increment. Control logic 115 also receives signals from PADR monitoring logic 120 that detect writing into the instruction stream for the self-modifying code.

The DEC decoder 102 decodes the macro instruction and
Issue an -op sequence on p-op bus 52. The decoder receives the instruction byte (macro instruction) loaded in the instruction register 130 from the front end 100. The macro instruction is decoded by decode logic 132 and p
The -op decode logic 135 sends information about the p-op type to the frontend and backend, while the instruction length decode logic 137 communicates with the PC logic 112 in the frontend.

Decoder p-op assembly logic 140 is decoded logic 132
And modify them according to register allocation information from the backend. p-ops is p-o
When driven on the p bus 52, it is loaded into the p-op output queue 142. Issue is delayed by issue hold logic 145 based on control signals from the back end.

Decoder 102 includes a sequencer 147 that controls issuance when multiple p-ops generate a single macroinstruction. The decode hold logic 150 blocks processing if a valid instruction byte does not arrive from the front end. When the p-op is issued, the decoder 102 assigns a tag. Tags are issued in a circular sequence and are therefore reused, but at a given point in time only one p-op is associated with that tag. The range of the tags must be large enough for the number of p-ops allowed to be outstanding so that the relative age can be determined. Such a determination can be made by simple subtraction if the range is at least twice the maximum number of outstanding p-ops.

The back end 105 keeps track of all outstanding p-ops floating around the CPU. Reliable operation (po
issues related to the CPU's tagging scheme that controls p, address, and data processing), arbitrates for abnormal conditions signaled by functional unit termination, and issues p-ops to initiate proper operation Need to be properly controlled. When the decoder issues a p-op, it issues that p-op.
Passed to the backend with information about the op. This is used to identify the correct action required to perform the task described above.

The back end includes tracking logic 160 that keeps track of all outstanding p-ops and a decoder that responds to the outstanding p-ops and constantly satisfies various constraints (described below) required for correct and reliable operation of the CPU. And holding condition logic 165 that controls the subsequent issuance of p-ops. The tracking logic 160
Information including the oldest unfinished p-op tag (OO tag) is supplied to the tag status bus 53. The back end is p-op
abort logic 170 for processing abort of s, register reassignment logic 175 for maintaining a pointer set array 177 and a free list array 178 described later, and a tag status bus 5
3 also includes tag generation logic 179 that controls 3.

Backend termination bus logic 180 receives termination information from each functional unit and enables tracking logic 160 and abort logic 170 to maintain the status of each outstanding p-op. Some are cumulative up to a certain point in the future. This tracking during normal operation mainly affects subsequent issuance of p-ops. However, if the functional unit reports an error with a corresponding end, the backend resolves the multiple abends for the given p-op and initiates the appropriate response. This is the CP
Includes sending an abort cycle to all other functional units (including MCC) to return the state of U to a previous state of p-op processing.

The tracking logic 160 and the censoring logic 170 determine that all outstanding p-
Contains registers that store specific information about ops. These registers are organized as a set of eight identical registers numbered 0-7 corresponding to the three least significant bits of the pending p-ops tag. At most 7p-ops can be pending and tags are issued accordingly, so relative age can be determined based on location number. The tracking logic 160 comprises eight status registers 19 with associated logic.
0, an end register 192, and a p-op information register 193. The abort logic 170 includes eight response select registers 195 with associated logic, a priority logic register 197, and an end storage information register 198.

Each status register 190 stores a single status bit that is set if the p-op with the tag corresponding to that location has not been completed. Each end register 192 stores one end bit per functional unit. This bit indicates whether the functional unit has finished p-op or
Set when no action needs to be taken on -op.

Each p-op information register 193 stores 8 bits related to the associated p-op. These include the most significant bit of the tag of the p-op operated by the functional unit, the type of the p-op (eg, floating point, branch), branch prediction information, and the censoring group bit. That is, "0" indicates that the p-op is not the last number and therefore cannot be retired alone, while "1" indicates that the adjacent old p-op with "0" in the censoring group bit.
This means that it is not possible to abort the p-op without aborting ops.

The collection of status bits allows the earliest outstanding p-op to be identified. The location of p-op supplies the three least significant bits of the tag, and the information register supplies the most significant bit. The status bits and the bits in the p-op information register 193 allow the hold condition calculation logic 165 to determine the hold condition, as described below.

Each response selection register 195 provides information to the front end about which response is needed. Each priority logic register 197 specifies the appropriate action to take in response to a multiple abnormal termination of a given p-op. Each termination storage register 198 maintains detailed termination information including details of the abnormal termination from the functional unit acting on the associated p-op.

In most cases, except when an abort occurs, the functional unit is irrelevant to the status of outstanding p-ops. The main exception to this is MCC 25, which needs to know that it is safe to actually perform memory and / or I / O writes to cache and / or output to the rest of the system. is there. In special cases AP and
The IEU also needs to know that it is safe to perform some p-ops. All of these requests are satisfied by the back end, which continuously issues information every clock cycle on the tag status bus 53, which indicates the OO tag and signal abort.

Tag Status Bus The tag status bus 53 is a 5-bit bus, and its signals are limited to only φ1. As in most cycles, when bit <5> is 0, bits <4..0> represent the OO tag, the oldest unfinished p-op tag. When bit <5> is 1, abort is instructed, and bits <4..0> indicate to go back and abort based on the tag of p-op. This is called a censored tag (ATag). During the abort cycle, the backend 105
Invalidates the decoder's issuance of the next p-op and causes one of two types of empty p-ops to be issued. Tag status bus
If the p-op with tag = i indicates that it is the oldest unpaid p-op, then this is all old p-ops
(I.e., p-ops with tag <i based on a 4-bit two's complement operation) means that they are no longer outstanding and are considered retired. All young issued p-ops containing p-op (i) (ie, p-ops with tag ≧ i) are pending. Of course, this is the p
Exclude -ops.

A p-op considered unfinished means that it can still be censored, and in fact this is the operation definition used by the backend 105 in determining when to retire p-ops. P-op by all functional units
When the processing of s is complete, it is common to retire them as soon as possible (based on their termination). However, there are various restrictions when p-ops can be actually retired. Some of the details will be described below.

When retiring the oldest unpaid p-op, the tag status bus indicates this by advancing it from the ○ tag = i instruction to the ○ tag = i + 1 instruction. The oldest open tag can be advanced each and every clock cycle.
Also, from OO tag = i to OO tag = i + n (1 ≦ n
≦ 7) to effectively retire some p-ops in one clock cycle. If there are no outstanding p-ops, the tag status bus indicates the next tag to be issued as the oldest outstanding.

Censoring up to p-op with tag = i (p-op (i)) drains all p-ops with tag ≧ i (based on two's complement arithmetic with 4-bit sign), CPU
Should be rolled back to the state when it was between p-op (i-1) and p-op (i). This involves issuing the next p-op tag. In other words, censoring should drain p-op (i) and all young p-ops and restore the CPU to a state where these p-ops are apparently not issued.

Censoring up to tag = i can occur at any time, and need not be delayed until p-op (i) becomes the oldest outstanding p-op. Such a termination can also be generated when p-ops having tag ≧ i exist in the city. But still, the censoring tag and all outstanding p
-Ops tags are guaranteed that all tag comparisons for relative age are still reliable. (As a side note, for example, if there are seven outstanding p-ops and their truncation occurs, the truncation tag must be one greater than the tag of the seventh (ie, youngest) p-op.) Rolling bag in spill and condition (in outline)
Censoring must be performed by each functional unit during the notified cycle. This is necessary because the decoder 102 may begin issuing new p-ops in the next cycle. This is especially
The direction or type (for transfer of control away) is true for the mispredicted "transfer control" macro instruction.

In summary, each functional unit must empty itself during one cycle and return to normal by the end of that cycle.

In general, the cycle following the censoring cycle may include another censoring cycle or p-
can either issue an op (using more subsequent cycles) or issue a simple empty p-op (because the decoder is not yet ready to issue the next p-op) . Assuming that the next cycle following one abort cycle is not another abort cycle, the oldest outstanding p-op tag may be the same as that preceding the abort cycle, or return It may have the tag number advanced to the censored tag. This last case occurs when all prior (old) p-ops have retired after truncation and, of course, all young outstanding p-ops are no longer present.

Tag Issuance The following description relates to p-op tags, an overview of what they are, and how DEC 12 issues them. All tags originate from DEC as part of all p-ops issued. Each p-op tag is used by a functional unit to tag addresses and data associated with each p-op. If up to seven outstanding p-ops are allowed, a tag of at least 3 bits is required. This is extended to a 4-bit tag with one more significant bit to simplify comparing the p-op tags with respect to relative age. That is, assigning tags as described below ensures that a 4-bit two's complement signed comparison indicates the relative age of the two tags.
Note that only the three least significant bits are needed at the point of care to unambiguously identify p-ops.

With respect to the order of macro instructions, all p-ops obtained from these instructions are issued in order, and tags are also assigned in order. The tag value of 16 is considered a valid tag, and the tag order is defined as [next tag]: = (“current tag” +1) modulo 16. Thus, the above comparison for relative age works reliably.

The above description is applied as it is during instruction processing without termination. Return to tag = i, censoring occurs, CP
When the U state rolls back to just before p-ops (i),
The tag assignment is reset by returning to tag = i. In order to keep the relative age comparison reliable, DEC must issue new p-ops starting at this point with tag = i. Effectively, the truncated p-ops tag is reissued to the new p-ops. This means, for example, that the censoring that has returned to a point before the preceding censoring has an effect as if only the second censoring had occurred.

More generally, a set of virtually unconstrained scenarios for censoring cycles and p-op tag issuance may occur. For example, if p-ops (3-7) is not yet completed, p
-Os (5), issue tag 5-8, p-op
Censoring to (6), censoring to p-op (4), issuing tag 4-5, censoring to p-op (3), issuing more p-ops, etc. Given the behavior of the CPU and the functional behavior of the DEC, this scenario may or may not be possible, but the main focus is immediately after the above tag issuance behavior, between the issuance of p-ops and the censoring. That's what the relationship should be. As explained in the previous section, at each abort, each functional unit should quickly be emptied, return to normal operation, and forget the abort.

When the p-ops are processed by each functional unit, the termination is notified to the DEC via the termination bus of the unit, and
The completion of p-op by the functional unit is instructed. These are monitored and tracked by the backend and p-
Controls when ops retire. Although there are special internal reasons why the back end delays the retirement of a certain p-op, there are generally two issues that govern when a p-op retires. That is, appropriate CP in normal environment
Ensuring U behavior and ensuring proper abortability of macro instructions (and exception handling sequences).

The most basic p-op is that every functional unit has its p
You cannot retire until you signal the (generally normal) termination of -op. There is a DEC decoder. When a p-op is issued, information about the type of the p-op is also passed to the back end. This includes functional units that will process the p-op and are therefore expected to terminate. Based on this information, the backend will retire the p-op as soon as possible after completion or completion, subject to other constraints.

For a single and short p-op sequence macro instruction, if a fault exception is detected in any p-ops, D
The EC must handle the abort of all instructions (ie all its p-ops). This requires that the backend does not retire any p-ops until all of them have completed (at normal termination). If they are completed successfully, they will all retire at the same time.

Note that in the case of a p-op approaching the 7p-ops outstanding maximum limit, this approach to instruction abort is not desirable. For example, one instruction is 7p-op
If it is a sequence, after issuing the seventh p-op, the DEC effectively stops while waiting for the complete termination of all 7p-ops before issuing any more p-ops. For p-op sequences longer than 7p-ops, a different approach is absolutely necessary to support proper instruction truncation.

In some cases, this can be handled via some combination that allows some memory writing by instructions to actually occur anyway. In some cases, one or more special p-ops may be used at the beginning of the p-op sequence and one of the later p-ops in the sequence without this check.
It is also possible or acceptable to perform some special checks to detect exceptions that are not detected until now. The present invention provides a real p-op during these special upfront inspections.
Is to add the check performed by the first p-op (etc.) of the sequence, only one of these early p-ops can result in instruction abort, all late p-ops are exceptions Fault-free execution is guaranteed.

With these approaches to supporting instruction abortion, only the early p-ops need to be left open until they have all been successfully completed. In particular, these sequences indicate that only the beginning of the p-ops with the largest number of sequences need be processed by the DEC (ie, backend) in this way, and that the remaining p-ops are not so constrained. are doing. Within DEC, information about this effect is passed from the decoder to the back end each time a p-op is issued. In many cases where the combination of the special upfront p-ops and the first p-op of the actual sequence is sufficient to catch all exception faults, even earlier p-ops will each complete You can retire immediately. This is acceptable if the special p-ops do not significantly affect the backout of the instruction (i.e., it does not change the programmer visibility).

A final general consideration of the retirement of P-ops is that even if all p-ops of a certain sequence of a macro instruction have been completed, if the earlier p-op has not yet been completed, That means that p-ops cannot be retired. This is essentially p-ops
Is another way to see that you have to retire in turn. However, when the old p-op is complete and ready to retire, both that p-op and these later p-ops will all retire at the same time.

Table 7 shows the sequence of tag issuance and termination. Four points A, B, C and D in the sequence are shown, delimiting the boundaries of the four intervals. FIGS. 4A and 4B and FIGS. 7A and 7B show information stored in registers of tracking logic 160 and censoring logic 170 at sequence points AD, respectively. A single p-op or group of p-ops is designated as belonging to the censoring group. A censoring group consists of one or more p-ops that must all be completed in order to complete either. In other words, if one of the p-ops in the censoring group needs to be censored, all the p-ops in that censoring group need to be censored.

During the first interval, p-ops (3, 4, 5) are issued,
-Ops (4, 5) belongs to the censoring group (AG). FIG.
(A) shows tracking information in the abort logic register. More specifically, when the p-op is issued, the p-op information is stored at a position corresponding to the tag number, and the p-ops (3,
The status registers for 4,5) are set, specifying their p-ops as issued. p-ops
The censoring bit for (3,5) is set, indicating that p-ops (4,5) belonging to censoring group p-op (3) is the only number in a certain censoring group.

During the second interval, p-op (6) is issued and p-op (3)
Is notified. As is apparent from FIG. 6B, the status bit for p-op (6) is
Set in 0 (6), the AP end bit for p-op (3) is set in end register 192 (3), and the normal AP end is written into end storage register 198 (3).

During the third interval, p-ops (7, 8, 9) are issued,
-Ops (7,8) belongs to a censoring group. During this interval, the IEU indicates that p-op (3) has completed successfully, the AP indicates that p-op (4) has completed normally,
Then, it indicates that p-op (6) has been completed normally. FIG. 7A shows that the status bits for p-ops (7, 8, 9) are stored in status registers 190 (7), 190 (0) and 190.
Set in (1) and the IEU end bit is set to the end register 1
Set in 92 (3) and 190 (6), indicating that the AP end bit is set in end register 192 (4). Corresponding normal end is end storage register 198
(3), written in 198 (6) and 198 (4). p
-Op (3) is retireable, status register 190 (3)
Note that the status bits in have been canceled.

During the fourth interval, the maximum number allowed as unpaid is 7
No additional p-ops are issued because there are outstanding p-ops. During this interval, the AP receives p-ops (5, 6,
7) indicates successful completion, and the IEU indicates that p-ops
Indicates that (4, 5, 9) has been completed normally. But then the AP indicates that p-ops (7) has terminated abnormally (eg, page fault), and then the IEU
(7) indicates that the process is completed normally. As a result, p-
ops (4, 5, 6) are now retireable and they are no longer designated as open p-ops. However, p-ops
Since (8) is abnormally terminated, p-ops (7) and p-ops (8) which are members of the censoring group of p-ops (8)
Must also be aborted. Thus the abort logic 170 must issue 7 ATags on the tag status bus and return the functional units (in this case AP and IEU) as if p-ops (7, 8, 9) had not been issued. To these functional units.

Pseudo Op issue constraint Back-ends are unfinished p-ops and p-o of each functional unit
Tracking p-termination, the retention condition logic 165 in the backend also uses the status of outstanding p-ops to control the issuance of additional p-ops. In order to guarantee the correct overall operation of the CPU and the operation of specific blocks of logic within specific functional units (specifically DEC, AP and NP), the backend is the maximum of various types of outstanding p-ops. Various constraints on numbers are continuously imposed. When the limits imposed by these constraints are reached during operation, the backend sends a hold condition signal to the decoder to control whether the p-op issued in the next cycle must be delayed.

The back end generates approximately half a dozen hold condition signals to send to the decoder, potentially delaying the next p-op.
The decoder uses these signals to generate the actual p-op decode / issue hold based on the currently decoded / assembled p-op and whether the notified hold condition applies. Each retention condition corresponds to one or more (similar) constraints. In the case of an arbitrary constraint, if it is determined that the backend is the maximum number of outstanding and one of these p-ops has completely completed, a corresponding holding condition signal is generated.

For many constraints, the oldest unpaid p-
It is guaranteed that op is the first p-op to finish completely. Also, in the case of some constraints, the retention condition is based on unfinished and not fully completed p-ops, rather than simply on all unfinished (ie, not retired) p-ops.
Once a p-op has completed, even if it remains open for several more cycles, it is no longer subject to any restrictions imposed by hardware limitations of the particular functional unit.

Although the back end is one of the main generators that presents the hold condition to the decoder, there are several other sources of the hold condition. Such retention conditions signal restrictions that may or may not apply with respect to the issuance of the current p-op. During each clock cycle, the pseudo-Op bus has an active p in order to be completely general with respect to p-op issue control.
It can be said that it is driven either by -op or empty p-op (which may be with a truncation operation).
From the decoder's point of view, the decoder always issues a valid p-op unless one of the following occurs:

1) Priority given to termination from back end 2) Holding from back end 3) Holding from BPC 4) Holding from VIB (virtual instruction buffer) 5) Decoding of prefix only 6) 2 cycle p-op The second half of the feed.

Of course, 5) and 6) are generated by the decoder, and 4) and 5) are the first p-ops of the macro instruction sequence.
Is applicable only to

"Retain from BPC" occurs when the decoder tries to decode the next macro instruction and finds a "transfer control" instruction that can be cached in the BPC (some types of transfer control instructions are not cached). In response to such an instruction, the decoder performs a certain entry (target stream of entry).
It is necessary to try BPC access to the prediction information of. The BPC access to the control transfer instruction occurs during the decoding of the instruction. If this BPC access cycle is not available to the decoder, a BPC hold is generated. If access to the BPC is available for preliminary information and a miss occurs, the decoder can proceed even if BPC target stream access is not available. If a hit occurs and access to both parts of the BPC is not available, the BPC
A hold is generated. Otherwise, the decoder can proceed with the preliminary information, while the target stream of BPC entries is dumped into the new instruction queue assigned to this transfer control instruction.

"Retain from VIB" occurs when the decoder is trying to decode the next macro instruction but has not received all the required instruction bytes (for the instruction length). Decoders that pass a detected valid prefix byte must have at least a valid opcode byte, or VIB retention must be enforced. Based on the preliminary decoding of this opcode byte, if mod r / m bytes are needed,
This must also be presented or VIB retention must be enforced again. Further, based on the preliminary decoding of mod r / m bytes, if sib bytes are needed, si
The same applies to -b bytes. If these bytes are valid, then the last instruction byte (actually the VIB word containing it) is examined (and implicitly all intermediate bytes), and if not valid (ie "bad").
Or "empty") VIB retention is generated.

"Decode only prefix" occurs when the decoder is trying to decode the next macro instruction, but only the prefix has been decoded so far, and now two more prefixes are being decoded. In the case of one prefix and a second empty byte, it is treated as "hold from VIB" until the second byte is no longer empty, or it is treated as "prefix only decoding" where one prefix byte is consumed and the VIB is advanced. .

"Sending the second half ..." means that the decoder
Occurs when the first cycle of -op is issued to the general. During this cycle, a special empty p-op is sent with additional p-op information, and the decoding and generation of the next p-op is delayed.

"Hold from backend" occurs when it is not "safe" for the decoder to issue a pop immediately based on the backend signal, due to the type of p-op issued. I do. The following lists all outstanding p-op constraints enforced by the backend.

1) 7 total p-ops, 2) two control transfer p-ops, 3) one abort group in a single stepping mode, 4) two p-ops with segment register reallocation.
s, 5) Additional first p-ops of 0 after DEC rest.

The maximum number of seven total outstanding p-ops applies to all unretired p-ops. In general, therefore, for this constraint, the p-ops do not complete completely in order. However, only the back end can retire p-ops in order.

Up to two outstanding control transfer p-ops apply to all these p-ops, but more precisely this constraint is actually a control transfer macro instruction and the first p-op of their p-op sequence. applied to ops. In the case of this control, the transfer p-ops of the control are weighted only while they are pending and not completely terminated. If this p-op has finished completely but has not yet retired, it is no longer important with regard to hardware limitations. Depending on when the instruction fetch page cross-requests are generated and how they are processed, the backend can signal this hold even if the two transfer controls p-ops are not outstanding. . However, there is no impact on this constraint in all cases where an unfinished instruction fetch doubleword exists for a relatively old sequential instruction stream. IEU is control transfer p-ops
Note that it is required to terminate (p-ops including IEU) in order.

When p-op single stepping becomes possible (for hardware debugging purposes), one censored group of p-ops at a time
Ops are issued, completely terminated, and retired before the next group is issued.

Due to the reallocation scheme used for the segment registers, the data segment registers (ie, DS, E
There can only be two outstanding p-ops including segment register reallocation for S, FS, GS). This restriction does not apply to p-ops that are read only from segment registers or stored in CS and / or SS. Its purpose is to guarantee the abortability passed to any and all segment registers that store p-ops. It is not necessary to include storage in CS and SS, since AP stationary behavior has already been applied to CS / SS storage p-ops.

When a DEC static p-op is issued, the decoder will add another p-o
The ps can continue to be issued sequentially, but the decoding of the next macro instruction must be delayed until some updated control bit information is received by the backend from the AP. These control bits are used by the EF to affect the macro instruction decoding and the p-op assembly process of the decoder.
Various bits of 1ags. A p-op that changes one or more EF1ags bits on which the decoder depends is
Must be treated as a DEC static p-op. This causes the DEC copy of these bits to be updated before further macroinstruction decoding occurs.
Until the expected update is received from the AP, the backend generates a hold condition to decode the different macro instruction and
Prohibit issuing -op.

All decode hold conditions, except truncation disabled, must be set by the time the decoder must start the next decode cycle (i.e., prepare control, etc. to advance the currently active instruction queue, and renew the It is determined early enough to be able to determine the next operating state of the decoder (so as to be able to access the queue to generate new VIB content and perform the preliminary decoding).
Since the p-op generated by the decoder is discarded and replaced with an empty p-op, the truncation invalidity is not generated until later and need not be generated. At the same time, the decoder is jammed and vectorized by the back end to a new p-op sequence to be generated. (Note: There is more than one type of jam and vector for timing and vector destinations.) As noted above, for normal hold conditions signaled by various (DEC internal) units, the decoder must Does not interact with the actual holding signals of the decoder, and the decoder does not receive these signals. Instead, each unit sends a hold condition signal, which is combined (and ANDed) with the state signal indicating the type of p-op being generated to generate the actual hold signal. These signals are combined (OR'ed) with additional hold signals generated by the decoder to generate an overall decoder hold signal. This not only controls p-op issuance and decoder state sequencing, but is also sent to other units to affect their state sequencing only with interaction with the decoder.

Functional unit quiesce As functional units process p-ops, they abort changes to programmer visibility and associated state,
Or you must have the ability to back out. These are all commonly changed performance limit states,
Includes general purpose registers, fixed point registers, and most segment registers, PCs, and status flags. Others, special states that rarely change, are not returned via the history stack or using register reallocation. Instead, they are handled by limiting when they can be changed by the controlling functional unit (s). Call this process quiescent.

In essence, for any special register, the owner (s) delays performing the change until the associated p-op is the oldest outstanding p-op. This eliminates the possibility that the p-op will be aborted for another (earlier) p-op. Furthermore, a possible reason for this p-op, which would lead to its truncation, has probably already been examined. Therefore, it is now considered safe to carry out the change. (Must be done whatever is necessary so that the controlling / modifying functional unit can subsequently undo the change if it can detect the reason for the backout of that p-op.) If the op is processed by the other functional unit in addition to the AP, only the controlling functional unit can notify the abnormal end. All these p-ops are limited and written so that other functional units always notify normal termination. If two functional units both dominate a special register, they will each modify their own copy, and their p-ops will cause both units to always signal successful completion.

In any case, only functional units that depend on the special state that is changed by a certain p-op are involved in the stationary. All other functional units that process the p-op behave normally. In essence, some p-op quiescence occurs on a localized basis and only where needed. As many CPUs as possible continue normal processing, and only the pop-up processing by the static functional unit (s) is possibly reduced.

Most quiescent p-ops require quiescence by the AP only, as long as most of the special registers are dominated by the AP. Many of these are AP-only p-ops, while the remainder is AP / IEU p-o
ps. Resting by NP (all on AP / NP p-ops)
Because of the changes to the three control registers it processes. In case of dual functional unit stationary, it is currently restricted to AP and IEU. This occurs when a certain p-op changes the direction flag in the FE1ag register. AP and IE
AP and the IEU perform a parallel but independent quiesce because U both maintain the latest copy.

Even if a functional unit is quiescing while processing any p-op, this does not necessarily mean that the unit will quiesce rights before starting processing the p-op.
Particularly when the AP is stationary, a part of the processing of the p-op can be performed before the stationary. The AP only needs to be stationary in changing special registers. When the quiesce is complete, the AP performs the change and can continue processing.

DEC can also perform quiescing, but this is only somewhat similar to quiescing performed by other functional units. Following the issuance of the DEC static p-op, DEC
-Delay assembly and issuance of ops. This delay occurs until DEC receives a “control bit update” from the AP. See the preceding section for a further description of DEC stationary. For the "control bit update", see the section on the AP termination bus described later.

In the case of DEC quiesce, as in other cases where DEC receives control bit updates from the AP, some special control bits DEC
The copy is updated. This occurs with the AP changing its own copy of these control bits. The copy held by DEC will not be seen as a master copy owned by DEC, but will instead be
Seen as a secondary copy maintained in DEC. DEC
Does not have the ability to back out updates to these bits. This is not a problem, however, since the AP must also change the master copy of these bits and will not send control bit updates before changing its own copy. This requires AP quiescing, so the update of the DEC control bit copy is effectively delayed by the AP until the associated p-op is the oldest outstanding.

Abnormal Termination Processing As described above, the back end monitors the termination of p-ops of each function, and accumulates the status regarding all undecided p-ops. Based on this information, the backend is p-op
Controls the retirement of s (generally successful after all associated units, then abend) and affects when new p-ops are issued by the decoder. p-
When the ops complete and receive one or more abends, the backend is also responsible for determining an appropriate response, and then starts it at the appropriate time.

When the backend receives terminations, including abnormal terminations of a given p-op, it generally accumulates them until all expected terminations have been received. If an abend exists, the p-op is not allowed to retire. At this point, the backend initiates the appropriate response. If there is more than one abend, the backend will prioritize and select the response to the abend. These two sides of the abnormal termination process will be described below.

This wait before initiating a response is an early / old p-op
This is done to minimize the design complexity of handling the dialogue case resulting from the abend response nested / replaced by the abend responses (which are detected and initiated later). In addition, if only the abnormal termination that causes the start of the exception processing is performed in this way, a serious penalty is not imposed on the performance due to the standby.

The specific response initiated by the backend depends on the abnormal end and whether or not old p-ops are pending. This does not explicitly depend on the p-op, but in particular does not explicitly depend on the operation code of the p-op. The response often sends an abort cycle with the appropriate tag, which need not be the tag of the aborted p-op. During a truncation cycle, or during a cycle that issues an empty p-op without concurrent truncation, the backend jams and vectorizes the decoder to a state where the decode continues decoding and p-op issued operations. If exception handling must be started, the decoder will assemble and issue the appropriate p before returning to macro instruction processing.
-Vectorized into op sequences. Depending on the type of exception being initiated, abnormally terminated p-ops may be included in the censoring or may be retired as normal.

In most cases where the responding abend does not result in exception handling, an immediate response is initiated when the p-op has completely terminated. In the case of a minor special abend, a response occurs immediately after the end is received by the backend. These terminations are not considered normal terminations, but are more useful. These terminations are not true terminations, because subsequent terminations are expected and the functional unit is required to generate a special abnormal termination.

The response to these cases is similar to the response described above, including the start of exception handling, and includes the possibility to vectorize back to the macro instruction instead of just vectoring to some appropriate p-op sequence. In other words, the later p-ops in the p-op sequence are killed and the decoder continues decoding the macro instruction stream from the next instruction (from the current instruction queue or a different instruction queue). Also, in the case of low abends, the response will either not directly affect the decoder and / or cause DEC to start another operation internally.

IEU End Bus Table 5 shows the format of the 5-bit IEU end bus 62. This bus uses standard CMOS style time division I / O,
The normal termination of p-ops and two types of abnormal termination (exception and mispredicted branch direction) are notified. φ2 bus has 3 bits p
Supply the -op tag and the 2-bit end Id.

Because of the timing of DEC decoding and the p-op assembly pipeline, if the IEU exit code and associated p-op tags are sent in time division to φ2-φ1 (ie, one phase earlier), DEC will return the correct next p-op (From the correct next macro instruction or from the appropriate exception handling p-op sequence) can immediately respond in a subsequent abort cycle.

In general, the IEU can and will terminate p-ops out of order (relative to the order of issuance by the DEC). Some p-ops such that the relative serialization between two p-ops of the same type must be maintained by the IEU as far as the order of processing / executing p-ops is concerned
There is a specific case of -op. In general, the order of execution in these cases is crucial, not the order of termination. The control transfer p-ops in which the IEU sees only conditional (near) control transfer p-ops is required by the IEU to end in relative serial order. From a DEC perspective, it is not absolutely necessary to process these p-ops in order.

As the IEU processes p-ops, there are two cases as to when they can be terminated. 1) If the p-ops do not request a DXBus transfer after execution, the p-op can terminate when it knows the correct termination. 2) If the p-ops request such a transfer after execution, the p-op can be terminated if it knows that the transfer will occur reliably, or if it knows that the transfer is actually occurring. In either case, termination can occur after these points.
In other words, in the case of 1), p-op is set during the ALU operation if the termination is unconditionally normal, or immediately after the ALU operation is completed if the termination depends on the ALU operation. Can be terminated. In case 2), the IEU has D
Knowing that the XBus arbitration has been won, the p-op can be terminated.

Based on the general IEU pipeline, output queue timing and instructions, and the timing of IEUTerm (ie, φ2-φ1), the following actual termination behavior of the IEU is now predicted. For p-ops where the result does not need to be transferred via DXBus, termination is initiated during the ALU operating cycle. For most p-ops, this is unconditionally successful and the correct termination for transfer control p-ops is determined during the first part of the ALU cycle (this is the INTO instruction p
Also applies to -op). Occasionally, this termination, which cannot go out on the termination bus, is queued and signaled to DEC at a later time (but, of course, quite immediately).

For p-ops that need to transfer the result onto the DXBus, termination is started during the transfer cycle. Again,
If the end cannot be exited immediately, it is put on hold and sent later.

In the case of p-ops, which belong to the case 1) above, may result in abnormal termination and depend on the ALU operation dependent BOUND and REPed column macroinstructions, the timing in case 1) does not work. In these cases, the p-ops are treated as if they needed to send the result over DXBus.

There are two reasons why terminations are generated out of order. First, the IEU selects p-ops to process / execute in no particular order. Second, the IEU is p-ops
Can be terminated in any further order. IE in a nutshell
U is 1) immediately ends in the case of p-ops, and 2) p-ops
In this case, you must first go on DXBus (perhaps to do so by waiting in the IEU data output queue). In the latter case, these p-ops end when they actually go on the DXBus. Additionally, if the queuing is to (temporarily) exceed 1) and 2) ending, there is a possibility that a slightly higher priority ending (eg, control transfer ending) will be signaled prior to the queuing ending. is there. (Of course, the relative serialization of the control transfer p-ops must be ensured.) Regardless of the end of the control transfer, the IEU is p
The process must be completed before terminating -op. Does this result in a register update from the AP to the IEU,
Or simply transfer the memory operand to a register
-Ops included. For both types of p-ops, the outgoing operand must be received before the p-op ends.
To illustrate this in contrast to the behavior of the AP, for various transfers and register updates, the AP can terminate before receiving what is a valid register update (requires a combined register result). Even if you do).

After notifying the abnormal end in response to the abnormality detected during the processing of the p-op, the IEU continues the processing of other p-ops as if the p-op ended normally. The IEU does not stop processing the p-ops, but rather waits for an upcoming response to the abend.

IEU Termination The termination shown in Table 5 is described below.

If there is no actual end to inform, the end shall not be signaled. The end bus is valid for all clock cycles and must always indicate something.

The normal termination is notified if no abnormality is detected during the processing of a certain p-op.

Mispredicted branch direction termination is signaled on control transfers p-ops (these must be conditional near-control transfers) if the predicted branch direction is incorrect. This is an alternative to a successful completion for the correctly predicted branch direction.

Abends are for exception reasons and are each used to signal a corresponding architecturally defined exception. The division error is annotated with p-o annotated with EUabort in the p-op sequence of DIV and IDIV macro instructions.
Used on ps. BO for binding inspection and INTO overflow
Used on EUabort p-ops for UND and INTO instructions. RE
The P'ed instruction repeat stop is terminated by the rep'ed column macro instruction
Notified on the p-ops of the -op sequence, i.e. the p-ops annotated with EUabort. If the test performed by the p-op indicates that the repetition of the column macro instruction should be stopped, this termination is signaled instead of a normal termination. This applies even if the p-op test indicates that the repetition of the column instruction should not be triggered (i.e., performing zero repetition). If no exception is detected in these situations, normal termination is signaled.

There is no possibility that the IEU will detect multiple anomalies in one p-op, so no relative priority will be issued during IEU abnormal termination, but a priority will be issued for the termination of another functional unit. Since there can be only one type of exception for a given p-op type in the IEU, the DEC censoring logic uses its p-o
Exception types can be uniquely identified based on p. IEU abends are grouped into groups based on their priority as recognized by DEC for AP and NP abends. Most abnormal terminations are grouped into medium priority groups, while REP termination terminations have low priority.

The mispredicted branch direction end is special in that it does not have a specific priority fixed for all AP ends. Instead, the execution branch direction (predicted direction and correctness of the prediction) combined with the AP termination determines the action initiated by the DEC backend.

AP End Bus Table 6 shows the format of the AP end bus 60. This bus uses standard CMOS style time division I / O and signals normal termination of p-ops and various abnormal terminations.

Due to the timing of DEC decoding and the p-op assembly pipeline, if the AP exit code is one phase earlier (φ
2-φ1) If sent in time division, DEC will be
p (from the next macroinstruction or from the appropriate exception handling or other p-op sequence) can immediately respond in a subsequent abort cycle. The encoding of the exit code is such that in critical cases, the DEC can provide an ideal response time and issue or abort another p-op or issue the correct next p-op .
For other exceptions, there is an effective special cycle within the response time. That is, one cycle occurs before the abort cycle, and the next cycle is followed by the correct next p-op.

This special cycle, which handles most abends, is distributed among the DEC backends to find out what happened and what to do, and that the DEC decoder is jammed and vectorized and the correct next p- Op decoding starts. In the case of quick termination, the back end has a limited processing situation. Supporting this rapid processing is that the AP always terminates the p-ops in order, so that the backend can predict the p-op tag associated with the next termination.

Quick termination is provided for situations such as normal termination of some p-op, and optionally control bit updates (from AP to DEC) indicating both / and / or mispredicted addresses. Can be For a successful completion, the back end with information about the p-op tag and the type of dominant p-op needs to reflect this termination in the hold condition signal to the decoder and branch control logic. In the case of a control bit update without the mispredicted address and / or D bit, the end bus transfer will provide the update value for that control bit, after which the decoder will continue decoding the macro instruction stream. Becomes possible. If the mispredicted address and / or the D bit is indicated, the timing of this termination is effectively the same as all other non-rapid terminations.

As described above, the AP must terminate p-ops in order (relative to the order of p-ops issued by DEC). This is independent of the order in which the AP processes p-ops,
For other reasons, there are restrictions on the order in which the AP can process p-ops. In all cases, the p-op can be terminated any time after it is completed. However, somewhat analogous to the situation in the IEU, there are two cases regarding the earliest point at which p-ops can be terminated. Case 1 is a case where the p-ops does not request the DXBus transfer after the execution, and the p-op can be terminated when the correct termination is known. In case 2 where the p-ops request such a transfer,
Knowing that the transfer will occur reliably, the p-op can be terminated. In other words, in the case 1, the p-op can be terminated when the reference (for the abnormal termination) and the necessary check of all the system memories are completed. In case 2,
When the AP knows that it has won the DXBus or PAdrBus arbitration for the transfer and knows that the transfer will occur, p
-Op can be terminated. This includes the case where the PAdrBus memory address reference transfer is aborted due to a TLB miss, and this termination cannot occur before knowing whether the transfer is actually completed. Additional restrictions / requests by DEC are described below, with specific emphasis.

Note that except for the receipt of a general register update from the IEU, NP, or memory, the AP can terminate the processed p-op before the update is received. The update essentially does not require any further processing, but simply stores it in the appropriate register and updates the register interlock control to indicate this. AP is related p-op
Is guaranteed to receive these updates by the time it completely terminates, and therefore before it retires. Of course, the AP must still properly track the expected register updates for abort occurrences.

After notifying the abnormal termination in response to the abnormality detected during the processing of a certain p-op, the AP appropriately ends the processing of the p-op. Depending on the termination, the AP can stop further p-op processing. This behavior occurs after an abnormal termination, such as when DEC initiates exception handling and responds. In all other cases, the AP continues processing.

After terminating the process, the AP saves and / or freezes the required internal state and waits for an upcoming response to the abnormal termination. This response may not occur and, more generally, the AP must coordinate with all responses that initiate exception handling.

AP termination The termination shown in Table 6 is described below. For all abnormal terminations that indicate an exception on p-ops, the termination Id bit <
Note that 3..0> directly corresponds to the number of interrupts of the exception to start processing. Two exceptions to this are the alternative "debug and general protection" fault codes (i.e. 1111 010X) used in special cases. It is special that the DEC is shut down instead of the "abnormal termination" (code = 1111 1001) without exception processing.

If there is no actual end to be notified, the end shall not be notified. If no abnormality is detected during processing of a certain p-op, a normal termination is notified.

"Control bit update" is used with all DEC static p-ops. These are p-ops that directly or indirectly affect all or any of the IF, D, and B bits (found in EF1ags and various segment descriptors). AP (1 or more) of the affected bit (s)
Once the new value (s) have been determined, this termination is used to send the updated value to DEC.

Note that this is not a true termination, and in particular does not terminate a p-op that results in a control bit change. Normal p-op termination is still required and must occur after a control bit update. (The control bit update itself must follow the end of the preceding p-op.) DE
Note also that C will continue to issue the p-op at any time after receiving the control bit update end, regardless of the end of the p-op. The concept is that during the processing of the p-op, as soon as the new value of the affected control bit is known
The AP sends this update to DEC and continues processing its p-op.

Since the above control bits represent the programmer-visible bits,
The AP and DEC must potentially be able to back out updates to these bits. To avoid this (without having a significant impact on performance), the AP changes the master copy of these bits (not later) when signaling control bit updates, and the Both of these actions are delayed until the old pending p-op is reached. In essence, signaling a control bit update implies AP quiesce before signaling an update.

The second form of control bit update is similar to the first form, but directs the transfer of the update to the "mispredicted address" and / or the D bit on the bus. This is used for the transfer of control p-ops where DEC has predicted the target address (and assuming that the D bit has not changed). If the (physical) target address predicted by DEC to transfer the control p-op is incorrect (i.e., different from the (physical) address at which the AP originated), the AP notifies this and updates the D bit Must be sent. Of course, AP
Must also send an address update (ie, the correct target address) to the instruction cache tag.

The AP does this all by sending out the correct target address through the PAdrBus and at the same time signaling a control bit update with the mispredicted address and / or the D bit (concurrency required). This update is similar to the first form above in terms of sending update control bit values. In addition, DEC appropriately changes certain internal states to indicate mispredictions and resumes instruction fetching and decoding using the correct address and D bits. As mentioned above, DEC is essentially guaranteed to receive updated control bits before DEC can decode the next valid macro instruction.

Unlike the first control bit update, this is a true end, specifically ending its transfer control p-op. The timing provided by the AP to send out the correct target address to notify the update allows to avoid notification of "control bit update end" if another anomaly (ie, exception) is detected. That is, the AP sends out the address and notifies the end of the update, or the abnormal end (along with the invalid address)
Notification.

In the case of a page cross that causes an error, no PAdrBus transfer occurs. This may be due to either or both of a segment overrun (which results in a general protection failure), a page failure, or both. The AP notifies abnormal termination and indicates that a failure has occurred. If instruction execution truly requires crossing a page boundary, exception handling is initiated. AP
From the viewpoint, the processing and termination of the page cross request is independent of the surrounding p-ops. DEC uses p-op flow and p-op
Emphasize the priority of exceptions on page crosses appropriately for op exceptions.

Each abend for an exception signals a corresponding architecturally defined exception. In two cases (eg, a “general protection” fault), there is a pair of ending Ids that signal an exception. One is commonly used and the other is used in some exceptional circumstances where it is necessary to distinguish as long as they have different priorities for abnormal termination by other functional units (ie, IEU and NP).

It should be noted that some of these abends are associated with a particular macro instruction. Specifically,
The "387 unavailable", "invalid opcode", and "general protection" (code = 1111 0100) terminations are signaled on the first p-ops of the associated p-op sequence. The "general protection" end (code = 1111 0100) and the "debug" end (code = 1111 0101 for debug failure) are signaled on the first p-ops of the macro instruction sequence. "Debug" end (code = 1111 for debug trap)
0001) is signaled on the last p-ops of the macro instruction and task switch sequence.

MCC Termination Bus The MCC 25 termination bus 65 is a 1-bit bus that uses standard CMOS style time division I / O. The actual signal transfer is φ1-
Occurs at the φ2 boundary (ie MCC end is φ2 transfer),
Transfers at other phase boundaries are undefined. This bus is used to signal the end of a normal memory write directly generated from p-ops. Terminations for memory reads, system memory references, and other references (eg, I / O) are not generated.

The MCC receives memory reference addresses from the AP in order (relative to the order of issuance of p-cps resulting in memory references). MCC
Must terminate the memory write reference in this order. Therefore, the explicit transfer of the p-op tag is not required to notify the end. The DEC backend monitoring the end bus based on the end of the write sequence predicts which p-op tag will be associated with the next end from the MCC.

The end of the memory write is signaled when the address is received from the AP and placed in the appropriate write reservation queue. This is irrelevant when the MCC receives the data and when the write leaves the queue. The writing of the read / change / write operation by the p-op also ends. In the case of p-ops that result in misalignment or greater than a 4-byte memory write, the AP needs to generate more than one misaligned address. The end of such p-op writing is notified when the last address is placed in the reservation queue.

The AP generates its own end of these p-ops regardless of the MCC end of the p-ops resulting in the memory write. This occurs when the AP transfers the last address of one or more word-aligned addresses to the MCC via the PAdrBus. Normally, it is not necessary for the MCC to indicate receipt of a memory write address since the MCC can immediately place the address (es) in the queue. However, if the MCC cannot place the address in the appropriate write reservation queue (because the queue is full or overlaps with a previous (old) write in one of the queues), Termination is required. In these latter cases, DEC is p-o
Termination is delayed to prevent advance of the issuance of p.

If the MCC does not have its own end that can be delayed, the following can occur: AP is p-
Upon terminating the op, DEC believes that the p-op that generated the write has completed and is safe in the write reservation queue.
DEC passed the tag corresponding to this write address 7
Alternatively, the process proceeds to issue of an abnormal p-op tag. This is MCC
Will have problems with abort processing, data and address matching, overlapping memory read processing, and performing cache writes.

Thus, the MCC has the ability to delay placing queued addresses with overlapping problems (and, of course,
The ability to delay the AP from sending more addresses)
Let's have. While the MCC delays the address (and assuming that this is the last address of one p-ops write), the end of the write by the MCC is similarly delayed. At the same time that the address is finally placed in the appropriate queue, the MCC signals the end.

The DCC continues to consider the p-op as unpaid while all the predicted functional units except the MCC have completely terminated the p-op expected to terminate from the MCC. In essence, DEC treats the p-op's MCC termination as akin to the termination of other functional units as far as the p-op can be retired.

There is no direct interaction with abnormal termination by other functional units (AP, IEU, NP) as far as the notification of successful termination of the MCC is concerned. Indirectly, p-op where MCC termination is predicted
Cannot always be terminated by the MCC. AP is p-o
Abnormally terminate p and don't generate all addresses for associated memory writes (and may not be possible)
In that case, DEC behaves accordingly. That is, DEC reorganizes these cases, does not delay the processing of the MCC abend, and continues to properly track the pending memory write p-op tags.

There are also special situations where the AP terminates p-op normally but does not generate a corresponding memory write. In these cases, the AP informs "normal end but no write" to indicate to DEC that no write is issued and therefore no end from the MCC is expected.

NP end bus In summary, NP end is a 2-bit bus (p-op
), And signal a floating-point matching exception. Although a logic for including the optional NP is provided in the CPU, the detailed description is omitted.

Register reallocation As described above, up to the event necessary to release the instruction
One of the mechanisms used to return the state of the CPU is register reallocation. This technique entails mapping the set of programmer visible (ie, virtual) registers into a larger set of physical registers. The number of physical registers exceeds the number of virtual registers by at least the maximum number of p-ops that are allowed to be pending and that can change registers. This technique applies to both general purpose register files and segment register files.

The specific macro instruction architecture (80386) is
It provides eight virtual general purpose registers named VR7 and six virtual segment registers. As described above, at most seven p-ops in total and at most two p-ops that change the segment register are allowed to be pending. In harmony with this, AP 15 includes a set of fifteen physical general registers, designated FR1-FR15, and eight physical segment registers, while IEU 17 includes fifteen physical general registers. Although the physical register PRO exists in the IEU,
It is used for other purposes.

FIG. 5 shows the virtual registers VR0 to VR7 to the physical registers PR1 to PR.
It is a schematic diagram of the mapping to R15. Each physical register has an associated valid bit schematically indicated by "V". These valid bits are used by the functional unit as follows. To support general-purpose register reallocation,
Backend register reallocation logic 175 maintains a pointer set array 177 and a free list array 178.
The pointer set array and the free list array each provide storage for eight lists, each of which has a three-bit index corresponding to the least significant three bits of the pending p-ops tag. Each pointer set and each free list are represented by columns in the figure.

The pointer set and free list for a given index are
The state immediately before the issuance of the p-op having the tag corresponding to the index is maintained. Pointer sets are virtual registers VR to VR7
, Each entry including a pointer to one of the physical registers. The free list contains seven entries that contain pointers to physical registers that are not pointed to by members of the pointer set.

Consider the initial state before issuing a p-op with tag = 0. In this initial state, VR0 is PR8, VR1 is PR7, VR2
Is mapped to PR6,…, and VR7 is mapped to PR1. The free list includes pointers to PR9 to PR15, where PR9 is the head of the list and PR15 is the tail of the list. This state is tag =
Zero is stored in the column of the first entry.

Now, three p-ops with the following tags 0, 1 and 2
Let's consider a representative series of s.

Tag = 0: VR0 = VR0 + VR3 Tag = 1: VR3 = VR3 + VR5 Tag = 2: VR4 = VR0 + VR3 Since VR0 is mapped on PR8 first, p-op (0)
Cannot change PR8 until it is established that p-op (0) can be completed. Therefore, p-op (0)
Must be changed to map VR0 onto a physical register in the free list.
Since PR9 is the head of the free list, VR0 is mapped onto PR9. PR8 is issued eight p-ops, p-op
Since (0) does not start until it is guaranteed that it has retired, it is placed at the end of the free list. Each other item in the free list advances to the beginning. Therefore tag = 0
The actual p-op issued with is PR9 = PR8 + PR5.

The next p-op, p-op (1), attempts to change VR3. In order to enable this p-op to be backed out, VR3 sets the physical register at the head of the free list, ie, P
Maps to R10. PR5 is placed at the end of the free list,
PR11 moves to the top of the free list. The actual p-op issued with tag = 1 is PR10 = PR5 + PR3.

P-op (2) tries to change VR4. Therefore, VR4 is mapped to the physical register PR11, and VR5 is placed at the end of the free list. The actual p-op issued with tag = 2 is
PR11 = PR9 + PR10.

When a p-op that modifies a physical register arrives at a certain functional unit, the valid bit of that register is cleared (indicating invalidity) and set only when the p-op ends (indicating validity). This is necessary to ensure that the correct data exists for the late p-op trying to read the physical register. In the particular example shown, p-op (0) changes PR9 and p-op (0)
(1) changes PR10. p-op (2) is PR9 and PR10
Must have valid source registers (PR9 and PR10) before it can be executed. This only occurs when p-op (1) and p-op (2) have ended. p-op (0) and p-op (1)
Should not be retired, since if any were purged, p-op (2) would also be purged.

Write Queue in Data Cache Subsystem FIG. 6 is a block diagram of the MCC 25 that provides control of the data cache subsystem. This job is
Associating the write address generated at 15 and passed through PAdrBus 55 with the corresponding data generated by any of several chips and passed over DXBus 58; and writing data (right justified within a 32-bit doubleword). Byte address) and the byte address specified by the AP, and check for memory data dependencies on the same address between the write and the subsequent read, and replace them as soon as data is available. Short-circuit and the p-ops that caused the write operation
To maintain coherence of execution by waiting for write operations to be guaranteed to complete successfully, and, if necessary, to perform write operations without modifying main memory or the cache itself. It is possible to abort.

The data cache subsystem handles three categories of data operations. A normal data access is a programmer-specified data access, except for what the NP 20 performs, if any. The other two categories are system access and NP access. Data read from the memory in each category is an earlier p-
It must represent the writes made by the ops, but the different categories of writes can be processed asynchronously. That is, writes near different categories (with respect to the order of execution) do not change the same address, or if they do, the asynchronous effect of writing between categories is mild.

MCC 25 includes a write buffer 302 and a multiplexer.
Write Reservation Queue (WRESQ) 300 combined with 303
A system write queue (SYSWQ) 305 in combination with a system buffer 307, and a write reservation queue (N in combination with an NP buffer 312 and a multiplexer 313).
PWQ) 310.

WRESQ 300 is only useful for normal data access. This means that each write data (which may be a single byte, 16-bit word, or 32-bit doubleword, but always arrives right-justified within a single 32-bit doubleword from the execution unit) , As indicated by the corresponding address (es) that can specify an alignment in memory on any byte boundary, and the same between writing and subsequently reading any category. Performs all of the above functions, including checking memory data dependencies on addresses.

SYSWQ 305 is the p-op that generated the system write.
Buffer system writes until s is successfully completed and they are written into memory. This provides at most four outstanding system writes. System access is an access performed by the AP to access hidden system structures (page dictionary entries, page table entries, segment descriptors, and task state segment data). All system writes occur as a single doubleword read / modify / write operation that sets the "accessed" or "busy" bit. Since the AP does not perform out of order execution, all system accesses occur in order. Further, since system writes occur from read / modify / write operations, the address must arrive at the MCC before the write data.

The NPWQ 310 buffers eight NP write addresses (sufficient to hold the result of at least two NP p-ops). The NP data access commanded by the NP differs from the normal data access in three main points. That is, a single NP p-op can read and / or write up to 10 bytes of data, while a normal p-op can access at most 4 bytes of data. Thus, the NP can perform multiple doubleword transfers to perform the write operation specified by a single p-op. The data for the NP p-op always arrives at the MCC sequentially (ie, in the same sequence as the addresses arrive).

The WRESQ 300 is the most complicated write queue, and performs processing for terminating and terminating the p-op as described later. WR
The ESQ consists of a complex data and instruction buffer that accepts eight entries. Each entry is a 30-bit associative memory (CAM) register for double-word addresses (double-word is 32-bit data), numeric comparison logic and "final"
4-bit dedicated tag CAM, including bits and "released" bits, and 4-byte width combined with control logic including valid bits for each data byte and "current" bits for all data registers Data register.

WRESQ is the data physical address bus queue (PAdrQ)
Receive memory addresses for data access from a FIFO buffer called 320 (these memory addresses are buffered in PAdrQ upon arrival from the AP). Each address contains the type of access to be performed (read, write or read / modify / write), the tag of the p-op that generated the address, and the double transferred to and / or from the addressed doubleword. With a 4-bit byte enable mask indicating the long word byte and a "final" bit indicating whether the address is the last one generated by the p-op.

Each address received from the PAdrQ for a write or read / modify / write access is all that has already been entered in the WRESQ with the valid bit set in any byte position indicated by the byte enable bit with the address. Is compared associatively with If WR
When it finds something in the ESQ that indicates an already overlapping write, processing of the new address into the WRESQ must be delayed until the overlapping write is written to memory and removed from the WRESQ.

In this case, the MCC must suspend until the location has been written to memory so that the write queue will accept more addresses. This is called a pipeline stall, in which case the MCC allows the address to be returned in PAdrQ, and if this structure signals an overflow, the MCC locks the PAdrBus and the AP gets more addresses. Prevent issuing. Otherwise, if a pipeline outage is not required or such an outage is resolved by removing overlapping entries, a new address is assigned to a location in the WRESQ.

The positions in WRESQ 310 are selected for round-robin assignment by an assignment counter. If the selected position is free, the address is "Address CAM"
The tag and the "last" bit are copied into the Tag CAM, the four "current" and "released" bits are set to 0, and the four "valid" bits are written to the longword. Is set corresponding to the byte enable bit that specifies the byte of If, on the other hand, the WRESQ location is still in use when taken up for reassignment (indicated by one or more valid bits being set at that location), that location is written to memory. Until the MCC must stop accepting further addresses (stall the pipeline).

During or after the clock period when a new entry is written into WRESQ, data is written into the data byte with the valid bit set. There is no guarantee that the AP will send the addresses before the execution unit provides the data to be written, and there is no guarantee that the MCC itself can process them as soon as the addresses arrive. Thus, data may have already been sent to the MCC before the WRESQ entry was established. The 8-entry WBuf 302 accepts this. This WBuf is arranged between DXBus (a bus for transferring write data to the MCC) and the input of WRESQ itself. The data arriving at the DXBus is identified by the type of operation it represents (a normal memory write if addressed to WRESQ) and the tag of the p-op where it originated.

When the normal memory write data arrives at the DXBus, it is stored in a 32-bit WBuf addressed by the least significant 3 bits of its 4-bit p-op tag, and this p-op
The most significant bit of the tag is stored with the entry and is "current" (unless a Tag CAM hit as described below occurs).
Bit is set for entry. At the same time, the tag is searched in the WRESQ Tag CAM. If the location for the data (or two adjacent locations) is "final"
As soon as the bit is found in the WRESQ containing one location that is set, the data is written to that (or their) location (in this case, the “current” bit of the WBuf entry is not set). Similarly, "final"
When an address with the bit set is entered into WRESQ, the WBuf entry corresponding to the tag of the p-op that generated the address is interrogated, and if the "current" bit is set, all data is Copied to the WBuf entry, the WRESQ "current" bit is set and the WBuf "current" bit is cleared.

Due to the two mechanisms described above, regardless of whether the data or address arrives first, or if they arrive at the same time, if both data and address are present, the address and data are both put into WRESQ. As input, the "current" bit of the WBuf entry for that p-op is cleared and the "current" bit (s) of the WRESQ entry (s) are set.
At this point, the WBuf position is free for reuse. Since data can arrive out of order at the address, two independent paths to the data register and the "current" bit of WRESQ are provided to allow processing to occur as soon as possible. One originating from the WBuf can be written into that location, where the corresponding address (selected by the round robin counter) is written simultaneously. T directly from DXBus interface
It can be written in the location (s) identified by the agCAM. As a result, the newly arriving address and the data from WBuf are paired, and the newly arrived data from DXBus is written in the previously established WRESQ entry. Can write.

The data input into WRESQ passes through a rotator that byte aligns it to the same byte position that it would occupy in memory. Separate rotators are provided for each of the two data paths into WRESQ. (First) WRESQ (possibly of two adjacent entries)
The number of adjacent “valid” bits that have a value of 0, counting from the least significant byte position of the entry, indicates that the data must be rotated for alignment to the left before data writing into WRESQ occurs. Indicates the number of byte positions. The logic associated with the "valid" bit indicates that if the preceding WRESQ location also does not include the address for the same p-op tag, and only then, the "valid"
This data is provided to the barrel shifter by gating the bit.

When data is written to a location in the WRESQ, it is either an adjacent location with the same tag value (if addressed by Tag CAM), or a previous location (if addressed by the new entry allocation counter). It is also written to the location adjacent to the direction of entry allocation where the "last" bit was invalidated. Since the data to be written is at most 4 bytes wide, rotating the sweater on a byte-scale to match the byte position for one doubleword, and then writing the doubleword, is twice the memory length. For an unaligned write operation that spans a word boundary, all four bytes will be written simultaneously to the appropriate location in the doubleword.

When a normal category address with the "last" bit set is extracted from PAdrQ, the MCC provides an MCC end signal to DEC. These addresses are processed in order (i.e., in the same order as the p-ops that generated them issued from DEC), and DEC knows which p-ops will generate a normal memory access, even if MCC termination Is (one or more)
Even if the address does not explicitly include the tag of the processed p-op, DEC can unambiguously associate the MCC end with the p-op. Termination from MCC causes WEC
In the worst case, more than 8 WBufs are required to accept data from all p-ops for which an entry has not yet been established, and extraneous data and addresses must be removed from the queue in the case of abort. You can be assured that it can be drained properly. DEC uses the oldest p that has generated a successful access and has not yet been terminated by the MCC.
This guarantee is obtained because no more than 7 p-ops are issued in addition to -op.

The addresses are associatively compared (as described for write addresses) with all addresses that were each previously entered in WRESQ (and also in the other two write queues) when extracted from PAdrQ Is done. As mentioned above, the overlap between the incoming write address and the existing WRESQ entry results in a pipeline stall until the early entry is written to memory and removed from the write queue. But even the same doubleword (different part of)
, Non-overlapping writes can be entered in the queue. The addresses for read operations and read / modify / write operations (address reads) are also associatively compared with the write queue entries. Like a write, this comparison is a "valid" correspondence between the byte enable bit of the read address and the queue entry.
Performed on a byte-by-byte basis, determined by logical AND with the bits.

If there is no WRESQ entry that addresses the byte specified by the read address, or if the "current" of each entry (write / queue bit) that addresses the byte specified by the read address
If the bit is set, the MCC notifies DCI 37 to perform a normal cache search for that address. (Delay if any cache access is a cache miss,
And the need for main memory operations to retrieve the requested data. On the other hand, if the read address hits in one or more write / queue entries where the "current" bit is not set, processing of the address from PAdrQ will cause the data for all these entries to be It must be suspended (pipeline stall) until it is received. When the stall is resolved and the cache data is available, the MCC directs the DCI to gate on DIOBus 57 only those bytes that do not have a "valid" bit with the write queue hit set. "Valid" for all write / queue entries that hit the address
Other bytes selected by the bits are driven into the write queue and on the DIOBus by the MCC. Therefore, write data that has not yet been sent to memory
It can be "short-circuited" for later reading. Since the pipeline is stalled when a second write is received for a byte that is pending in the write queue, there may be more than one entry that addresses a given byte of data. Although not possible, there can be several entries that supply different bytes of the same doubleword. The write queue combines the "valid" bytes from all of these to select data and drive it onto DIOBus.

Like other units in the CPU, the MCC must keep track of the tag status provided by DEC via the tag status bus. During each clock cycle, DEC sends the oldest pending p-op tag (OOTag) or abort tag (A
Sends one of two message types on the tag status bus with the advice of Tag). WRESQ maintains a pointer to its oldest entry, called the "oldest entry pointer" (OEP). There is an entry that is
Remains unqualified for writing to memory until older than g. XX Tag in each cycle of receiving XX Tag
Is compared to the tag CAM contents of each write queue entry with one or more "valid" bits set and the "released" bits unset. Tag comparison is performed by subtracting the 4-bit OOTag from the 4-bit tag of the entry using a 4-bit two's complement operation. The tag is a binary counting sequence (0000,0001,
0010,…, 1110,1111,0000,…), and tags that are not more than 7 at a time are undecided, so the value of XXTag is at most (if 7 undecided) from one cycle to the next cycle. If all the p-ops have retired and a new p-op is issued in the same cycle, one can jump to 8.
Therefore, if the value of the most significant bit of the difference obtained by subtracting OOTag from the tag of the entry is "1", it is OOTa
Since it cannot be 8 or more younger than g, it indicates that the tag of the entry is 1 to p-ops older than OOTag. Thus, for each entry found to be younger than OOTag, the "released" bit of that entry is set. An entry is set if the "freed" bit of the entry pointed to by the OEP is set, its "current" bit is set, and one or more "valid" bits are set.
Only in that case, the data can be written into the cache and / or the main memory. When a write occurs, the "valid" bit of the entry is cleared,
The OEP is advanced to the next sequential entry with one or more "valid" bits (if present) set.

When DEC signals the abort, p-p in all queues, including PAdrQ, WRESQ and the other two write queues
ATag is checked against op tag field. This check is performed in a manner similar to the check that determines when an entry can be released, that is, by subtracting the ATag from the tag field specified in the queue. If the tag field of the queue entry is larger (older) than the ATag, the entry is kept in the queue, otherwise its "valid" bit (s) are cleared. The pointer may also need to be adjusted depending on the implementation of the queue's control logic. In the case of WRESQ, if an entry is deleted, the allocation pointer moves back to the earliest deleted entry, and if it has moved past the OEP, the OEP moves to the entry preceding the allocation pointer.

Similar checks are made for entries in WBuf associated with WRESQ and other similar structures addressed by tag values, but the address of the entry in WBuf is simply the lower 3 bits of the tag, Since only the most significant bit (MSB) of the tag of the entry is stored in the entry itself, the stored MSB with a 3-bit address greater than or equal to the lower three bits of the ATag and equal to the MSB of the ATag Has or has an address smaller than the lower 3 bits of the ATag and is relative to the MSB of the ATag
It is sufficient to reset the "valid" bits of all entries with SB.

Like all functional units of the CPU, the MCC ignores data presented on the internal bus during the abort cycle and retransmits the data it was sending after abort if still appropriate. Therefore, during a single cycle, MCC (and C
The PU) resets itself to the state that the p-op carrying a tag greater than or equal to the ATag that has never been issued.

FIG. 7 is a block diagram of the IEU 17. The IEU implements two data paths, a single cycle data path 400 and a multi-cycle data path 405. The single cycle data path executes all integer instructions that can be completed in one cycle, such as addition, subtraction, and digit shifting. Multi-cycle data paths include multiplication, division, and ASCI
Perform all integer p-ops that require multiple cycles, such as I and decimal arithmetic. The two data paths use a common register file 410 containing the physical registers to which the virtual registers are mapped as described for register reallocation.

Each data path includes elements coupled to a common bus set 412, and a bus combiner 415 separates between the two data paths. The single cycle data path includes a general purpose ALU 420, a barrel shifter 422, and special logic 425 for code propagation, leading zero and one directions, and so on. The multi-cycle data path includes a multiplication / division circuit 430 (8 × 32 multiplier array) and an ASCII
And a circuit 435 for decimal adjustment.

Input p-ops are received from p-op bus 52 and directed to p-op queue 450. Multiplexer 452 selects the executed p-op in the queue, and the executed p-op is communicated to single cycle control logic 455 (implemented by the PLA). For a single cycle p-op, control logic 455 controls the single cycle data path element. In the case of a multi-cycle data path p-op, control logic 455 controls the multi-cycle elements in the first cycle of p-op and provides addresses to microcode ROM 460. Microcode ROM 406 provides control of subsequent cycles of the p-op along with multi-cycle control logic 462 (PLA).

In the case of ALU p-ops, the result is stored in a register, the termination is immediately entered into the termination queue 470, and the contents of the termination queue 470 are sent out on the IEU termination bus. In the case of a memory write, the result is advanced directly to DXBus (in which case the end is entered into the end queue), or
Or DXBus output queue 475 for subsequent output
Which is either located within. When the bus becomes available, the termination is entered into the termination queue.

The depth of the P-op queue 450 is eight. The P-op queue has a plurality of read ports and one write port. Queue control logic 480 controls the queue so that it typically functions like a FIFO (first in first out), but also supports out-of-order reads. Queue control logic indicates whether the queue has any entries. Queue control logic also identifies the location of the p-op in the queue.

If the p-op queue receives a p-op when the queue is empty, the p-op is immediately decoded and an appropriate control signal is generated. An execution readiness check is performed at the time when decoding of the p-op is in progress. This check includes data operand and flag operand dependencies, and some special execution criteria such as sequential execution and functional unit serialization.
If the p-op fails the execution readiness check, some or all control signals are disabled. If the p-op is not executed, the p-op is placed in the queue.

If there are entries in the queue, the queue
Works like a FIFO. The first p-op in the queue and the next youngest p-op in the queue are read. Execution preparation logic 482 performs a check on both p-ops. The readiness check for the p-op at the head of the queue includes data operand dependencies. If the p-op at the head of the queue passes the execution readiness check, the p-op is decoded and executed. If the p-op cannot be performed, it is reissued for testing in the next cycle of operation.

Execution readiness checks for the next youngest p-op in the queue include data operand and flag dependencies, interlocks for the first p-op in the queue, and special execution (such as sequential execution) for that p-op. Including whether or not the subject of the standard.
For example, it is checked whether a valid bit is set in the source register required by p-op. If the first p-op in the queue fails to execute, if the next youngest p-op in the queue has passed all of the execution readiness checks, this p-op is decoded and executed. If both the p-op at the head of the queue and the next younger p-op in the queue can be successfully executed, the head of the queue is executed.

The multiple read pointers and one write pointer keep track of the operation of the queue. If the next young p-op
Is executed, the corresponding real pointer is updated to point to the next entry in the queue. If the p-op at the head of the queue is executed, the first read pointer is
Obtaining the value of the read pointer, the second read pointer is updated to point to the next entry in the queue.
The write pointer is used to point to the first empty position in the queue. During the truncation cycle, all pointers are compared to the truncation tag and set to the appropriate value based on the result.

Queue control logic 480 has a status bit for each entry in the queue. The status bit is set to "valid" while loading a new p-op into the queue. If the entry in the p-op queue is to be cleared during the abort cycle, the appropriate status bit is set to "invalid". The identified p-op for execution is decoded. If the p-op identified for execution is a single-cycle p-op, the control signals for the single-cycle data path 400 (register file, ALU, barrel shifter, and special logic) are controlled by control logic 455.
Generated by A single cycle p-op is executed during a single clock cycle. During this time, the multi-cycle data path 405 performs no function.

If the p-op identified for execution is a multiple cycle p
If -op, the first state control signal is generated by the single cycle control logic. Single cycle control logic also activates microcode ROM 460. Control signals for the remaining states are generated from the microcode ROM and the multi-cycle control logic 462. Multi-cycle data path 405 performs operations during this time. Multi-cycle operation uses only register file 410 from the single cycle data path.

It is possible to perform simultaneous (parallel) execution of P-ops. If the p-op identified for execution is a multi-cycle p-op, a possible performance benefit is obtained by executing the next single cycle p-op from the queue. Single cycle p using single cycle data path
Multi-cycle p-ops can also be performed using multi-cycle data paths. If there is data or status flag dependency on multiple cycles p-op, then no single cycle p-op is performed. The single cycle p-op is not executed even during the time when there is a resource conflict between the multi-cycle p-op and the single cycle p-op (during writing to the register file and updating the status flag).

The multi-cycle control logic has a state machine that identifies the state of operation. An integer execution unit can take one of four states: single cycle, multiple cycle, simultaneous, or idle.

The bus between the single cycle data path and the multi cycle data path is disconnected by bus combiner 415 during simultaneous operation. These buses are normally connected during multi-cycle operation to transfer data from the data file and / or use the results from the previous p-op (for the next p-op). Is possible.

If a p-op is identified as feasible, the p-op is presented to single-cycle control logic and / or multi-cycle control logic. If the functional unit finds that it is busy, no p-op is performed. This is signaled back to p-op queuing control, ready to execute the logic. Appropriate adjustments are made to the multiple read pointers.

Typically, the p-op queue, queuing control logic, and readiness logic attempt to maintain the issuance of p-ops based on data op and interlock resolution and special execution criteria. The control logic of the various functional units within the IEU (ALU, barrel shifter, special logic, multiply / divide circuit) resolves hardware resource conflicts and performs either single-cycle, multi-cycle, or simultaneous operations. If a resource conflict is signaled by a signal called QNEXT and the issued p-op cannot be executed, it must be reissued by the p-op queuing control logic. Flag stack
Flags are tracked using 485.

Conclusion Having described the preferred embodiment of the invention completely,
Various modifications, alternatives, and equivalents may be used. For example, while the embodiments described above have been implemented using separate chips for each functional unit, the basic architecture using separate pipeline control is equally effective and useful in a single chip embodiment. Would. Similarly, while this particular embodiment executes a particular instruction, other embodiments can be designed to execute other instruction sets.

Also, while a specific mechanism for communicating tags to functional units (tag status bus using OOTag or ATag using encoded tags) has been described, other possibilities exist. One possibility in a system where at most np-ops can be pending at a time is to represent the tag as a single set of bits in an N-bit vector, where N is greater than or equal to n. . Undecided p
Issue these tags sequentially so that the collection of ops is represented by the contiguous (in a cyclic sense) group of set bits in the N-bit vector. This vector is communicated to the functional unit to indicate status, while signaling abort by a similar type of vector.

Accordingly, the above description and accompanying drawings are not intended to limit the scope of the present invention, which is limited by the appended claims.

Continuing the front page (72) Inventor Stilles David Earl United States of America California 94087 Sunnyvale Dartshire Way 830 (72) Inventor Van Dyke Corvin Es United States of America California 94539 Fremont Kayuga Court 45770 (72) Inventor Meter Shrenik United States of America 95148 San Jose Mount Isabel Court 3164 (72) Inventor Faber John Gregory United States California 95124 San Jose Racer Ancourt 5246 (72) Inventor Greenray Dale Earl United States of America 95124 San Jose Redwood Drive 1744 (72) Inventor Calgnoni Robert A. United States California 94087 Sunnyvale Mourlane 1594 (56) Reference JP-A-61-107471 (JP, A) Open Akira 60-129838 (JP, A) JP Akira 58-1246 (JP, A) JP Akira 58-178464 (JP, A) (58 ) investigated the field (Int.Cl. ^7, DB name) G06F 9 / 38

Claims (15)

(57) [Claims] 1. An apparatus for issuing a series of operations each of which achieves a state of one outstanding operation when issued, and a plurality of units connected to an issuing apparatus each capable of executing at least two or more of several outstanding operations. A functional unit; a device for assigning a tag to each outstanding operation that is a member of a set of tags ordered to determine the relative age of the two outstanding operations by examining the assigned tags; A computer processor, comprising: a device for determining when an operation has been performed and completed; and a device for limiting the number of outstanding operations to ensure the uniqueness of the outstanding tag. 2. The method according to claim 1, wherein said limiting device allows at most n operations to be outstanding at a time, and wherein said tags are issued sequentially over a range greater than or equal to 2n. The computer processor of claim 1, wherein the relative age of the outstanding operations can be determined by a signed comparison of their tags. 3. An apparatus for determining an oldest outstanding operation and a tag marking a boundary between the outstanding operation and the operation to be retired, whereby at least one of the functional units indicates that the operation has been successfully retired. The computer processor of claim 1, further comprising: a notification device. 4. An apparatus for grouping adjacent operations such that retirement of any operation in the group is performed only when all operations in the group can be retired. 4. The computer processor according to claim 3. 5. A device for buffering memory writes at least during periods when their source operations have not yet been completed but are not retired, and a device for releasing buffered writes when those source operations have flowed out. 4. The computer processor of claim 3, further comprising: a device for completing placement of the buffered writes into cache or memory when their source operations have retired. 6. The computer of claim 5, further comprising a device for returning buffered write data to subsequent read operations before the write data is leaked or placed in a cache or memory. Processor. 7. The issuing device is responsive to an input instruction having an instruction set architecture including m programmer-visible registers, wherein at least some operations modify one of these registers, and The computer processor of claim 1 further comprising: a device for limiting the number to n; at least (m + n) physical registers; and a device for mapping programmer visible registers to physical registers. 8. An apparatus for guaranteeing that a physical register is not reused until an operation in which the physical register is changed is successfully retired, and a precedent state when an abnormal state is detected in a virtual-to-physical mapping. 8. The computer processor of claim 7, further comprising: an apparatus for restoring the contents of the programmer-visible registers. 9. Apparatus for converting an instruction in an input stream into a series of operations in response to an input stream containing the instructions, a plurality of functional units each capable of executing at least some of these operations, A device that communicates to more than one of the functional units (operations thus communicated are referred to as outstanding operations); and determining the relative age of the two outstanding operations by examining the tags for each outstanding operation. A device that sequentially allocates data in such a manner, a device that maintains information on the completion of operations by functional units for each outstanding operation, and a time when each operation that is combined with each functional unit and communicated is completed A device that communicates the end information together with the tag of the operation to the maintenance device; a device that determines the oldest outstanding operation; and a display of the oldest outstanding operation. Responsive to at least the termination information regarding the oldest pending operation,
A device allowing the retirement of the operation only when the completion information of the operation indicates that all the functional units have completed the operation normally; responding to at least the retirement of the oldest uncompleted operation, A device for updating the display of the oldest unfinished operation so as to indicate that the retired operation is no longer unfinished. 10. Apparatus for communicating to a functional unit a censoring tag specifying a group of operations to be evacuated in response to information that a given unfinished operation has been abnormally terminated; A device for flushing all outstanding operations specified by the censoring tag, a device for removing the designation of pending operations from the operation specified by the censoring tag, and a device for further tags starting with a value equal to the tag of the earliest operation leaked. The computer processor of claim 9, further comprising: a device for causing the tag assignment device to initiate assignment. 11. An apparatus for responding to an input stream containing instructions to convert instructions in the input stream into a series of operations, a plurality of functional units each capable of performing at least some of these operations, and these operations. To at least some of the functional units (operations communicated in this way are referred to as pending operations); a device to limit the number of pending operations to a predetermined maximum number; and assigning tags sequentially to each pending operation. A device, a device that maintains information on the end of the operation by the functional unit for each outstanding operation, and when each operation, which is combined with each functional unit and communicated, ends and whether the end is normal A device for communicating the end information together with the tag of the operation to the maintenance device; a device for communicating the indication of the outstanding operation to the functional unit; A device for sequentially retiring normally completed operations in response to the termination information; and at least a given uncompleted operation in response to information that a given pending operation has been abnormally terminated. A device that instructs the functional unit to drain all late outstanding operations, a device that is combined with the functional unit and drains all outstanding operations specified by the instruction device, and a tag of the earliest outstanding operation that flows out A device for causing the tag allocating device to start allocating further tags starting from the tag that was previously assigned. 12. A method for controlling a pipelined operation in a computer processor including a plurality of functional units each capable of executing at least some of the outstanding operations, the method comprising the steps of: Assigning to each outstanding operation a tag that is a member of a set of tags ordered so that their relative ages can be determined; determining when a given outstanding operation is completed; guaranteeing the uniqueness of the outstanding tags Limiting the number of outstanding operations to perform the method. 13. A branch operation in which at least some of the above operations are branch operations, wherein a step of predicting a result of an uncompleted branch operation, a step of detecting an erroneous prediction of an uncompleted branch operation, and 13. The method of claim 12, further comprising draining all outstanding operations issued. 14. The method of claim 1, wherein the issuing step is responsive to an input instruction having an instruction set architecture including m programmer-visible registers, wherein at least some operations modify one of these registers, and 13. The method of claim 12, further comprising: limiting the number to n; providing at least (m + n) physical registers; and mapping programmer-visible registers to physical registers. 15. A step for ensuring that a physical register is not reused until an operation that has changed the physical register has been successfully retired, and a precedent state when an abnormal state is detected in a virtual-to-physical mapping. 15. The method of claim 14, further comprising the step of restoring the contents of the register visible to the programmer, and hence the programmer.