JPS5580159A - Interface circuit test system - Google Patents

Abstract

PURPOSE: To make the false test of a high-speed transmission operation possible by selecting one of the tag-out false signal in a diagnosing register and a signal, which is obtained by folding a part of tag-in signals, and using the selected signal as a tag-out signal in case of test for the interface circuit.

CONSTITUTION: A bus-out signal and the false signal of a tag-out signal are held in diagnosing bus-out register 5 of channel interface control part 1 and diagnosing tag-out register 6 respectively, and contents are set by the command of IOC logic part 2. When on-line designation control line 29 is turned on, bus-out 22 from the channel and tag-out signal line 23 are made available, and further, bus-line to the channel and tag-in signal line 25 are made available. Meanwhile, when line 29 is turned off, contents of registers 5 and 6 are applied to sequence control part 3 to stop bus-in and tag-out signals to the channel; and when folding designation control line 30 is turned on, a service-out false signal is applied to control part 3 to make false test possible.

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