WO2007037384A1 - System having a self-synchronization type processing unit - Google Patents

Abstract

There is provided a system having a plurality of self-synchronization type processing units. One of the processing units include a signal exchange unit of input side for receiving a plurality of input signals supplied from the processing units of input side; a logic unit for generating an output signal according to the input signals; a signal exchange unit of output side for transmitting the output signals to at least one processing unit of the output side; a first judgment function for deciding an input signal not received and useless for generation of the output signal by the input signal received by the signal exchange unit of the input side; and a second judgment function for deciding an input signal which has not been received and need not be received according to the useless report indicating the output signal is useless received by the signal exchange unit of the output side. Furthermore, the signal exchange unit of the input side transmits a useless report to the processing unit of the input side for supplying the input signal which has not yet been received and need not be received according to the first judgment function or the second judgment function.

Description

 System having a self-synchronous processing unit

 Technical field

 [0001] The present invention relates to a system having a self-synchronous type, that is, an asynchronous type processing unit.

 Background art

 [0002] As a digital circuit design method, a synchronous design method in which the entire system is controlled by a global clock is widely adopted. On the other hand, self-timed (self-synchronous) design methods that take the command of clocks as a binding and aim for higher performance and lower power consumption by releasing the bindings, that is, asynchronous design methods are also being considered. ing. One of the advantages of self-timed design is that the connected circuit elements perform handshake to adjust timing, allowing design that does not depend on element delay or wiring delay. Self-timed design can also overcome some of the disadvantages and disadvantages of synchronous design. Disadvantages of synchronous design are, for example, malfunction when the computation time exceeds the clock period, and waiting for the clock boundary when the computation is completed earlier than the clock period.

 [0003] A number of proposed delay models for asynchronous circuits have been proposed. In U.S. Pat.No. 6,606,3 56, SDI (Scala ble Delay Insensitive) is a model that improves the performance of the DI (Delay Insensitive) model and QDI (Quasi Delay Insensitive) model. ) Propose model. US Pat. No. 6,732,336 proposes improving the performance of QDI circuits by employing asynchronous pulse logic (AP L) that replaces the two-phase or four-phase handshake of the QDI circuit with pulses. .

[0004] One of the advantages of asynchronous design over synchronous design is that you can proceed to the next without waiting indefinitely until the clock boundary when the operation is complete. However, in an asynchronous design, a predetermined protocol (handshake) is adopted to transfer data between elements or units without sharing a clock. For this reason, in the asynchronous design, the calculation should proceed faster. The overhead of handshaking between the power circuit elements is added. However, it is not always possible to obtain a faster result than the synchronous design.

 Disclosure of the invention

 [0005] One embodiment of the present invention is a system having a plurality of self-synchronous processing units. One processing unit of the plurality of processing units includes an input-side signal exchange unit for receiving a plurality of input signals respectively supplied from a plurality of input-side processing units, and a plurality of input signals. And an output side signal exchanging unit for transmitting the output signal to at least one output side processing unit. The processing unit further includes a first determination function that determines an unreceived input signal that is unnecessary for generating an output signal based on an input signal received by the input-side signal exchange unit, and the output-side signal exchange unit receives And a second determination function for determining an unreceived input signal that is not required to be received based on a notification that indicates that the output signal is not used. Then, the signal exchange unit on the input side transmits a waste notification to the input processing unit that supplies the unreceived input signal that has been judged not to be received by the first determination function or the second determination function.

 [0006] Another aspect of the present invention is a self-synchronous processing unit. One type of processing unit is an input-side signal exchange unit for receiving a plurality of input signals respectively supplied from a plurality of other input-side processing units, a logic unit, and at least one output side. Output signal exchange unit for transmitting output signals to other processing units, first determination function for determining unreceived input signals that are not required for generating output signals, and notification of unnecessary output signals And a second determination function for determining an unreceived input signal that is not required for reception. The signal exchange unit on the input side sends a waste notification to another processing unit on the input side that supplies an unreceived input signal that is judged as unnecessary by the first judgment function or the second judgment function. .

[0007] Another type of self-synchronous processing unit is one that does not have a logic section that generates an output signal. For example, it functions as a notch (including an inverter) or a branch. This processing unit forwards the waste notification sent from the output side to the input side. For this reason, this processing unit has an input-side signal exchange unit and an output-side signal exchange unit, and the input-side signal exchange unit is notified by the notification of the unnecessary output signal received by the output-side signal exchange unit. Not used for other processing units on the input side that supply unreceived input signals Send a notification.

 [0008] In a processing unit in which an output-side signal exchange unit transmits an output signal to a plurality of output-side processing units, an output signal is generated when a waste notification is received from all output-side processing units. It becomes useless. Therefore, the second determination function determines an unreceived input signal that is not required to be received when an output signal non-use notification is received from all of the plurality of output-side processing units.

 Another aspect of the present invention is a method for controlling a system having a plurality of self-synchronous processing units. This method is the first factor that an unreceived input signal that is unnecessary for generating an output signal is generated by the input signal received by the signal exchange unit on the input side, or received by the signal exchange unit on the output side. Due to the second factor that an unreceived input signal that is not received due to the unnecessary notification indicating that the output signal is not used is generated, it is sent to the processing unit on the input side that is scheduled to supply the input signal. Including sending.

 [0010] Propagation notification can be added to a handshake protocol for transferring a data signal between processing units by sending a confirmation signal (a data signal) when no data is input. . As a result, the handshake regarding the non-use notification can be performed by the data signal. One such handshake protocol is as follows, and signal transfer is confirmed on the input / output side by one of the following processes pl to p4.

 pi. When an input signal is received, a confirmation signal is sent to the processing unit (other processing unit) on the input side that is the source of the input signal.

 p2. A confirmation signal is sent as an unnecessary notification to the input processing unit (other processing unit) that is the source of the unreceived input signal, and the input processing unit (other processing unit) (Unit) Force Receives dummy input signal.

 p3. Send the output signal and receive the processing unit (other processing unit) force check signal on the destination output side.

 p4. If a confirmation signal is received when the output signal has not been transmitted, it is recognized as a non-use notification and a single output signal is transmitted.

[0011] On the input side, signal transfer is confirmed by processing pi or p2. On the output side In this case, signal transfer is confirmed by processing p3 or p4. Therefore, the processing unit, it is preferable that e Bei handshaking function of confirming the transfer of any 〖Koyori signal _P 4 from the processing pi.

[0012] According to another aspect of the present invention, there is provided a signal transmission method including a self-synchronous processing unit confirming transfer of a signal with another self-synchronous processing unit. It is a method. Confirming signal transfer (handshaking) includes:

[0013] When an input signal is received by the signal exchange unit on the input side, a confirmation signal is transmitted to another processing unit on the input side of the input signal supply source,

 The first factor that causes an unreceived input signal that is not necessary for generating the output signal due to the input signal, or the unnecessary notification that indicates that the output signal is not received, received by the output side signal exchange unit, is not used for reception. Due to the second factor that causes unreceived input signals to be generated, a confirmation signal is sent as a non-use notification to other processing units on the input side of the source of the unreceived input signal, and the destination of the confirmation signal Receiving dummy input signals from other processing units on the input side,

 Send output signals, receive confirmation signals from other processing units on the output side, and

 When a confirmation signal is received when the output signal has not been transmitted, it is recognized as a non-use notification and a dummy output signal is transmitted.

 Brief Description of Drawings

FIG. 1 is a diagram showing an outline of a self-synchronous system.

 FIG. 2 is a diagram showing a schematic configuration of a self-synchronous processing unit.

 FIG. 3 is a diagram showing a two-wire self-synchronous element.

 FIG. 4 is a flowchart showing the internal operation of the element shown in FIG.

 FIG. 5 is a flowchart showing an outline of the internal operation of the processing unit shown in FIG.

 FIG. 6 is a flowchart showing a more detailed internal operation of the processing unit shown in FIG.

 FIG. 7 shows a self-synchronous NOT gate element.

[FIG. 8] FIG. 8 (a) is a diagram showing a synchronous signal branch, and FIG. 8 (b) is a diagram showing a self-synchronous signal branch. 9] A diagram showing a self-synchronous buffer element.

 FIG. 10 is a timing chart in which handshaking is performed in the element of FIG.

 FIG. 11 is a timing chart of an example different from FIG.

 [FIG. 12] A timing chart of another example different from FIG.

 FIG. 13 is a timing chart of another example different from FIG.

 FIG. 14 is a flowchart showing the internal operation of a self-synchronous flip-flop.

 FIG. 15 is a flowchart showing a more detailed internal operation of the self-synchronous flip-flop.圆 16] An example of combinational logic circuit.

 [FIG. 17] A circuit in which the combinational circuit of FIG. 16 is changed to a configuration using multiple processing units with two inputs and one output.

 18] FIG. 18 (a) to FIG. 18 (h) are examples showing the operation of the circuit shown in FIG.

 FIG. 19 (a) to FIG. 19 (e) are different examples showing the operation of the circuit shown in FIG.

 [FIG. 20] FIGS. 20 (a) to 20 (e) are examples showing the operation of the circuit shown in FIG. 17 by handshaking.

 [FIG. 21] FIG. 21 (a) to FIG. 21 (d) are examples in which the operation of the circuit shown in FIG.

 [FIG. 22] FIG. 22 (a) to FIG. 22 (d) are examples in which the operation of the circuit shown in FIG.

[23] Example of sequential circuit.

[24] A circuit in which the sequential circuit in Fig. 23 has been changed to a configuration that uses multiple 2-input, 1-output processing units.

 [FIG. 25] FIGS. 25 (a) to 25 (d) are examples showing the operation of the circuit shown in FIG. 24 by handshaking.

 [FIG. 26] FIGS. 26 (a) to 26 (d) are examples in which the operation of the circuit shown in FIG.

 [FIG. 27] FIGS. 27 (a) to 27 (d) are examples in which the operation of the circuit shown in FIG.

[Fig.28] Fig.28 (a) to Fig.28 (d) show the operation of the circuit shown in Fig.24 following the step of Fig.27 (d). An example shown by Jake.

 [FIG. 29] FIGS. 29 (a) to 29 (d) are examples in which the operation of the circuit shown in FIG.

 [FIG. 30] FIGS. 30 (a) to 30 (d) are examples in which the operation of the circuit shown in FIG.

 [FIG. 31] FIG. 31 (a) to FIG. 31 (d) are examples in which the operation of the circuit shown in FIG.

 BEST MODE FOR CARRYING OUT THE INVENTION

 [0015] One embodiment of the present invention is a system having a plurality of self-synchronous processing units, based on an input-side signal exchange unit for receiving a plurality of input signals, and the plurality of input signals, A logic unit for generating an output signal; and a signal exchange unit on the output side. When the logic implemented in the logic part of the processing unit is 2-input AND, if one input signal is true, it is necessary to wait for the other input signal to determine the output signal. However, if one input signal is false, the output signal is false, and the other input signal is a signal that is unnecessary (don't care) for generating the output signal. Therefore, in the self-synchronous processing unit, it is possible to output an output signal that is highly likely to be received at different timings and does not need to wait for the other input signal.

 Similarly for other logics such as 2-input OR, an unreceived input signal may become don't care depending on an input signal received at a certain timing. In the case of a selector, if the selected side is determined by the input signal received at a certain timing, it is not selected! The unreceived input signal on the side becomes don't care.

[0017] If the output signal is don't care, the input signal in the processing unit that generates the output signal is also don't care. Therefore, the first decision function determines the unreceived input signal that is not required for generation of the output signal (first factor). Furthermore, in the second decision function, an unreceived input signal that is not required for reception is determined by the notification of the unnecessary output signal (second factor). In this system, a waste notification is further sent to the processing unit on the input side that supplies an unreceived input signal that has been judged as unnecessary by the first judgment function or the second judgment function. [0018] When an output signal is determined by one input signal in a certain processing unit, the output signal is transmitted to the other processing unit on the output side by the signal exchange unit on the output side. At the same time, with respect to an unreceived input signal determined to be unnecessary by the first determination function, an input side signal exchange unit is connected to the input side processing unit that is to supply the unreceived input signal. Thus, a non-use notification is transmitted. Further, in the processing unit on the input side, the useless notification is further transmitted to other processing units on the input side that have not been received by the second determination function. Accordingly, since an output signal is propagated from a certain processing unit to the output side, signal processing proceeds and the waiting state of the downstream processing unit is released. In addition, since the unnecessary notification is propagated to the unreceived input side, the waiting state of the upstream processing unit can be released and the signal processing can be advanced, so that the processing speed of the system can be improved.

 [0019] Furthermore, it is desirable that the signal exchange unit on the output side of the self-synchronous processing unit transmits the output signal as a pulse signal each time an output signal is generated by the logic unit based on the input signal. Regardless of whether or not the value of the output signal is changed by logic, the processing unit of the embodiment of the present invention outputs a pulse of the output signal every time the output signal is generated. Therefore, the processing unit transmits the output signal once per process for one user clock cycle. This reflects the nature of the synchronous user circuit, “All signal lines transmit values once every clock cycle”.

 [0020] In the self-synchronous system of the embodiment of the present invention, between all the processing units,

A handshake is performed once. Each time a handshake is performed, it can be considered that the processing for one cycle of the user clock of the synchronous user circuit proceeds. For this reason, self-synchronous, that is, asynchronous circuit design is possible with the widely used concept of synchronous design.

[0021] It is desirable that the signal exchange unit on the output side transmits the output signal as a signal that is displaced in three states. An example of a signal that shifts to three states is a signal that shows neutrality and binary values (two states) that do not include it. It is also possible to transmit the output signal (input signal) with a two-wire system. However, in order to use the output signal as a confirmation signal when propagating a waste notification downstream, in the case of the 2-wire system, if the delay amount is different, the result of handshake may be different. By transmitting the output signal as a signal that shifts to three states, the output signal is single-wire (1-wire). Since the signal (input signal) can be exchanged, the problem with delay can be solved. The three states can be realized by, for example, converting the voltage into plus, zero, and minus if it is an electric signal. For an optical signal, for example, the polarization state can be changed to three states.

 [0022] The processing unit preferably includes a memory for storing an input signal that cannot be processed by an unreceived input signal or a confirmation signal. The self-synchronous processing unit preferably includes a memory for storing a received signal, for example, an input signal or a confirmation signal, as a token (event token) for advancing an event. Since the processing queue has a memory for storing signals that cannot be processed, it is possible to proceed with processing related to the received signals.

 [0023] The self-synchronous system according to the embodiment of the present invention does not require a global clock. Therefore, there is no restriction that the processing time (latency) of each processing unit included in the self-synchronous system must be shorter than the global clock period. For this reason, the logic of the logic part of the processing unit or the connection of the processing unit can be changed flexibly. Therefore, the self-synchronous system is suitable for a reconfigurable system capable of changing the logic for generating the output signal in the logic unit.

 [0024] In one form of the reconfigurable system, the signal exchange unit on the input side has a function of changing the processing unit on the input side, and the signal exchange unit on the output side includes the processing unit on the output side. It is a system including a processing unit having a function to change. An example of such a system is that the input side and output side signal exchange units include communication or data transmission functions, and the processing units connected to each can be changed wirelessly or by wire. Another form of the reconfigurable system is a communication system that enables exchange of signals between a plurality of processing units, and further includes a communication system that can reconfigure the connection of the plurality of processing units. Is.

[0025] This self-synchronous system may be a distributed system in which a plurality of computers are connected via a computer network realized by radio or wire. In addition, an integrated circuit system in which a plurality of elements having appropriate arithmetic functions are housed in one chip, and there is an electronic device may be connected by light. One form of integrated circuit unit is It includes a number of processing units and a routine damatrice for transmitting signals between the processing units. An example of a routing matrix is a circuit in an integrated circuit unit that can be reconfigured by changing connections between at least some of the processing units included in the plurality of processing units.

 FIG. 1 shows an example of a self-synchronous integrated circuit device. This integrated circuit device (integrated circuit unit, device or system) 1 is transmitted by FFT (Fast Fourier Transform) operation, various calculation processes including decoding of data compressed by MPEG, routing by IP address, and packet. It can be used for a wide variety of purposes such as network processing including data reconstruction. The integrated circuit unit 1 can be configured to execute one or more processes as a single system. It is also possible to construct one system by combining multiple integrated circuit units 1. Further, it is possible to construct one system by combining one or a plurality of integrated circuit units 1 with a general-purpose CPU or other dedicated circuit.

[0027] The integrated circuit unit 1 has a plurality of processing units (Process! Ng Unit (PU), Processing Element (PE) or i Conngurable Logic Block (LB), and PU in the down) that can change each arithmetic logic. 10 and a routing matrix 5 for configuring a path connecting the plurality of processing units (PUs) 10. The routing matrix 5 is a connection unit (switching unit or switching unit or wiring unit) that can change the connection configuration of the routing matrix 5 by changing the connection between the wiring (wiring group) 6w for transmitting data between PUslO and the wiring group 6w. Selector unit) 6s. The integrated circuit unit 1 further supplies the configuration memory 2 storing the configuration data 7 of PUslO and the routing matrix 5 and supplies the configuration data 7 from the configuration memory 2 to PUslO. The configuration data control unit 3 is provided. The configuration memory 2 stores multiple sets of configuration data 7. The control unit 3 selects one of a plurality of sets of configuration data 7 and supplies it to the PUslO and, if necessary, the routing matrix 5. The routing matrix 5 also has a function of transferring the configuration data 7 to the PUslO and the connection unit 6s. [0028] The routing matrix 5 is not limited to one in which the wiring 6w is arranged in a matrix. For example, PUs 10 may be connected to form a network node. The routing matrix 5 is also a wired communication system that enables signal exchange between a plurality of PUs 10. When PUslO is distributed, PUsl 0 can be connected by a wireless communication system. By reconfiguring the connection of PUs 10 with a wired or wireless communication system, the circuit configured with PUslO can be changed.

 FIG. 2 shows a schematic functional configuration of the self-synchronous asynchronous processing unit (PU) 10. The PU 10 includes an input interface 11 that is a signal exchange unit on the input side, a logic unit 12 that determines an output Y, and an output interface 13 that is a signal exchange unit on the output side. The input interface 11 receives two input signals Ad and Bd supplied from two other input side PUslOa and 10b, respectively. The two input signals Ad and Bd are not necessarily supplied from PUslOa and 10b at the same timing. Therefore, the input interface 11 serving as the signal exchange unit on the input side receives the two input signals Ad and Bd, respectively.

 The logic unit 12 determines the output Y based on the inputs A and B given by the input signals Ad and Bd, respectively. The output interface 13 transmits an output signal Yd indicating the output Y of the logic unit 12 to another processing unit (PU) lOy on the output side. Furthermore, the PU 10 includes a control unit 15 that controls the internal operation of the PU 10. In addition, the PU 10 includes a queuing memory 14 that stores a signal that cannot be processed due to an unreceived signal.

 The control unit 15 includes a first determination function 18 and a second determination function 19. The first determination function 18 determines an unreceived input signal that is not necessary for generating the output signal Yd based on the input signal Ad or Bd received by the input interface 11. The second determination function 19 determines an unreceived input signal that is not received by the output interface 13 received notification by the output interface 13 that is not used.

Furthermore, the control unit 15 includes a handshake function 17 for confirming transmission / reception of signals. Handshake function 17 confirms transmission and reception of input signals Ad and Bd with PUslOa and 10b on the input side. The handshake function 17 Check transmission / reception of output signal Yd to / from PUlOy on the power side.

When the handshake function 17 receives the input signal Ad, the handshake function 17 transmits a confirmation signal (attenuation signal) Ak to the input PUlOa on the input side of the input signal Ad. Through this process, PU10 exchanges the input signal with PUlOa once (nond shake). In other words, this processing power is one of the handshake (protocol) between SPU10 and PUlOa.

 Similarly, when the handshake function 17 receives the input signal Bd, the handshake function 17 transmits a confirmation signal (attenuation signal) Bk to the PUlOb on the input side of the supply source of the input signal Bd. This process is one of the handshake (protocol) between PU10 and PUlOb. The handshake function 17 transmits the output signal Yd and receives the acknowledge signal Yk from the PUlOy on the output side of the transmission destination. This process is one of the handshaking (protocol) between PU10 and PUlOy.

 [0035] Further, the handshake function 17 is not used for an input-side processing unit that supplies an unreceived input signal determined to be unnecessary by the first determination function 18 or the second determination function 19. Send notifications. The handshake function 17 transmits one or both of acknowledgment signals Ak and Bk as a non-use notification (don't care notification) to one or both of PU1 Oa and 10b on the input side that are determined not to be received. Further, the handshake function 17 receives a dummy input signal supplied with one or both of the PUslOa and 10b to which the acknowledge signal is transmitted in a state where the input signal is not received. These processes are one of the handshakes (protocols) between PU10 and PU10a and Z or 10b.

 [0036] Further, the handshake function 17 receives a don't care notification from the PUlOy on the output side. When the handshake function 17 receives the acknowledge signal Yk when the output signal Yd is not transmitted, it recognizes it as a don't care notification. The handshake function 17 transmits a don't care notification to the second determination function 19 and transmits a dummy output signal Yd. This is one of the handshake (protocol) between the processing power PU10 and PUlOy.

The control unit 15 has a reconfiguration function 16 for changing the processing content of the PU 10 by the configuration data 7 supplied from the configuration memory 2 via the routing matrix 5. Reconfiguration function 16 is based on configuration data 7 Change the logic of logic part 12 of PU10. The reconfiguration function 16 changes the processing unit connected to the input interface 11 and the output interface 13. As a result, the data path composed of a plurality of PUslOs is reconfigured in the system 1 and the function of the data path is changed. In this example, the input interface 11 and the output interface 13 are connected to other PUs via the routing matrix 5. By changing the configuration of the connecting unit 6s in the routing matrix 5, the data node composed of multiple PUslOs can be reconfigured in the system 1.

 FIG. 3 shows an example of a 2-wire, 2-input, 1-output self-synchronous element 90. The 2-input 1-output logic element has two input signals, signals A and B, and one output signal, signal Y. For each signal, a data line (such as AO) for transmitting logic "0", a data line (such as A1) for transmitting logic "1", and an acknowledge line (such as Ak) are required. For this reason, a total of nine signal lines are connected to the element 90.

 FIG. 4 is a flowchart showing the internal operation of the self-synchronous processing element (PE) 90 shown in FIG. First, in step 91, the PE 90 waits for an input signal A0, Al, BO or B1 whose input data line force also indicates logic “0” or logic “1” to be transmitted. When these signals are transmitted, PE 90 determines the source of the input signal in step 92. In step 93 or 94, the PE 90 returns an acknowledge signal Ak or Bk corresponding to the input signal to the supplier. In step 95, PE90 determines whether the output value needs to be changed. If the output signal Y0 or Y1 needs to be changed, PE 90 transmits a new output value in step 96. Thereafter, in step 97, the PE 90 waits for the output signal acknowledgment Yk.

 [0040] In this self-synchronous element 90, the input signal and the output signal are the same data signal only in the difference between the input side and the output side. A system using this self-synchronous element 90 is correct if the data signal and acknowledge signal are guaranteed not to be lost or propagated in the middle of transmission and a circuit design corresponding to an appropriate delay model is made. Operate

A self-synchronous element (processing unit PU) 10 shown in FIG. 2 is a one-wire, two-input, one-output self-synchronous element (processing unit). The 1-wire PU10 is connected to one logical signal. Assign two actual signal lines. Therefore, a total of 6 signal lines are connected to PU10. The two signal lines for the other PU10 are the data line 5a and the signal line 5b for acknowledgement, respectively. The data line 5a is a signal line for transmitting logic "0" or logic "1" as the data signals Ad, Bd and Yd. The acknowledge signal line 5b is a signal line for transmitting the acknowledge signals Ak, Bk, and Yk.

 The output interface 13 is connected to a positive potential power line and a negative potential power line. The output interface 13 outputs a positive pulse when transmitting a logic “1 (true)” as the output signal Yd, and outputs a negative pulse when transmitting a logic “0 (false)”. Therefore, the data line 5a propagates, as data signals Ad, Bd, and Yd, a positive pulse that transmits logic “1” and a negative pulse that transmits logic “0”. The relationship between logic and potential is only an example, and the relationship can be reversed.

 FIG. 5 is a flowchart showing the internal operation related to data output of the self-synchronous PU 10 shown in FIG. This flowchart shows the operation of the data output except for the don't care notification function for comparison with the 2-wire self-synchronizing element 90. In step 21, the PU 10 waits for the input signal Ad or Bd to be received. In step 22, when the PU 10 confirms reception of the input signal Ad, the PU 10 performs handshake by transmitting the acknowledge signal Ak in step 23a. In step 24a, PU10 waits for input signal Bd. When the input signal Bd is received, in step 25a, the PU 10 transmits an acknowledge signal Bk and performs handshaking. On the other hand, when the reception of the input signal Bd is confirmed in Step 22, the PU 10 transmits the acknowledge signal Bk and performs handshaking in Step 23b. Further, in step 24b, the PU 10 waits for the input signal Ad. When the input signal Ad is received, in step 25b, the PU 10 transmits an acknowledge signal Ak and performs a handshake.

 [0044] When the input signals Ad and Bd are received, in step 26, the PU 10 transmits the output signal Yd. In step 27, the handshake is completed when the anode signal Yk is received.

As described above, the basic operation of the one-wire PU 10 is to transmit and receive signals once for all the input / output lines in a single process. In other words, all inputs and outputs in PU10 Ability to transmit signals once per line Equivalent to one cycle of the user clock. For this reason, unlike the two-wire self-synchronous design element, it has the same property as the synchronous element: “All signal lines transmit values once per clock cycle”. Therefore, a clock synchronous system design can be applied to a system using PU 10.

 [0046] In order to proactively implement clock-synchronous system design, the basic operation of PU10 is as follows. It receives signals once for all inputs and then outputs once, and only one input is used. It is not allowed to advance ahead, and the output is transmitted every time regardless of whether the output value needs to be changed.

 In the present embodiment, a clock synchronous user circuit can be implemented without using a global clock by the device (system) 1 having the PU 10. For this reason, the man-hours for clock skew adjustment and critical path adjustment can be omitted. Furthermore, the following non-shake backflow function allows the processing to proceed with only one side input while maintaining the characteristics compatible with the clock synchronous type. Furthermore, by using the memory 14 for queuing, the processing speed can be improved at any time while retaining the feature of being compatible with the clock synchronous type.

 FIG. 6 is a flowchart relating to the internal operation of the 2-input 1-output self-synchronous PU 10 shown in FIG. This flowchart shows the internal operation including the handshake backflow function. First, in step 31, the PU 10 waits for pulses from the input data lines Ad and Bd and the output acknowledge line Yk.

A typical example shown in FIG. 5 is a case where a data pulse is supplied from the input data line Ad. Since the PU 10 has received the input signal Ad, in step 35, the PU 10 issues an acknowledge pulse from the input acknowledge line Ak (analog signal Ak). Next, before waiting for the other data line Bd pulse (input signal Bd), PU10 determines in step 36 whether or not the input signal Bd is unnecessary (don't care) power to determine the output signal Yd. . If the input signal B d is required, the PU 10 moves to step 39. In step 39, since the output signal is not determined, PU10 holds the input signal Ad in step 46 and waits for the input signal Bd to be received. Next, when the input signal Bd is received in step 31, the PU 10 transmits the acknowledge signal Bk in step 35. Through step 39, PU10 In step 41, the output signal Yd is transmitted. PU10 returns to step 31 and waits for acknowledge signal Yk.

 [0050] On the other hand, in step 36, the value of output Y is determined only by the value of input A, and the value of input B may be don't care. That is, in step 36, when the output signal Yd is determined by the input signal Ad and the input signal Bd is don't care, the PU 10 transmits the acknowledge signal Bk without waiting for the input signal Bd in step 38. At the same time, in step 41, PU10 transmits the determined output value as pulse signal Yd. The acknowledge pulse Bk transmitted in step 38 is not a receipt response message “received data pulse Bd” but a notification message “input B is don't care”.

 [0051] Thereafter, returning to step 31, the PU 10 waits for the acknowledge pulse Yk and the data pulse Bd. This data pulse Bd does not indicate the logical value of the input B, but is an acknowledgment response message to the notification that “the value of the input B is don't care”, either a positive pulse signal or a negative pulse signal.

 [0052] In step 31, when the input signal Bd comes before the input signal Ad, the operation of the PU 10 is only the exchange of the input signal Ad and the input signal Bd in the above. In the following, the noise signal propagated through the input lines A and B will be described as the input signals Ad and Bd, and the pulse signal propagated through the output line Y will be described as the output signal Yd. The same applies to the acknowledge signals Ak, Bk and Yk.

 [0053] As described above, there may be a case where the data signal Yk for the purpose of a non-shake (protocol) indicating that the output signal has been confirmed comes in step 31. The acknowledge signal Yk in this case is a notification from the PU 10y on the output side that “the value of output Y is don't care”. Therefore, in step 52, the PU 10 transmits a dummy output signal Yd as a don't care acknowledgment response. The pulse signal of this output signal Yd can be either positive or negative.

[0054] At the same time when the dummy output signal Yd is output, the PU 10 outputs the acknowledge signals Ak and Z or Bk to the PUlOa and Z or 10b on the input side that is to supply the unreceived input signal in step 57. Send. For example, if the input signal Ad has been received , PU10 transmits an acknowledge signal Bk to PUlOb. If the input signals Ad and Bd are not received, PU10 transmits acknowledge signals Ak and Bk to PU10a and 10b, respectively. These acknowledge signals are messages that notify the processing queue on the signal transmission side that the values of signals A and B are don't care. In step 31, PU10 waits for a dummy input signal Ad or Bd (dummy output signal in PU10a and 10b) of the corresponding don't care acknowledgment response.

Therefore, the PU 10 has the following four types as handshake protocols for confirming signal transmission / reception.

 Type 1) When receiving the input signal Ad or Bd, the PU 10 transmits the acknowledge signal Ak or Bk to the input PUlOa or 10b on the input side of the input signal Ad or Bd.

 Type 2) PU10 sends an acknowledge signal Ak or Bk to PUlOa or 10b on the input side of the unreceived input signal Ad or Bd as an unnecessary notification (don't care notification), and dummy input from PUlOa or 10b Receives the signal Ad or Bd.

 Type 3) PU10 transmits output signal Yd and receives acknowledgment signal Yk from PUlOy on the destination output side.

 Type 4) When the acknowledge signal Yk is received when the output signal Yd is not transmitted, the PU 10 recognizes it as a don't care notification and transmits a dummy output signal Yd.

 [0056] Type 1 and Type 3 handshakes relate to normal data pulse transmission and reception. Type 2 and Type 4 handshakes are intended to propagate don't care notifications using data pulses and alarms.

[0057] At the same time as PUlOb on the input side outputs the normal input signal Bd, PU10 may output the acknowledge signal Bk for notification that the input B value is don't care! In that case, the sending PUlOb misunderstands the acknowledgment signal Bk as a normal receipt response. The receiving PU 10 misunderstands the input signal Bd as a don't care acknowledgment response. Even if they are misunderstood in this way, there is no problem in the operation of System 1 as the handshake for one cycle of the user clock has been completed. Therefore, it is not necessary to take any measures to prevent this misunderstanding. The flowchart shown in FIG. 6 will be described in more detail. In step 31, PU10 waits for a signal to be received. The signals received by PU10 are input signals Ad and Bd, and output signal acknowledge signal Yk. Upon receipt of either signal, PU 10 determines in step 32 whether or not a handshake for one signal has been completed based on that signal. There are four types of handshaking. If one of the signals has been sent in advance and the receipt confirmation signal has been received, the handshake (type 1 or type 3) for one user clock is completed. Therefore, PU10 returns to step 31 and waits for the next signal.

 [0059] However, if the handshake is completed in step 32! /, The transmission waits for the data line in which the handshake is completed in the queuing memory 14 in step 43! /! Check if there is a signal. If there is a signal waiting to be transmitted, PU 10 transmits the signal in step 44. For example, it is assumed that the input signal Ad is continuously received and the input signal Bd becomes don't care by the first and second input signals Ad. In this case, first, PU10 outputs an acknowledge signal Bk for don't care notification in response to a non-input signal Bd corresponding to the first input signal Ad, and the second input until the handshake is completed. The state may be maintained without outputting the acknowledge signal Ak to the signal Ad.

 On the other hand, the PU 10 may transmit the acknowledge signal Ak prior to the second input signal Ad. In this case, the PU 10 can store the second don't care notification for the PUlOb on the input side in the memory 14 for queuing. As a result, processing proceeds in PUlOa and its upstream processing unit. In this case, in step 32, the PU 10 receives the input signal Bd with respect to the acknowledge signal Bk of the first don't care notification, and then in step 44, the next don't care stored in the queuing memory 14 is received. An acknowledge signal Bk can be output. By this don't care notification, processing of the PU1 Ob and its upstream processing unit can proceed.

The same applies to the output signal Yd. If the input signal Bd is don't care for the first and second input signals Ad, the first and second output signals Yd are determined by the first and second input signals Ad. Therefore, the first output signal Yd is transmitted, and the second output signal Yd is stored in the queuing memory 14. In step 32, P When U10 confirms the acknowledge signal Yk for the first output signal Yd, it can transmit the next output signal Yd in step 44.

[0062] Further, as shown below, there may be a signal that is held in the event token state without being able to proceed with processing while receiving a signal and not transmitting an acknowledge signal. In that case, in step 48, the processing of the held signal is started without waiting for the reception of the next signal.

 [0063] If the handshake is not completed by the received signal, a new cycle is started. First, in step 33, if the queuing memory 14 is full, or if continuous reception is not permitted, the PU 10 cannot perform a handshake by performing an acknowledgment. Therefore, in step 49, the PU 10 stores the received signal as an event token in the queuing memory 14, and waits for the next signal. That is, the memory 14 stores a received input signal that requires another input signal in order to generate an output signal, and stores a signal that becomes another event token including the input signal.

 [0064] In step 34, if the received signal is the input signal Ad or Bd, it is a data input. If the received signal is an acknowledge signal Yk, it is a don't care notification. If it is an input signal, PU 10 outputs acknowledge signal Ak or Bk in step 35.

[0065] In step 36, the PU 10 determines whether or not the received input signal is a force that makes the other input signal unnecessary (don't care) (determination of the first factor). When a don't care input signal is generated, the PU 10 determines in step 37 whether or not a don't care notification can be transmitted for the unreceived input signal. For example, when the input signal Ad is continuously received as described above, the PU 10 receives the acknowledge signal Bk that becomes the second don't care notification until it receives the input signal Bd that is acknowledge to the PUlOb on the input side. Cannot output. Therefore, in step 45, the PU 10 stores the don't care notification for the PUlOb on the input side in the queuing memory 14, and transmits it in step 44. If the don't care notification can be sent to the processing unit on the input side that is the source of the input signal that has become don't care, the PU 10 sends an acknowledge signal in step 38. To do.

 [0066] In step 39, the PU 10 determines whether or not the output signal Yd is determined. If none of the unreceived input signals are don't care according to the received input signal, the output signal Yd is not determined until the unreceived input signal is received. Therefore, in step 46, the PU 10 stores the input state in the memory 14 and waits for the next signal. Note that there is logic that does not determine the output signal Yd even if one of the input signals that have not been received becomes don't care. For example, a selector. Even in this case, the PU 10 stores the input state in the memory 14 and waits for the next signal.

 [0067] If the output signal Yd is determined, the PU 10 checks in step 40 whether or not the output signal Yd can be transmitted. If it can be output, in step 41, the PU 10 transmits the output signal Yd. As described above, in a state where the output signal Yd is continuously determined by continuously receiving the input signal Ad, it may be determined in step 40 that the second output signal Yd cannot be transmitted. There is sex. In this case, in step 47, the PU 10 stores the output signal Yd that cannot be transmitted in the queuing memory 14, and transmits it in step 44.

 [0068] In step 41, the output signal is transmitted only to the processing unit on the output side that is not notified of the don't care notification. That is, the output signal is not transmitted to the processing unit on the output side that is notified of the don't care notification. At the same time, in step 54 described later, the don't care notification from the processing unit on the other output side stored in the queuing memory is canceled. This function is a function that can be omitted in the one-output type, one fan-out PU10 and the system using it. On the other hand, this function is necessary for multi-output and multi-fanout PUs and systems that include them. For example, after receiving a don't care notification from the PU on one output side and returning a don't care acknowledgment response, if the input signal Ad comes and the output signal is determined, only the PU on the other output side will receive the normal output. A signal is transmitted.

[0069] At the same time as PU10 outputs the normal output signal Yd, PUlOy on the output side may output the acknowledge signal Yk for the notification that the output Y value is “don't care” t \! In that case, as with the input signal, the handshake types will be mistaken for each other. Shi There is no hindrance to the operation of the system. Therefore, it is not necessary to take any measures to prevent this misunderstanding! /.

 [0070] As described above, if the received signal is acknowledge signal Yk in step 34, it is a don't care notification (determination of the second factor). Therefore, in step 52, PU10 outputs dummy dummy output signal Yd. At the same time, in step 57, PU10 transmits acknowledge signals Ak and Z or Bk which are don't care notifications to PUlOa and Z or 10b of the source of the unreceived input signal. By receiving the don't care notification and transferring it upstream (input side), the don't care notification can be propagated upstream or back.

 [0071] In the process of backflowing the don't care notification, the don't care notification Yk may continuously arrive. In step 55 shown in FIG. 6, the PU 10 determines whether or not it is possible to transmit the don't care notification for each processing unit on the input side that flows back the don't care notification. If the handshake for the preceding don't care notification is not completed, in step 56, the PU 10 stores the don't care notification in the queuing memory 14. In that case, in step 57, the don't care notification is sent only to the processing unit that has completed the handshake for the preceding don't care notification.

 [0072] Steps 53 and 54 shown in FIG. 6 are functions that can be omitted in PU10 of one output type and one fanout. In a multi-output or multi-fanout processing unit, the input signal becomes don't care typically when all the output signals become don't care. Therefore, if PU10 is a multi-output processing unit, in step 53, it is determined whether or not a don't care notification can be transmitted to the upstream. When the don't care notification is not notified from all the output side processing units, the don't care notification from the output side is stored in the queuing memory 14 in step 54, and the next signal is awaited.

If the logic of the logic unit 12 is 2-input AND and the input signal Ad is “0 (false)”, the other input signal Bd is don't care. If the logic of the logic unit 12 is 2-input OR and the input signal Ad power S “l (true)”, the other input signal Bd becomes don't care. In these cases, the other input signal becomes don't care and the output signal Yd is determined. Therefore, As a 2-input PU10, the determination of the occurrence of don't care and the determination of the determination of the output signal can be performed in one step.

 [0074] Of these internal operations of the PU 10, the handshake function 17 controls the handshake. In steps 36 to 38, the first judgment function 18 performs control for generating a don't care notification. Further, the second judgment function 19 performs the control for returning the don't care notification in steps 52 to 57.

 [0075] By combining a plurality of 2-input 1-output PUs 10, a processing unit that realizes multi-input logic can be configured. Alternatively, it is possible to prepare a multi-input processing unit. For example, it is possible to configure a processing unit in which the logic of the logic unit 12 is a 2 tol selector and three signals including a selector control signal are input as input signals. In this case, if the selector control signal selects the input signal Ad, the input signal Bd becomes don't care. However, the output signal Yd is not determined until the input signal Ad is received. Therefore, it is desirable to have step 39.

 [0076] If the logic of the logic unit 12 is 2-input XOR, the output signal Yd is not determined unless both input signals Ad and Bd are determined. Therefore, one input signal does not make the other input signal don't care. For this reason, it is possible to omit the processing of steps 36 to 38 by the first determination function 18 in the internal operation of the PU 10, and for don't care notification, the main processing is to reverse the flow after step 52.

 [0077] When the logic unit 12 is NOT, only one input of the PU 10 is used because it is one input.

 For this reason, the flow of internal processing is further simplified. That is, steps 36 to 38 can be omitted from the internal operation of PU10. For don't care notification, only the process of backflow after step 52 is performed. If the NOT gate is implemented as a self-synchronous device, it is not necessary to adopt PU10 and create a circuit that executes this flowchart gracefully.

FIG. 7 is a different example in which a NOT gate is implemented as a self-synchronous element. As shown in this figure, as the NOT gate, an element 61 including a voltage inverter 62 that converts a positive pulse into a negative pulse and a negative pulse into a positive pulse may be mounted. However, if time is required for the voltage reversal process, the flowchart in Fig. This is advantageous to the overall system performance because the Ak acknowledge pulse can be returned earlier.

 [0079] Signal branching (multi-fanout) in a self-synchronous system is different from a normal synchronous circuit. In the case of a synchronous circuit, as shown in Fig. 8 (a), the signal can be branched by simply connecting the lines. In a self-synchronous device, as shown in Fig. 8 (b), the logical signal is physically a pair of a data line and an acknowledge line, and the logical signal is branched by simply connecting the lines. It is not possible. One method is to add the functions of steps 53 to 54 to the PU10 of the signal source to support multi-fanout. Another method is to connect a processing unit 63 for signal branching. The branch processing unit 63 has a logic part 63c. The internal operation of the logic unit 63c includes the processing described in Step 52 and later, particularly for multiple outputs in the flowchart shown in FIG. 6, and determines the occurrence of don't care based on the input signal from Step 36 to Step 39. It does not include processing.

 [0080] A buffer circuit with one input and one output (one fan-out) has no logical function. However, in actual implementation, the buffer circuit is used to assist the signal transmission of the synchronous circuit and the long distance signal transmission. In the self-synchronous system 1, such a buffer is used to assist long-range signal transmission. It is also possible to assign PU10 with 2 inputs and 1 output for a 1 input 1 output nota. Alternatively, as shown in FIG. 9, a processing unit 64 dedicated to the nota circuit can be mounted. The processing unit 64 for a buffer with 1 input and 1 output (1 fanout) has a logic part 64c. The operation of the logic unit 64c does not include the process of determining the occurrence of don't care based on the input signal of step 39 in the flowchart shown in FIG. 6, and the process of backflowing the don't care notification after step 52 (multi-fanout). Does not include processing for! /,).

 The processing unit 64 for the noffer returns the acknowledge signal Ak when the input signal Ad arrives, and returns the don't care acknowledgment response (output signal) Yd when the don't care notification (the anode signal) Yk arrives. As a result, the handshake turnaround time can be reduced and the system can operate at high speed compared to a long distance knockshake without a noffer.

[0082] The control method of the self-synchronous processing unit shown in FIG. For example, it can be applied to multi-input AND gates, N AND gates, and AND-OR composite gates. Therefore, the PU 10 can provide a self-synchronous service even when the logic of the logic unit 2 is changed to flexible by the reconfiguration function 16. Furthermore, the PU 10 can change the connection of the processing units on the input side and the output side via the input interface 11 and the output interface 13, and the routing matrix 5 can be reconfigured as the system 1. As a result, the asynchronous system 1 can flexibly implement various circuits or data paths, and can execute various applications by dynamically reconfiguring the data paths.

[0083] An example of the system 1 including a large number of PUs 10 can implement a multi-stage combinational logic circuit by changing the logic of the PUs 10. In this system, when the logic circuit is evaluated, the output stage force is also applied to the input stage as well as the “data-> acknowledge” handshake from the input stage to the output stage. The handshake can be reversed, such as “→ OK response”. For this reason, it is possible to reduce the problem of the handshake overhead that was a weak point of the conventional self-timed design and implementation method.

[0084] This design approach provides the device manufacturer with the assurance that "pulses will not disappear or multiply during transmission". "Two pulses will not be interchanged or merged during transmission." It also demands the guarantee. This is because, after a processing unit issues a data error of a dummy output signal Yd for don't care acknowledgment response for a certain clock cycle, and before the signal Yd reaches the PUlOy on the output side, PU10 is in the next clock cycle. This is because there is a possibility of outputting a data pulse of the normal output signal Yd for use. In this situation, two pulses exist on the data line that transmits the output signal Yd at the same time, and if these pulses are interchanged or merged during transmission, the PUlOy on the receiving side will malfunction. Therefore, in order to prevent malfunctions, it is necessary to ensure that the rules do not switch or merge during transmission. However, the requirement to “guarantee that pulses will not be interchanged or merged during transmission” is extremely reasonable and is not a particular burden on device manufacturers. In this system 1, the overhead due to handshake backflow can be obtained simply by designing the circuit in consideration of such restrictions. Reduction can be achieved.

 Further, in the system 1 using the PU 10 described above, the data line is described as a dual power source specification of a positive power source and a negative power source so that one data line can be configured. Even in a system using the 2-wire self-synchronous device shown in Fig. 3, that is, a processing unit with a specification of two single-power-supply data lines, the self-timed It is possible to construct “elements”. However, in that case, the device manufacturer is requested to guarantee the above, and in addition, the guarantee that "pulses sent one after the other in a set of two data lines will reach the receiving element in the same order". Also require.

 [0086] For example, consider a case where the output signal Yd is transmitted through a single power supply data line consisting of two signal lines YO and Y1. After sending the pulse signal YO as a dummy output signal for the don't care acknowledgment response for a certain clock cycle on the sending side, before sending it to the receiving side element, the sending side element is used for the next clock cycle. The normal pulse signal Y1 may be output. There is a possibility that the data line transmitting pulse signal Y1 is extremely shorter than the data line transmitting pulse signal YO, and the later pulse signal Y1 may reach the receiving element first. In that case, the receiving element regards the pulse signal Y1 as a dummy output signal for the don't care acknowledgment response, and regards the subsequent pulse signal YO as a regular data pulse for the next clock cycle. For this reason, the system malfunctions. To prevent such malfunctions, carefully align the wiring length and load capacity of the data line that transmits the signal YO and the data line that transmits the signal Y1 so that the subsequent pulse does not arrive first. It needs to be manufactured.

 [0087] As in this example, if the data line has the two power supply specification, the output signal Yd is transmitted by one line.

 This can alleviate the demands on device manufacturers that do not have the above design or manufacturing problems. Depending on the type of device or the manufacturer, the dual power supply specification is more burdensome than manufacturing with carefully aligned data line lengths and load capacities! / ヽ In the case of a single power supply data line 2 If this one set method is adopted.

[0088] Furthermore, in the system 1 employing the above-described PU10, pulses (pulse signals) are used to exchange signals through data lines and acknowledge lines. On the other hand, the well-known four-phase noise shake and two-phase (transition signaling) handshake It is possible to construct a “self-timed device for mounting a synchronous circuit with a handshake backflow function” by using it as a handshake of a source. However, the four-phase noise shake is not preferable in terms of performance because the handshake turnaround time is longer than the two-phase noise shake and the pulse method. On the other hand, the two-phase noise shake requires a slightly forcible timing guarantee and timing adjustment when trying to achieve it with a dual power supply (one data line) specification. Therefore, in order to explain the self-timed device with handshake backflow function easily and without failure with the minimum timing constraints, the above-mentioned pulsed handshake method with two power supplies is suitable.

 Furthermore, in the PU 10, the processing based on each received signal is advanced as much as possible.

 One method is to store the fact as an event token when a signal is received continuously, as shown in steps 33, 48, and 49 in Figure 6, but send an acknowledgment acknowledge signal. That's it.

 [0090] For example, the output signal Yd is determined by the input signal Ad from the PUlOa on the input side, the acknowledge signal Bk for notifying don't care is transmitted to the PUlOb on the input side, and the output signal Yd to the PU1 Oy on the output side When PU10 is transmitted, the PU 10 waits for an acknowledge response output signal Bd or the analog signal Yk. At this time, when the input signal Ad is further received from the PUlOa on the input side, the fact that the input signal Ad has arrived is stored in the memory 14 as an event token. Next, the PU10 force desired input signal Bd and acknowledge signal Yk are received, and the handshake in step 32 is completed. At this time, since the event token of the next input signal Ad already exists, the PU 10 immediately proceeds to step 34. At the same time, erase the token. This event token can have a maximum of one for each of the signals Ad, Bd and Yk. This is because an unprocessed signal will not be received repeatedly unless an acknowledgment signal for receiving data or a response to acknowledge don't care is returned.

[0091] In the PU 10, a queuing memory 14 is provided as a second measure for proceeding with processing based on each received signal. As long as the queuing memory 14 can be used, the PU 10 transmits an acknowledgment response to the received signal. That is, in step 33, for example, the received acknowledge signal Ak with respect to the input signal Ad is not returned. Since the input Ad cannot come again because it is not returned, it waits for another signal such as the acknowledge signal Yk. On the other hand, PUlOa that sent the input signal Ad is waiting for the receipt acknowledge signal Ak. Therefore, by returning the acknowledge signal Ak without waiting for the receipt of the acknowledge signal Yk, the processing on the sending side PUlOa can be advanced. On the other hand, the signal to be output by the received input signal Ad is stored in the queuing memory 14 in step 45 or 47, and waits for transmission.

 Further, a case is considered where the acknowledgment signal Yk for don't care notification is received continuously. Specifically, the output signal Yd is sent as a don't care acknowledgment response to the first acknowledge signal Yk, and the input don't care acknowledgment response to the second don't care notification acknowledge signal Yk. Wait. On the other hand, the PU 10 y on the output side can be processed by transmitting the output signal Yd as the don't care acknowledgment response to the second acknowledge signal Yk. However, in steps 55 and 56, an acknowledgment response is obtained for the preceding don't care notification, and the don't care notification for the processing unit is stored in the queuing memory 14 and awaits transmission.

 FIGS. 10 to 13 show timings at which an input signal and an output signal are transmitted and received in PU64 of the buffer circuit shown in FIG. FIG. 10 is a time chart in which the operation of the PU 64 receiving the input signal Ad four times and transmitting it as the output signal Yd each time is repeated four times.

In FIG. 11, the PU 64 processes the first data at the same straightforward timing as in FIG. When the PU64 processes the second data, it receives the third input signal Ad before the second acknowledge signal Yk. In this case, the acknowledge signal is not sent in advance. Therefore, in step 49, PU64 queues as an event and waits for the second acknowledge signal Yk pulse. When receiving the second acknowledge signal Yk, in step 32, the PU 64 moves to step 35 and step 39 from step 48 as soon as it is received, and the third acknowledge signal Ak and the third output signal Y d are received. Send. The operation for the next third acknowledge signal Yk is the same. Since the fourth acknowledge signal Yk was received following the output signal Yd, the PU64 does not queue as an event and processes it at a straightforward timing. In FIG. 12, PU 64 processes the first data at the same straightforward timing as in FIG. When the PU64 processes the second data, it receives the third input signal Ad before the second acknowledge signal Yk. In this case, there are two levels of queuing, and PU64 sends an acknowledge signal to the second signal received in the middle of the processing related to the first signal, and the third signal is It is set to queue as an event. For this reason, the PU 64 waits for step 47, and then proceeds to step 44 from step 32 where the second acknowledge signal Yk is received, and transmits the third output signal Yd. Next, since the PU 64 receives the fourth input signal Ad in the same manner as described above before receiving the third acknowledge signal Yk, the PU 64 operates in the same manner as described above. The PU 64 receives the fifth input signal Ad before receiving the fourth acknowledge signal Yk, and then receives the sixth input signal Ad. For this reason, the PU 64 transmits the fifth acknowledge signal Ak to the fifth input signal Ad and waits for step 47. P U64 does not transmit the acknowledge signal Ak for the sixth input signal Ad, and waits for step 49. Thereafter, when the PU 64 receives the fourth acknowledge signal Yk, it sends the fifth output signal Yd in step 44. At the same time, the PU 64 proceeds from step 48 to step 35, and transmits an acknowledge signal Ak for the sixth input signal.

 [0096] After that, the PU 64 received the seventh input signal Ad before the fifth acknowledge signal Yk. Therefore, the PU 64 waits for step 49, waits for the fifth acknowledge signal Yk, transmits the sixth output signal Yd and the seventh acknowledge signal Ak, and the seventh output signal Yd 47 waits. Next, the PU 64 waits for the sixth acknowledge signal Y k, transmits the seventh output signal Yd in step 44, and receives the seventh acknowledge signal Y k. As described above, even if the PU64 immediately receives the third input signal Ad after returning the second acknowledge signal Ak, the PU64 can perform processing without breaking the logic. This event token queuing process is a self-synchronous circuit design method! Refers to a technology called slack.

FIG. 13 is a diagram showing a state in which the don't care notification is reversed. In FIG. 13, the output side PUlOy operates in advance under the same queuing conditions as in FIG. Therefore, Figure 13 and FIG. 12 is the same as above except that step 35 in FIG. 12 is changed to step 52 and step 47 is changed to step 56.

 [0098] Processing of event tokens is important. This is because the processing for outputting the acknowledge signal Ak and the output signal Yd also takes a predetermined time although it is minute, and the input signal Ad and the acknowledge signal Yk may be received during the minute period. At that time, these signals should be stored in memory 14 as event tokens and processed immediately in the next step. Also, when the input signal Ad and acknowledge signal Yk are received simultaneously, only one of them can be received and the other cannot be ignored. Therefore, one signal that cannot be processed immediately is treated as an event token. In this case, regardless of which is received first, the same result can be obtained by immediately processing the next step based on the remaining event token. You need to support at least one event token per input. However, by returning an acknowledge signal and queuing two or more, it can handle slack and provide a higher-performance PU10 and system 1.

 [0099] The above is a self-synchronous processing unit for implementing combinational logic. Therefore, by providing a self-synchronous element for implementing a flip-flop, a synchronous user circuit can be implemented in a self-synchronous system. The flip-flop is a 1-input 1-output processing unit similar to the noffer circuit, and starts by transmitting the output signal Yd with an initial value of 0, and the handshake of the output signal Yd → acknowledge signal Yk and the input signal Ad → Acknowledge signal Perform Ak handshake once. As a result, the flip-flop operation corresponding to one clock cycle of the synchronous user circuit that outputs the latched input signal by the acknowledge signal Yk can be realized.

FIG. 14 is a flowchart of the basic internal operation of the flip-flop (FF). Figure 15 is a flowchart of the internal operation of the flip-flop (FF) corresponding to the backflow handshake. First, as described above, in step 71, the FF starts from transmitting the output signal Yd with an initial value of 0 as described above. In step 72, the FF waits for the input signal Ad or the output acknowledge signal Yk. . In step 73, when the FF receives the input signal Ad prior to the output acknowledge signal Yk, in step 74, the FF transmits the input acknowledge signal Ak. In step 75, FF waits for output acknowledge signal Yk and In 76, output signal Yd is transmitted. On the other hand, if the output acknowledge signal Yk is received before the input signal Ad, the FF waits for the input signal Ad in step 77. In step 78, the FF transmits the output signal Yd and the input acknowledge signal Ak.

[0101] The input signals Ad and Ak are handled in the same way as the type 1 handshake handled in the basic flow in Fig. 6. The handling of the output signals Yd and Yk is the same as the type 3 handshake in the basic flow in Fig. 6 when viewed from the outside. The operation is to output the data Yd for a certain cycle and the force receives the corresponding Yk. It is. However, in Fig. 14, the new power is “The transmission permission signal (transmission request signal in other words) indicating that the preparation for the next cycle data is ready” is received, and the response for that is for the next cycle. The data signal Yd is output. ”T is treated as if it were a new type of handshake. This is always the same as the flow shown in Figure 6. Therefore, it is possible to incorporate the flip-flop function in PU10 that realizes the flow of FIG. In addition, it is possible to construct system 1 including PU10 having a flip-flop function.

 [0102] In the basic flow of FIG. 14, the input value A received as the input signal Ad is output as the output signal Yd for the next clock site. Therefore, in the basic flow of Fig. 14, which is considered only within the range of one clock cycle, the backflow of the don't care notification due to the handshake that does not handle the input signal A! However, in step 77, if the acknowledge signal Yk, which is a don't care notification pulse for the next clock cycle, is received while waiting for the input signal Ad of one clock cycle, the output signal of the next clock cycle is received. Yd means don't care, and the input signal Ad in the current clock cycle also means don't care.

[0103] FIG. 15 is a flowchart showing an internal operation for reversing the handshake in that case. In step 81, when the acknowledgment signal Yk is received instead of the input signal Ad, the FF makes a decision in step 82, and in step 83, transmits a dummy output signal Yd of a don't care acknowledgment response and an acknowledge signal Ak of a don't care notification. In step 84, a dummy input signal Ad is received. As a result, it is possible to Realize reverse notification. This internal operation is the same as the operation of returning the don't care notification after step 52 of PU10 shown in FIG. 6, and the internal operation shown in FIG. 15 can also be realized by PU10.

 [0104] Even in the self-synchronous flip-flop, the input signal Ad or the acknowledgment signal Yk that advances the processing sequentially is waited for at the desired timing and the desired signal Yk or the input signal Ad is received. Sometimes. These can be stored as event tokens in PU10. Further, it can be stored in the queuing memory 14 corresponding to slack. A flip-flop is a buffer with a delay, as is called a dead delay in the field of signal processing. For this reason, by introducing a self-synchronous flip-flop, the delay tolerance of the self-synchronous system can be enhanced.

 FIG. 16 is a combinational logic circuit that implements the following logical expression (1). Fig. 17 shows the circuit shown in Fig. 16 converted to a circuit that can be implemented in System 1 with multiple PU10s, which is constructed with a 2-input AND gate, 2-input OR gate, and NOT gate. . For signal branching, a dedicated signal branching processing unit 63 is used and is also clearly shown in the circuit diagram. The logic circuit shown in Fig. 16 can also be implemented with self-synchronous circuit elements such as multi-input gates and composite gates.

 Z =! X1 & X2 & X3 + X1 &! X2 + X1 &! X3 (1)

 18 (a) to (h), as a comparative example, in the circuit shown in FIG. 17, the progress of handshaking when executing in a self-synchronous manner without using the function of flowing back don't care notifications. It shows the condition. One of the wirings in the circuit shown is a set of a data line and an acknowledge line, and the handshake is completed when the data pulse (input signal and output signal) and the acknowledge pulse come and go. In the following, it is assumed that all wiring and processing in individual processing units have the same delay.

 [0107] As shown in Fig. 18, when there is no backflow function of don't care notification by handshake, each processing unit performs output handshake by determining the output value after the handshake of all inputs is completed. . In this figure and below, the wiring after the handshake is completed

When the value S is “l”, it is indicated by a thick solid line, and when the value is “0”, it is indicated by a thick dashed line. Fig. 18 (a) Odor If (1, 0, 1) data pulses are generated at the inputs (XI, X2, X3) and the handshake is completed, the unit time from Figure 18 (b) to Figure 18 (h) Each time, the handshake between the processing units is digested one step at a time, and “1” is output as output Z after 7 unit hours.

 FIGS. 19 (a) to 19 (e) show the progress of handshaking when the backflow function of don't care notification by handshaking is used. The wiring where the backflow handshake (don't care notification & understanding) occurred is shown by a thick broken line. Up to Figure 19 (b), the operation is the same as in Figure 18. In Fig. 19 (c), PUlOc generates a don't care notification using the handshake backflow function! Since PUlOc is a 2-input AND and its lower input CB is found to be “0”, the output signal CYd is determined to be “0”. Therefore, in this cycle, the output signal CYd is output, and the unreceived input CA is treated as a don't care and the handshake is reversed.

 In FIG. 19 (d), the PUlOc input side, that is, the upstream PUlOd receives the output don't care notification and treats the unreceived input DA as don't care. Therefore, don't care notification acknowledge signal DAk is output. At this time, the PUlOe on the input side was about to output a normal data pulse to the output EY, so the don't care notification acknowledge signal and the normal output signal are misplaced. In other words, PUlOd regards the legitimate output signal as a don't care acknowledge response, and PUlOe regards the don't care notification as a data reception acknowledge signal.

 [0110] In Fig. 19 (e), the output F Y is determined by the upper input FA in the PUlOf of the last two-input OR. Therefore, a don't care notification is sent to the PUlOg on the input side of the lower input FB to reverse the handshake. In this case as well, PUlOg tries to transmit the output signal, so it is mistaken for the don't care notification acknowledge signal and the regular data pulse, and the handshake is completed in both PUlOf and 10g.

[0111] As can be seen from these figures, it takes 8 unit hours to execute the circuit of Fig. 17 without the handshake backflow function as shown in Fig. 18. On the other hand, if there is a handshake backflow function, as shown in FIG. 19, the execution of the circuit of FIG. Handshake Whether backflow occurs or not depends on the value of the signal. Therefore, with the handshake backflow function, the circuit in Fig. 17 cannot always be executed in 5 unit hours. For example, if the input (Xl, X2, X3) is (1, 1, 0), even if there is a handshake backflow function It takes 8 unit hours. However, in the self-synchronous system, unlike the concept of synchronous circuit design, “whether the handshake backflow function is used or not, it is necessary to secure a clock period equivalent to 8 unit hours, so handshake backflow It is not judged that the function is effective. There is no global clock in a self-synchronous system. For this reason, there is no fixed clock cycle, and as soon as handshaking is completed according to the situation at that time, it can be considered that the processing equivalent to one cycle of the user clock has been completed and can proceed to the next. Therefore, in the self-synchronous circuit 17, if there is a handshake backflow function, when the input (Xl, X2, X3) is (1, 0, 1), processing for one user clock in 5 unit times The system performance can be improved according to the appearance frequency of the case.

 [0112] Figure 20 (a) to Figure 22 (d) (Figure 20 (a) to (e), Figure 21 (a) to (d), Figure 22 (a) to (d)) are shown in Figure 19 The situation in which handshaking proceeds in the self-synchronous circuit shown is shown in more detail. In these figures, the triangles pointing to the right are data line pulses, that is, input signals and output signals (hereinafter, input data pulses and output data pulses). The black mark is a regular pulse representing logic “1”, and the hatched mark is a regular pulse representing logic “0”. The white mark is a dummy pulse for don't care acknowledgment response. The triangles pointing to the left are pulses of an acknowledge line, that is, an acknowledge signal (hereinafter, an input acknowledge pulse and an output acknowledge pulse). Black marks are data reception response pulses of logic “1”, and hatched marks are data reception response pulses of logic “0”. The white mark is a don't care notification pulse.

 [0113] In these figures, it takes one unit time for the pulse to leave the sending processing unit and reach the force receiving processing unit, and one unit for the processing unit to receive the pulse and cause an action. It is assumed that it takes time. Furthermore, the processing unit assumes that all pulses can be acted on in one unit time when multiple pulses are received simultaneously. Regarding the handshake backflow function, each processing unit assumes that don't care processing is given priority when it simultaneously receives the data panorama of the input signal and the acknowledge signal from the output side of the don't care notification.

Based on these assumptions, FIG. 20 (a) to FIG. 22 (d) will be described. Figure 20 (a) to Figure 22 (d) State transitions per unit time are shown. First, at time tl in FIG. 20 (a), a data pulse of (1, 0, 1) is generated at inputs (Xl, X2, X3). At time t2 in Fig. 20 (b), these pulses arrive at the signal branch processing unit. At time t3 in Figure 20 (c), the signal branch processing unit takes action, generating an input acknowledge pulse and an output data pulse. At time t4 in Fig. 20 (d), the input acknowledge pulse of the signal branch processing unit arrives at the source of the input signal. At the same time, the output data pulse of the signal branch processing unit arrives at the receiving processing unit. At time t5 in Fig. 20 (e), PUlOc generates a don't care notification pulse and reverses it.

 [0115] At time t6 in Fig. 21 (a), a don't care notification pulse arrives at PUlOd, and at time t7 in Fig. 21 (b), PUlOd further reverses the don't care notification pulse. At time t8 in Fig. 21 (c), a handshake is established between the normal output data pulse and the don't care notification pulse between PUlOd and 10e, and the back flow of the don't care notification stops. At time t9 in Fig. 21 (d), PUlOf at the final stage outputs an output data pulse and also generates a don't care notification pulse and reverses it.

 [0116] At time 1; 10 in Fig. 22 (&), a handshake is established between the normal output data pulse and the don't care notification pulse between PUlOf and 10g. At time tl2 in Fig. 22 (c), the handshake between the final stage PUlOf and the receiving side of the output signal is completed, and the output signal of this circuit is determined at time tl3 in Fig. 22 (d). In the above, it is assumed that all wiring delays are the same, but the circuit is executed correctly even if the wiring delay is different for each wiring, and the circuit is executed correctly even if the delay of the same wiring varies depending on the situation. In addition, although the values of the inputs (X1, X2, X3) are fixed for the sake of explanation, a new calculation can be started by inputting a new value after time t5 when the input handshake ends. .

FIG. 23 shows an example of a sequential circuit with a flip-flop. Specifically, Figure 23 shows a 3-bit counter described in a normal synchronous design description. The circuit of FIG. 24 is obtained by converting the counter of FIG. 23 into a configuration including a two-input logic element, a NOT gate element, a signal branching element, and a flip-flop FF. Therefore, the circuit of FIG. 24 can be implemented in system 1 including a 2-input / 1-output self-synchronous PU10. In the circuit diagram of FIG. 24, one wiring represents a pair of a data line and an acknowledge line as described above. The

 [0118] Fig. 25 (a) to Fig. 31 (d) (Fig. 25 (a) to (d), Fig. 26 (a) to (d), Fig. 27 (a) to (d), 028 (a) to (d), Fig. 29 (a) to (d), Fig. 30 (a) to (d), Fig. 31 (a) to (d)), the circuit shown in Fig. 24 is self-synchronized and handshaked. The state executed using the backflow function is shown. Figures 25 (a) to 31 (d) show the state transitions per unit time. Note that the counter circuit is executed repeatedly rather than once. Therefore, the operation of the circuit is indicated by the data pulse, the analog pulse, and the don't care notification pulse. Also, the square representing the flip-flop shows the cycle value of the user clock! /, Indicating the cycle of the user clock! /.

 [0119] At time T1 shown in Fig. 25 (a), the initial value 0 is also output for the three flip-flop forces. They arrive at the processing unit that receives the output signal at time T4 shown in Fig. 25 (d). At time T8 shown in Fig. 26 (d), a pulse arrives at the data input of the flip-flop (counter LSB) of output Z1. At time T9 shown in Fig. 27 (a), only the flip-flop of output Z1 proceeds to the process of user clock cycle 1.

 [0120] At time T11 shown in FIG. 27 (c), the flip-flop of output Z2 is updated to the process of user clock cycle 1. At time T15 shown in Figure 28 (c), the output Z3 flip-flop (counter MSB) is updated to the process of user clock cycle 1. Meanwhile, processing of user clock cycle 1 proceeds in the NOT gate processing unit around the output Z1 flip-flop. Therefore, at time T17 shown in FIG. 29 (a), the flip-flop of the output Z1 proceeds to the processing of the user clock cycle 2.

[0121] At time T19 shown in FIG. 29 (c), the flip-flop of the output Z2 proceeds to the processing of the user clock cycle 2. The processing delay of the output Z2 flip-flop is small compared to the processing of the output Z1 flip-flop. The processing delay of the output Z3 flip-flop is large. Therefore, at time T25 shown in FIG. 31 (a), the flip-flop of the output Z1 proceeds to the processing of the user clock cycle 3 in advance. On the other hand, at time T27 shown in FIG. 31 (c), the flip-flop of the output Z3 finally proceeds to the processing of user clock cycle 2. At time T27, the output Z2 flip-flop proceeds to user clock cycle 3 processing. Therefore, the output Z3 flip-flop is compared to the output Z2 flip-flop. 1 lag (1 or more lags for the output Zl flip-flop).

[0122] In this way, in the 3-bit counter circuit implemented in the asynchronous system 1, the output Z1 flip-flop and the output Z2 flip-flop are processed ahead of the output Z3 flip-flop. Advances. However, the difference does not grow indefinitely. When the difference in processing between these flip-flops spreads to a certain extent, the signal branch processing unit (PUlOh in Figure 24) that connects the circuits associated with the output Z1 and Z2 flip-flops to the output Z3 flip-flop. And 10i) will not return an acknowledge pulse. For this reason, the flip-flop related circuits of outputs Z1 and Z2 cannot proceed any further. Therefore, after that, every time the flip-flop of output Z3 advances by one cycle, it returns the acknowledge pulse by PUlOh and 10i force Si times of the signal branch, and the flip-flop of outputs Z1 and Z2 is also 1 cycle accordingly Proceed with each minute. By storing two or more event tokens in memory 14, which queues the processing unit's event tokens, it is possible to increase the limit at which the output Z1 and Z2 flip-flops can proceed ahead.

 [0123] In the operation of the self-synchronous system shown in Figs. 25 (a) to 31 (d), at time T7 shown in Fig. 26 (c), time T9 shown in Fig. 27 (a), etc. It can be seen that a don't care notification norse occurs and the handshake backflow function is effectively utilized. In particular, at time T19 in Fig. 29 (c), a don't care notification pulse that generates a 2-input AND PUlOj occurs at time T21 in Fig. 30 (a)! /, A 2-input AND PU 1 Ok input don't care notification. Propagating as a pulse. From these figures, it can be seen that the handshake processing power for executing the multistage logic is output to the input stage. This handshake backflow function shortens the execution time of the entire multi-stage logic and improves system performance.

[0124] In the operation of the counter circuit shown in Fig. 25 (a) to Fig. 31 (d), the three flip-flops operate at different timings because of the complexity of the logic that calculates the next value of each flip-flop. The main reason is that there was a difference between the two. There is a reason that the processing unit on the receiving side is not shaking the output signals of each flip-flop at different timings. The processing unit that receives the output signal may be configured to “do not return acknowledge until all three signals are ready”. That With such a configuration, the signal branch processing unit immediately after the three flip-flops does not operate at different timings, and the processing of the three flip-flops does not proceed at different timings as described above.

 The input signal for the self-synchronous system can be considered similarly. In the counter circuit examples shown in FIGS. 23 and 24, there is no “input signal for the entire system”. When there are input signals for the entire system, if the input signals are synchronized and handshaked, the flip-flops in the system do not operate at different timings indefinitely. Will fit in some degree. If the handshake of the input / output signal of system 1 is stopped by using such an operation, the internal output of system 1 will be to some extent, that is, the output that is not dependent on the input signal that has stopped coming, or the output that can no longer be output. Stall after proceeding until the signal stops processing. If the handshake of input / output signals of system 1 is then resumed, system 1 continues and force processing resumes.

 [0126] In this way, in the synchronous circuit, the processing equivalent to stopping and restarting the global clock is part of the system 1 or system 1 in the self-synchronous system 1 in which no global clock exists. This can be achieved by stopping or resuming handshaking of input / output signals of a circuit configured in a general manner. Therefore, in the self-synchronous system 1, the data flow implemented in the system 1 can be changed by temporarily stopping the data flow processing and changing the logic of the processing unit or changing the connection of the processing unit. Rows can be dynamically reconfigured.

 [0127] In this system 1, the data lines and acknowledge lines that make up the routing matrix 5 to which the PU 10 is connected transmit pulses only once during the process corresponding to one cycle of the original synchronous circuit. . Therefore, when the original synchronous circuit is normally mounted in a synchronous manner, or when the self-synchronous circuit is mounted in a two-wire self-synchronous design method, a large amount of spikes are caused by imbalance of element delay and wiring delay. It is possible to suppress the generation of power and power consumption.

As described above, according to one embodiment of the present invention, circuit elements such as AND gates, OR gates, NOT gates, and flip-flops used in the synchronous design are not self-timed. It is implemented by the method. For each signal of the synchronous user circuit, the self-timed device allocates two signals, the data line and the acknowledge line, and the data line uses two power sources, a positive power source and a negative power source. On the data line, one positive pulse represents a logic “1” for one clock cycle, and one negative pulse represents a logic “0” for one clock cycle. In the acknowledge line, one pulse represents an acknowledge for one clock cycle.

 [0129] A two-wire self-timed device using one power supply transmits an output signal only when the output value must be changed. The one-wire self-timed device according to one embodiment of the present invention transmits an output signal once per process for one cycle of the user clock regardless of whether the output value is changed. This reflects the nature of the synchronous user circuit that “all signal lines transmit values once per clock cycle”. Therefore, in the circuit system constructed by combining the self-timed elements of one form of the present invention, every time a handshake is performed once on all data lines / acknowledge lines, one cycle of the user clock of the synchronous user circuit It can be considered that the processing of minutes proceeds.

[0130] Further, in the handshake, usually, the signal transmitting side element first issues a data pulse to the signal receiving side element, and the receiving side element that receives the data pulse sends an acknowledge pulse to the transmitting side element. Take the procedure of returning. However, if the receiving element is a multi-input element, the value of the signal of interest may be don't care depending on the value of other input signals. In that case, the receiving element first issues an acknowledge pulse (meaning don't care notification) to the sending element, and the sending element that receives it sends an arbitrary data pulse (meaning don't care acknowledgment). Is returned as a handshake.

[0131] When an input signal causes a don't care to be sent to another input when another input becomes don't care due to an input, the input signal is received before the input signal is received. Also sends a don't care notification pulse to the input signal. As a result, when executing multi-stage logic, the value is determined only one after another from the input stage to the output stage. The don't care propagates and a handshake of reverse flow (non-shake backflow function) occurs. [0132] According to one aspect of the present invention, since a clock synchronous circuit can be implemented without using a glossy clock, the number of steps for clock skew adjustment and critical path adjustment can be reduced compared to conventional clock synchronous implementation. . In addition, compared to the 2-wire self-timed design and implementation method, there is an effect that the circuit can be designed based on the concept of the synchronous design that is widely spread. Also, when evaluating a multi-stage combinational logic circuit, the input stage force is also directed to the output stage, and the handshake “Data → Acknowledge” is performed. From the output stage to the input stage, the “don't care notification → don't care” You can also reverse the handshake. For this reason, the problem of the non-shake overhead that was a weak point of the conventional self-timed design and implementation method is also reduced. In addition, each signal line within one logical clock cycle

Since transmission is performed only once, it is possible to suppress a situation in which a large amount of spikes are generated due to variations in element delays and power is consumed, as in conventional clock synchronous mounting and self-timed design mounting.

 In the above, the internal operation of the self-synchronous PU 10 is shown in the form of a flowchart, but it can also be described by other notations such as a state transition diagram and a production rule. The system 1 having a general-purpose self-synchronous PU 10 is described above. On the other hand, a self-synchronizing processing unit equipped with a dedicated logic or a self-synchronizing element can be combined to form a self-synchronizing circuit with a handshake backflow function. Furthermore, the self-synchronous processing unit or element does not have to be connected by wiring, and there is an electrical signal! /, Which can realize self-synchronous mounting by transmitting an optical signal wirelessly or by wire. . In addition, the self-synchronous system can overcome the effects of wiring delay and device delay imbalance, and is a distributed large-scale system in which multiple systems or processing units are connected by computer work such as the Internet. The above configuration can also be applied to this.

Claims

The scope of the claims

 [1] A system having a plurality of self-synchronous processing units,

 One processing unit of the plurality of processing units is

 An input-side signal exchange unit for receiving a plurality of input signals respectively supplied from a plurality of input-side processing units;

 A logic unit for generating an output signal based on the plurality of input signals; an output-side signal exchange unit for transmitting the output signal to at least one output-side processing unit;

 A first determination function for determining an unreceived input signal that is unnecessary for generating an output signal based on an input signal received by the signal exchange unit on the input side;

 A second determination function for determining an unreceived input signal that is not required to be received based on a notification that indicates that the output signal is not received, which is received by the signal exchange unit on the output side. A signal exchange unit transmits the waste notification to an input-side processing unit that supplies an unreceived input signal that is determined to be unnecessary by the first determination function or the second determination function; system.

 [2] In Claim 1, the output-side signal exchange unit transmits an output signal to a plurality of output-side processing units,

 The second determination function is a system for determining an unreceived input signal that becomes unnecessary for reception when the power for all of the plurality of output-side processing units is received.

[3] The system according to claim 1, wherein the processing unit has a handshake function for confirming signal transfer by any one of the following processes al to a4.

 al When an input signal is received, a confirmation signal is sent to the processing unit on the input side that is the source of the input signal.

 a2 The confirmation signal is transmitted as the non-use notification to the input-side processing unit that is the source of the unreceived input signal, and the dummy input signal is transmitted from the input-side processing unit to which the confirmation signal is transmitted. Receive.

a3 Send an output signal and receive the confirmation signal from the output processing unit that is the destination of the output signal. a4 If the confirmation signal is received when the output signal has not been transmitted, it is recognized as a non-use notification and a dummy output signal is transmitted.

4. The system according to claim 1, wherein the signal exchange unit on the output side transmits the output signal as a pulse signal each time the output signal is generated by the logic unit.

5. The system according to claim 1, wherein the output side signal exchange unit transmits the output signal as a signal that is displaced into three states.

6. The system according to claim 5, wherein the three states include neutrality and two states that do not include the neutrality.

 7. The system according to claim 1, wherein the processing unit further includes a memory for storing an input signal that cannot be processed by an unreceived input signal.

 8. The system according to claim 1, wherein the processing unit further includes a memory for storing the received signal as an event token that cannot be processed! /.

 9. The system according to claim 1, wherein the logic unit has a function of changing logic for generating an output signal.

 [10] In Claim 1, the signal exchange unit on the input side has a function of changing the processing unit on the input side,

 The output-side signal exchange unit has a function of changing an output-side processing unit.

 11. The communication system according to claim 1, further comprising a communication system that enables exchange of signals between the plurality of processing units, wherein the communication system can reconfigure the connection of the plurality of processing units.

 12. The system according to claim 1, further comprising an integrated circuit unit including the plurality of processing units and a routing matrix for transmitting signals between the plurality of processing units.

 [13] In Claim 12, the routing matrix reconfigures a circuit in the integrated circuit unit by changing a connection between at least some of the processing units included in the plurality of processing units. system.

[14] A self-synchronous processing unit, A signal exchange section on the input side for receiving a plurality of input signals respectively supplied from other processing units on the plurality of input sides;

 A logic unit for generating an output signal based on the plurality of input signals; an output-side signal exchange unit for transmitting the output signal to at least one other processing unit on the output side;

 A first determination function for determining an unreceived input signal that is unnecessary for generating an output signal based on an input signal received by the signal exchange unit on the input side;

 A second determination function for determining an unreceived input signal that is not required to be received by a use notification indicating that the output signal is not received, received by the signal exchange unit on the output side, and

 The signal exchange unit on the input side is addressed to the other processing unit on the input side that supplies an unreceived input signal determined to be unnecessary for reception by the first determination function or the second determination function. A processing unit that sends unused notifications.

[15] In Claim 14, the signal exchange unit on the output side transmits an output signal to other processing units on the plurality of output sides,

 The second determination function is a processing unit that determines an unreceived input signal that is not required to be received when the use notification of the uselessness is received.

16. The processing unit according to claim 14, further comprising a handshake function for confirming signal transfer by any one of the following bl to b4 processes.

 bl When an input signal is received, a confirmation signal is sent to another processing unit on the input side that is the source of the input signal.

 b2 The confirmation signal is transmitted as the non-use notification to the other processing unit on the input side of the supply source of the unreceived input signal, and a dummy signal is transmitted from the other processing unit on the input side to which the confirmation signal is transmitted. Receive the input signal.

 b3 Transmit the output signal and receive the confirmation signal from another processing unit on the output side of the output signal.

b4 When the confirmation signal is received when the output signal has not been transmitted, it is recognized as the unnecessary notification and a dummy output signal is transmitted.

17. The processing unit according to claim 14, further comprising a memory for storing an input signal that cannot be processed by an unreceived input signal.

18. The processing unit according to claim 14, further comprising a memory for storing, as an event token, a signal that cannot be processed among the received signals.

[19] A self-synchronous processing unit,

 An input-side signal exchange unit that receives an input signal from another input-side processing unit; and an output-side signal exchange unit that transmits the input signal to at least one other output-side processing unit. ,

 The signal exchange unit on the input side sends an unnecessary notification to another processing unit on the input side that supplies an unreceived input signal in response to an unnecessary notification of the output signal received by the signal exchange unit on the output side. Processing unit.

[20] A plurality of processing units comprising at least one processing unit according to claim 14,

 And a routing matrix for transmitting signals between the plurality of processing units.

21. The integrated circuit unit according to claim 20, wherein the plurality of processing units further include at least one processing unit according to claim 19.

[22] In Claim 20, the routing matrix reconfigures a circuit in the integrated circuit unit by changing a connection between at least some of the processing units included in the plurality of processing units. Integrated circuit unit.

[23] It has a plurality of processing units, and each processing unit is the processing unit according to claim 19,

 An integrated circuit unit further comprising a routing matrix for transmitting signals between the plurality of processing units.

[24] A method of controlling a system having a plurality of self-synchronous processing units, wherein one processing unit of the plurality of processing units is a plurality of input signals respectively supplied from a plurality of input-side processing units. A signal exchanging unit on the input side for receiving the signal, a logic unit for generating an output signal based on the plurality of input signals, and for transmitting the output signal to at least one processing unit on the output side And the signal exchange section on the output side of Have

 The method is

 The first factor that an unreceived input signal that is not required for generating an output signal is generated by the input signal received by the signal exchange unit on the input side, or the output received by the signal exchange unit on the output side Due to a second factor in which an unreceived input signal that is not required for reception is generated due to a notification indicating that the signal is not used, it is sent to the processing unit on the input side that is scheduled to supply the input signal. A method comprising sending a notification.

25. The method according to claim 24, further comprising transmitting the output signal as a pulse signal each time the output signal is generated by the logic unit.

26. The method of claim 24, comprising confirming signal transfer between the plurality of processing units, and confirming the signal transfer includes:

 When an input signal is received, a confirmation signal is sent to the processing unit on the input side that is the source of the input signal.

 The confirmation signal is transmitted as the non-use notification to the input-side processing unit that is the source of the unreceived input signal, and the dummy input signal is transmitted from the input-side processing unit to which the confirmation signal is transmitted. Receive,

 An output signal is transmitted, and the confirmation signal is received from an output-side processing unit to which the output signal is transmitted;

 When the confirmation signal is received when the output signal is not transmitted, it is recognized as the unnecessary notification and a dummy output signal is transmitted.

[27] A method for transmitting a signal, comprising: a self-synchronizing processing unit confirming the transfer of a signal with another self-synchronizing processing unit;

 The self-synchronous processing unit is based on an input-side signal exchange unit for receiving a plurality of input signals respectively supplied from a plurality of other input-side other processing units, and the plurality of input signals. A logic unit for generating an output signal, and an output side signal exchange unit for transmitting the output signal to at least one other processing unit on the output side,

Confirming the transfer of the signal includes: When the input signal is received by the signal exchange unit on the input side, a confirmation signal is transmitted to another processing unit on the input side of the input signal supply source,

 Received by the first factor that an unreceived input signal that is not required for generating an output signal is generated by the input signal, or by a notification indicating that the output signal is not received, indicating that the output signal is not used. Due to a second factor of generating an unreceived input signal that is unnecessary, the confirmation signal is transmitted as the unnecessary notification to another processing unit on the input side of the supply source of the unreceived input signal, Receiving a dummy input signal from another processing unit on the input side to which the confirmation signal is sent,

 Transmitting an output signal and receiving the confirmation signal from another processing unit on the output side to which the output signal is transmitted;

 When the confirmation signal is received when the output signal is not transmitted, it is recognized as the unnecessary notification and a dummy output signal is transmitted.

 28. The method of claim 27, comprising transmitting the output signal as a pulse signal each time the output signal is generated by the logic unit.