JPWO2007037384A1 - System having a self-synchronous processing unit - Google Patents

Abstract

A system having a plurality of self-synchronous processing units is provided. One processing unit of the plurality of processing units receives an output signal based on the input side signal exchange unit for receiving the plurality of input signals respectively supplied from the plurality of input side processing units and the plurality of input signals. A logic unit for generating, an output signal exchange unit for transmitting an output signal to at least one output processing unit, and an input signal received by the input signal exchange unit to generate an output signal The first determination function that determines an unreceived input signal that is not used for the first time, and a notification that indicates that the output signal is not received, which is received by the output side signal exchange unit, determines the unreceived input signal that is not used for reception. 2 determination functions. Further, the signal exchange unit on the input side transmits a waste notification to the processing unit on the input side that supplies an unreceived input signal that has been judged not to be received by the first determination function or the second determination function.

Description

  The present invention relates to a system having a processing unit of a self-synchronous type, that is, an asynchronous type.

  As a digital circuit design method, a synchronous design method in which the entire system is controlled by a global clock is widely adopted. On the other hand, a self-timed (self-synchronous) design method that considers the command by the clock as a binding and aims at high performance and low power consumption by releasing from the binding, that is, an asynchronous design method is also being studied. One advantage of the self-timed design is that the connected circuit elements perform handshake to adjust the timing, so that a design that does not depend on element delay or wiring delay is possible. In addition, self-timed design can overcome some of the disadvantages or disadvantages of synchronous design. Disadvantages of the synchronous design are, for example, malfunction when the computation time exceeds the clock cycle, and waiting indefinitely until the clock boundary when the computation is completed earlier than the clock cycle.

  Several delay models for asynchronous circuits have been proposed. In US Pat. No. 6,606,356, an SDI (Scalable Delay Insensitive) model assuming a circuit in which a delay is in a predetermined range as a model for improving the performance of a DI (Delay Insensitive) model and a QDI (Quasi Delay Insensitive) model. Has proposed. US Pat. No. 6,732,336 proposes improving the performance of a QDI circuit by employing asynchronous pulse logic (APL) that replaces the two-phase or four-phase handshake of the QDI circuit with a pulse.

  One of the advantages of asynchronous design over synchronous design is that "you can proceed to the next without waiting indefinitely until the clock boundary when the operation is complete". However, in the asynchronous design, a predetermined protocol (handshake) is employed to transfer data between elements or units that do not share a clock. For this reason, the calculation should proceed faster in the asynchronous design, but due to the overhead of handshaking between circuit elements, a result faster than the synchronous design is not always obtained.

  One embodiment of the present invention is a system including a plurality of self-synchronous processing units. One processing unit of the plurality of processing units includes an input-side signal exchange unit for receiving a plurality of input signals respectively supplied from the plurality of input-side processing units, and an output signal based on the plurality of input signals. And an output side signal exchange unit for transmitting the output signal to at least one output side processing unit. The processing unit further includes a first determination function for determining an unreceived input signal that is unnecessary for generating an output signal based on an input signal received by the input side signal exchange unit, and the output side signal exchange unit And a second determination function for determining an unreceived input signal that is not required to be received based on a notification that indicates that the output signal is not used. Then, the signal exchange unit on the input side transmits a waste notification to the processing unit on the input side that supplies an unreceived input signal that has been judged not to be received by the first determination function or the second determination function.

  Another aspect of the present invention is a self-synchronizing processing unit. One type of processing unit includes an input-side signal exchange unit for receiving a plurality of input signals respectively supplied from a plurality of other input-side processing units, a logic unit, and at least one output-side unit. Received by an output-side signal exchange unit for transmitting an output signal to another processing unit, a first determination function for determining an unreceived input signal that is unnecessary for generating an output signal, and an output signal non-use notification And a second determination function for determining an unreceived input signal that is not required. The signal exchange unit on the input side transmits a waste notification to another processing unit on the input side that supplies an unreceived input signal that is judged to be unnecessary by the first determination function or the second determination function.

  Another type of self-synchronous processing unit is one that does not have a logic section that generates an output signal. For example, it functions as a buffer (including an inverter) or a branch. This processing unit forwards the waste notification transmitted from the output side to the input side. For this reason, this processing unit has an input-side signal exchange unit and an output-side signal exchange unit, and the input-side signal exchange unit is notified by an unnecessary notification of the output signal received by the output-side signal exchange unit. Then, a non-use notification is transmitted to another processing unit on the input side that supplies an unreceived input signal.

  In the processing unit in which the output-side signal exchange unit transmits the output signal to the plurality of output-side processing units, the generation of the output signal is unnecessary when the use-notification is received from all the output-side processing units. Therefore, the second determination function determines an unreceived input signal that is not required to be received when an output signal non-use notification is received from all of the plurality of output-side processing units.

  Another aspect of the present invention is a method for controlling a system having a plurality of self-synchronous processing units. This method is the first factor that an unreceived input signal that is unnecessary for generating an output signal is generated by an input signal received by an input-side signal exchange unit, or an output-side signal exchange unit received Due to a second factor that causes an unreceived input signal that is not required to be received due to a waste notification indicating that the output signal is not used, a waste notification is transmitted to the processing unit on the input side that is to supply the input signal. Including that.

Propagation of unnecessary notification can be added to a handshake protocol for transferring a data signal between processing units by transmitting a confirmation signal (acknowledge signal) when no data is input. As a result, the handshake regarding the non-use notification can be performed by the data signal. One such handshake protocol is as follows, and signal transfer is confirmed on the input / output side by any of the following processes p1 to p4.
p1. When the input signal is received, a confirmation signal is transmitted to the input side processing unit (other processing unit) of the input signal supply source.
p2. A confirmation signal is transmitted as a non-use notification to the input side processing unit (other processing unit) of the supply source of the unreceived input signal, and from the input side processing unit (other processing unit) to which the confirmation signal is transmitted Receive a dummy input signal.
p3. An output signal is transmitted, and a confirmation signal is received from a processing unit (another processing unit) on the output side of the transmission destination.
p4. If a confirmation signal is received when the output signal has not been transmitted, it is recognized as a notification not to be used, and a dummy output signal is transmitted.

  On the input side, signal transfer is confirmed by processing p1 or p2. On the output side, signal transfer is confirmed by processing p3 or p4. Therefore, it is desirable that the processing unit has a handshake function for confirming signal transfer by any one of the processes p1 to p4.

  Yet another aspect of the present invention is a method for communicating a signal that includes a self-synchronizing processing unit confirming the transfer of a signal to and from another self-synchronizing processing unit. . Confirming signal transfer (handshaking) includes the following.

When an input signal is received by the signal exchange unit on the input side, a confirmation signal is transmitted to another processing unit on the input side of the input signal supply source,
The first factor that an unreceived input signal that is not required for generating an output signal is generated by the input signal, or the unnecessary notification that indicates that the output signal is not received, which is received by the output-side signal exchange unit. Due to the second factor that causes the unreceived input signal to be generated, a confirmation signal is transmitted as a non-use notification to other processing units on the input side of the source of the unreceived input signal, and the destination of the confirmation signal is transmitted. Receiving dummy input signals from other processing units on the input side,
Transmitting an output signal, receiving a confirmation signal from another processing unit on the output side of the output signal, and
If a confirmation signal is received when the output signal has not been transmitted, it is recognized as a waste notification and a dummy output signal is transmitted.

The figure which shows the outline | summary of a self-synchronous type | system | group. The figure which shows schematic structure of a self-synchronous type processing unit. The figure which shows a two-wire-type self-synchronous element. 4 is a flowchart showing an internal operation of the element shown in FIG. 3. The flowchart which shows the outline | summary of the internal operation | movement of the processing unit shown in FIG. The flowchart which shows the further detailed internal operation | movement of the processing unit shown in FIG. The figure which shows a self-synchronous NOT gate element. FIG. 8A shows a synchronous signal branch, and FIG. 8B shows a self-synchronous signal branch. The figure which shows a self-synchronous buffer element. 10 is a timing chart in which handshaking is performed in the element of FIG. The timing chart of an example different from FIG. The timing chart of the example further different from FIG. FIG. 13 is a timing chart of an example further different from FIG. 6 is a flowchart showing an internal operation of a self-synchronous flip-flop. The flowchart which shows the further detailed internal operation | movement of a self-synchronous flip-flop. An example of a combinational logic circuit. 17 is a circuit in which the combinational circuit of FIG. 16 is changed to a configuration using a plurality of processing units with two inputs and one output. 18A to 18H show examples of the operation of the circuit shown in FIG. 19A to 19E are different examples showing the operation of the circuit shown in FIG. 20A to 20E show examples of the operation of the circuit shown in FIG. 17 by handshaking. FIG. 21A to FIG. 21D show examples of the operation of the circuit shown in FIG. 17 by handshaking following FIG. 22 (a) to 22 (d) show examples of the operation of the circuit shown in FIG. 17 by handshaking following FIG. 21 (d). An example of a sequential circuit. 24 is a circuit in which the sequential circuit of FIG. 23 is changed to a configuration using a plurality of 2-input / 1-output processing units. 25A to 25D show examples of the operation of the circuit shown in FIG. 24 by handshaking. 26 (a) to 26 (d) show examples of the operation of the circuit shown in FIG. 24 by handshaking following FIG. 25 (d). FIG. 27A to FIG. 27D show examples of the operation of the circuit shown in FIG. 24 by handshaking following FIG. FIG. 28A to FIG. 28D are examples showing the operation of the circuit shown in FIG. 24 by handshaking following FIG. FIG. 29A to FIG. 29D are examples showing the operation of the circuit shown in FIG. 24 by handshaking following FIG. FIG. 30A to FIG. 30D are examples showing the operation of the circuit shown in FIG. 24 by handshaking following FIG. 29D. 31 (a) to 31 (d) show examples of the operation of the circuit shown in FIG. 24 by handshaking following FIG. 30 (d).

BEST MODE FOR CARRYING OUT THE INVENTION

  One embodiment of the present invention is a system having a plurality of self-synchronous processing units, and generates an output signal based on the signal exchange unit on the input side for receiving a plurality of input signals and the plurality of input signals. And a logic unit for output and a signal exchange unit on the output side. When the logic implemented in the logic unit of the processing unit is a two-input AND, if one input signal is true, it is necessary to wait for the other input signal to determine the output signal. However, if one input signal is false, the output signal is false, and the other input signal is a signal that is unnecessary (don't care) for generating the output signal. Therefore, in the self-synchronous processing unit, there is no need to wait for the other input signal that is highly likely to be received at different timings, and an output signal can be output.

  Similarly, for other logics such as 2-input OR, an unreceived input signal may become don't care depending on an input signal received at a certain timing. In the case of a selector, when a selected side is determined by an input signal received at a certain timing, an unreceived input signal on the unselected side becomes don't care.

  If the output signal is don't care, the input signal in the processing unit that generates the output signal is also don't care. Therefore, in the first determination function, an unreceived input signal that is not necessary for reception of the output signal is determined (first factor). Further, in the second determination function, an unreceived input signal that is not required to be received is determined based on a notification that the output signal is not used (second factor). In this system, a waste notification is further transmitted to an input-side processing unit that supplies an unreceived input signal that has been judged as unnecessary by the first judgment function or the second judgment function.

  When an output signal is determined by one input signal in a certain processing unit, the output signal is transmitted to the other processing unit on the output side by the signal exchange unit on the output side. At the same time, for the unreceived input signal determined to be unnecessary in the first determination function, the input-side signal exchange unit does not use the input-side processing unit to supply the unreceived input signal. A notification is sent. Further, in the processing unit on the input side, the unnecessary notification is further transmitted to another processing unit on the input side that has not been received by the second determination function. Therefore, since an output signal is propagated from a certain processing unit to the output side, signal processing proceeds and the waiting state of the downstream processing unit is released. In addition, since the unnecessary notification is propagated to the unreceived input side, the waiting state of the upstream processing unit can be released and the signal processing can be advanced, so that the processing speed of the system can be improved.

  Further, it is desirable that the signal exchange unit on the output side of the self-synchronous processing unit transmits the output signal as a pulse signal each time the output signal is generated by the logic unit based on the input signal. The processing unit according to the embodiment of the present invention outputs a pulse of the output signal every time the output signal is generated regardless of whether or not the value of the output signal is changed by logic. Therefore, the processing unit transmits an output signal once per process for one cycle of the user clock. This reflects the property of the synchronous user circuit that “all signal lines transmit a value once per clock cycle”.

  In the self-synchronous system of the embodiment of the present invention, handshaking is performed once between all the processing units. Each time handshake is performed, it can be considered that the process for one cycle of the user clock of the synchronous user circuit proceeds. For this reason, it is possible to design a self-synchronous, that is, asynchronous circuit, based on the concept of synchronous design that is widely used.

  It is desirable that the signal exchange unit on the output side transmits the output signal as a signal that shifts to three states. An example of a signal that shifts to three states is a signal indicating neutrality and binary values (two states) that do not include the neutral state. It is also possible to transmit an output signal (input signal) by a two-wire system. However, in order to use the output signal as a confirmation signal when propagating the unnecessary notification downstream, in the case of the two-wire system, there is a possibility that the result of handshaking is different if the delay amount is different. By transmitting the output signal as a signal that shifts to three states, the output signal (input signal) can be exchanged by a single line (one-wire type), so that the problem associated with the delay can be solved beforehand. The three states can be realized by converting the voltage into plus, zero, and minus, for example, if it is an electric signal. In the case of an optical signal, for example, the polarization state can be changed to three states.

  The processing unit preferably includes a memory for storing an unreceived input signal or an input signal that cannot be processed by a confirmation signal. The self-synchronous processing unit preferably includes a memory for storing a received signal, for example, an input signal or a confirmation signal, as a token (event token) that advances an event. Since the processing unit includes a memory for storing a signal that cannot be processed, the processing related to the received signal can proceed.

  The self-synchronous system of the embodiment of the present invention does not require a global clock. Therefore, there is no restriction that the processing time (latency) in each processing unit included in the self-synchronous system must be shorter than the global clock period. For this reason, it becomes possible to change the logic of the logic part of a processing unit, or the connection of a processing unit flexibly. Accordingly, the self-synchronous system is suitable for a reconfigurable system in which the logic for generating the output signal in the logic unit can be changed.

  In one form of the reconfigurable system, the signal exchange unit on the input side has a function of changing the processing unit on the input side, and the signal exchange unit on the output side has a function of changing the processing unit on the output side. The system includes a processing unit. An example of such a system is such that the input side and output side signal exchange units include communication or data transmission functions, and the processing units connected to each can be changed wirelessly or by wire. Another form of the reconfigurable system is a communication system that enables exchange of signals between a plurality of processing units, and further includes a communication system that can reconfigure the connection of the plurality of processing units. It is.

  This self-synchronous system may be a distributed system in which a plurality of computers are connected by a computer network realized by radio or wire. Further, an integrated circuit system in which a plurality of elements having appropriate arithmetic functions are housed in one chip and connected by electronic or optical may be used. One form of the integrated circuit unit includes a plurality of processing units and a routing matrix for transmitting signals between the plurality of processing units. An example of the routing matrix is a circuit in the integrated circuit unit that can be reconfigured by changing connections between at least some of the processing units included in the plurality of processing units.

  FIG. 1 shows an example of a self-synchronous integrated circuit device. This integrated circuit device (integrated circuit unit, device, or system) 1 includes FFT (Fast Fourier Transform) calculation, various calculation processes including decoding of data compressed by MPEG, routing by IP address, and data transmitted by packets. It can be used for a wide variety of purposes such as network processing including reconfiguration. The integrated circuit unit 1 can be configured to execute one or a plurality of processes as a single system. It is also possible to construct one system by combining a plurality of integrated circuit units 1. Furthermore, it is also possible to construct one system by combining one or a plurality of integrated circuit units 1 with a general-purpose CPU or other dedicated circuit.

  The integrated circuit unit 1 includes a plurality of processing units (Processing Unit (PU), Processing Element (PE) or Configurable Logic Block (CLB), hereinafter PU) that can change the respective arithmetic logics, and a plurality of the processes. And a routing matrix 5 for configuring a path connecting the units (PUs) 10. The routing matrix 5 is a connection unit (switching unit or switching unit or wiring unit) that can change the connection configuration of the routing matrix 5 by changing the connection between the wiring (wiring group) 6w for transmitting data between the PUs 10 and the wiring group 6w. Selector unit) 6s. The integrated circuit unit 1 further includes a configuration memory 2 that stores the configuration data 7 of the PUs 10 and the routing matrix 5, and configuration data control for supplying the configuration data 7 from the configuration memory 2 to the PUs 10. Unit 3. A plurality of sets of configuration data 7 are stored in the configuration memory 2. The control unit 3 selects one of a plurality of sets of configuration data 7 and supplies it to the PUs 10 and the routing matrix 5 if necessary. The routing matrix 5 also has a function of transferring the configuration data 7 to the PUs 10 and the connection unit 6s.

  The routing matrix 5 is not limited to one in which the wiring 6w is arranged in a matrix. For example, the PUs 10 may be connected to form a network node. The routing matrix 5 is also a wired communication system that enables exchange of signals between a plurality of PUs 10. When the PUs 10 are distributed, the PUs 10 can be connected by a wireless communication system. By reconfiguring the connection of the PUs 10 by a wired or wireless communication system, the circuit configured by the PUs 10 can be changed.

  FIG. 2 shows a schematic functional configuration of the self-synchronous asynchronous processing unit (PU) 10. The PU 10 includes an input interface 11 that is an input-side signal exchange unit, a logic unit 12 that determines an output Y, and an output interface 13 that is an output-side signal exchange unit. The input interface 11 receives two input signals Ad and Bd supplied from two other input-side PUs 10a and 10b, respectively. The two input signals Ad and Bd are not necessarily supplied from the PUs 10a and 10b at the same timing. Therefore, the input interface 11 that is the signal exchange unit on the input side receives the two input signals Ad and Bd, respectively.

  The logic unit 12 determines the output Y based on the inputs A and B given by the input signals Ad and Bd, respectively. The output interface 13 transmits an output signal Yd indicating the output Y of the logic unit 12 to another processing unit (PU) 10y on the output side. Furthermore, PU10 is provided with the control unit 15 which controls the internal operation | movement of PU10. Further, the PU 10 includes a queuing memory 14 that stores a signal that cannot be processed due to an unreceived signal.

  The control unit 15 includes a first determination function 18 and a second determination function 19. The first determination function 18 determines an unreceived input signal that is unnecessary for generating the output signal Yd based on the input signal Ad or Bd received by the input interface 11. The second determination function 19 determines an unreceived input signal that is not required to be received by the output interface 13 that has been received by the output interface 13.

  Further, the control unit 15 includes a handshake function 17 for confirming transmission / reception of signals. The handshake function 17 confirms transmission / reception of the input signals Ad and Bd with the PUs 10a and 10b on the input side. The handshake function 17 confirms transmission / reception of the output signal Yd with the output-side PU 10y.

  When the handshake function 17 receives the input signal Ad, the handshake function 17 transmits a confirmation signal (acknowledge signal) Ak to the PU 10a on the input side of the supply source of the input signal Ad. With this process, the PU 10 exchanges input signals (handshake) with the PU 10a once. That is, this process is one of handshakes (protocols) between the PU 10 and the PU 10a.

  Similarly, when the handshake function 17 receives the input signal Bd, the handshake function 17 transmits a confirmation signal (acknowledge signal) Bk to the PU 10b on the input side of the supply source of the input signal Bd. This process is one of handshakes (protocols) between the PU 10 and the PU 10b. The handshake function 17 transmits an output signal Yd and receives an acknowledge signal Yk from the PU 10y on the output side of the transmission destination. This process is one of handshakes (protocols) between the PU 10 and the PU 10y.

  Further, the handshake function 17 transmits a waste notification to an input-side processing unit that supplies an unreceived input signal that has been judged as unnecessary by the first determination function 18 or the second determination function 19. The handshake function 17 transmits one or both of the acknowledgment signals Ak and Bk as a non-use notification (don't care notification) to one or both of the PUs 10a and 10b on the input side that are determined not to be received. Further, the handshake function 17 receives a dummy input signal supplied from one or both of the previous PUs 10a and 10b that have transmitted the acknowledge signal in a state where the input signal is not received. These processes are one of handshakes (protocols) between the PU 10 and the PUs 10a and / or 10b.

  Further, the handshake function 17 receives a don't care notification from the PU 10y on the output side. When the handshake function 17 receives the acknowledge signal Yk when the output signal Yd is not transmitted, the handshake function 17 recognizes it as a don't care notification. The handshake function 17 transmits a don't care notification to the second determination function 19 and transmits a dummy output signal Yd. This process is one of handshakes (protocols) between the PU 10 and the PU 10y.

  The control unit 15 has a reconfiguration function 16 for changing the processing content of the PU 10 by the configuration data 7 supplied from the configuration memory 2 via the routing matrix 5. The reconfiguration function 16 changes the logic of the logic unit 12 of the PU 10 based on the configuration data 7. The reconfiguration function 16 also changes the processing unit connected to the input interface 11 and the output interface 13. As a result, the data path constituted by the plurality of PUs 10 in the system 1 is reconfigured, and the function of the data path is changed. In this example, the input interface 11 and the output interface 13 are connected to other PUs via the routing matrix 5. Also by changing the configuration of the connection unit 6s of the routing matrix 5, the data path constituted by the plurality of PUs 10 in the system 1 can be reconfigured.

  FIG. 3 shows an example of a two-wire, two-input, one-output self-synchronous element 90. The 2-input 1-output logic element has two signals A and B as input signals and one signal Y as an output signal. For each signal, a data line (such as A0) for transmitting logic “0”, a data line (such as A1) for transmitting logic “1”, and an acknowledge line (such as Ak) are necessary. For this reason, a total of nine signal lines are connected to the element 90.

  FIG. 4 is a flowchart showing the internal operation of the self-synchronous processing element (PE) 90 shown in FIG. First, in step 91, the PE 90 waits for an input signal A0, A1, B0 or B1 indicating logic “0” or logic “1” to be transmitted from the input data line. When these signals are transmitted, the PE 90 determines the source of the input signal in step 92. In step 93 or 94, the PE 90 returns an acknowledge signal Ak or Bk corresponding to the input signal to the supplier. In step 95, the PE 90 determines whether the output value needs to be changed. If the output signal Y0 or Y1 needs to be changed, the PE 90 transmits a new output value at step 96. Thereafter, in step 97, the PE 90 waits for an acknowledge Yk of the output signal.

  In this self-synchronous element 90, the input signal and the output signal are the same data signal only in the difference between the input side and the output side. If these data signals and acknowledge signals are not guaranteed to disappear or multiply during transmission, and if a circuit design corresponding to an appropriate delay model has been made, a system using this self-synchronous element 90 is correct. Operate.

  A self-synchronous element (processing unit PU) 10 shown in FIG. 2 is a one-wire, two-input, one-output self-synchronous element (processing unit). The one-wire PU 10 assigns two actual signal lines for each logical signal. For this reason, a total of six signal lines are connected to the PU 10. The two signal lines for the other PUs 10 are a data line 5a and an acknowledge signal line 5b, respectively. The data line 5a is a signal line for transmitting logic “0” or logic “1” as the data signals Ad, Bd, and Yd. The acknowledge signal line 5b is a signal line for transmitting the acknowledge signals Ak, Bk and Yk.

  The output interface 13 is connected to a positive potential power line and a negative potential power line. The output interface 13 outputs a positive pulse when transmitting a logic “1 (true)” as the output signal Yd, and outputs a negative pulse when transmitting a logic “0 (false)”. Therefore, the data line 5a propagates, as data signals Ad, Bd, and Yd, a positive pulse that transmits logic “1” and a negative pulse that transmits logic “0”. The relationship between logic and potential is only an example, and the relationship can be reversed.

  FIG. 5 is a flowchart showing an internal operation related to data output of the self-synchronous PU 10 shown in FIG. This flowchart shows the operation of the data output except for the don't care notification function for comparison with the two-wire self-synchronizing element 90. In step 21, the PU 10 waits for the input signal Ad or Bd to be received. In step 22, when the PU 10 confirms reception of the input signal Ad, in step 23a, the PU 10 transmits an acknowledge signal Ak and performs handshaking. In step 24a, the PU 10 waits for the input signal Bd. When receiving the input signal Bd, in step 25a, the PU 10 transmits an acknowledge signal Bk and performs handshaking. On the other hand, when the reception of the input signal Bd is confirmed in Step 22, the PU 10 transmits the acknowledge signal Bk and performs handshaking in Step 23b. Further, in step 24b, the PU 10 waits for the input signal Ad. When receiving the input signal Ad, in step 25b, the PU 10 transmits an acknowledge signal Ak and performs handshaking.

  When receiving the input signals Ad and Bd, in step 26, the PU 10 transmits the output signal Yd. In step 27, the acknowledge signal Yk is received and the handshake is completed.

  As described above, the basic operation of the one-wire PU 10 is to transmit and receive signals once for all input / output lines in one process. That is, in the PU 10, one signal transmission through all the input / output lines corresponds to one cycle of the user clock. For this reason, unlike the two-wire self-synchronous design element, it has the property of “all signal lines transmit values once per clock cycle”, which is equivalent to the synchronous element. Therefore, a clock synchronous system design can be applied to a system using the PU 10.

  In order to actively implement a clock synchronous system design, the basic operation of the PU 10 is as follows. The signal is received once for all the inputs and then the output is output once. The output is transmitted every time regardless of whether or not the output value needs to be changed.

  In the present embodiment, a clock-synchronized user circuit can be mounted without using a global clock by the device (system) 1 including the PU 10. For this reason, the man-hours for clock skew adjustment and critical path adjustment can be omitted. Furthermore, with the handshake backflow function described below, it is possible to proceed as a result with only one side input while maintaining the characteristics of compatibility with the clock synchronous type. Further, by using the queuing memory 14, the processing speed can be further improved while maintaining the feature of being compatible with the clock synchronous type.

  FIG. 6 is a flowchart regarding the internal operation of the self-synchronous PU 10 having two inputs and one output shown in FIG. This flowchart shows the internal operation including the handshake backflow function. First, in step 31, the PU 10 waits for pulses from the input data lines Ad and Bd and the output acknowledge line Yk.

  A typical example shown in FIG. 5 is a case where a data pulse is supplied from the input data line Ad. Since the PU 10 receives the input signal Ad, the PU 10 issues an acknowledge pulse from the input acknowledge line Ak in step 35 (acknowledge signal Ak). Next, before waiting for the pulse (input signal Bd) of the other data line Bd, the PU 10 determines in step 36 whether or not the input signal Bd is unnecessary (don't care) in order to determine the output signal Yd. If the input signal Bd is necessary, the PU 10 proceeds to step 39. In step 39, since the output signal is not determined, the PU 10 holds the input signal Ad in step 46 and waits for the input signal Bd to be received. Next, when the input signal Bd is received in step 31, the PU 10 transmits the acknowledge signal Bk in step 35. Through step 39, the PU 10 transmits an output signal Yd in step 41. The PU 10 returns to step 31 and waits for the acknowledge signal Yk.

  On the other hand, in step 36, the value of the output Y is determined only by the value of the input A, and the value of the input B may be don't care. That is, in step 36, if the output signal Yd is determined by the input signal Ad and the input signal Bd is don't care, the PU 10 transmits the acknowledge signal Bk in step 38 without waiting for the input signal Bd. At the same time, in step 41, the PU 10 transmits the determined output value as the pulse signal Yd. The acknowledge pulse Bk transmitted in step 38 is not a receipt response message that “data pulse Bd has been received” but a notification message that “input B is don't care”.

  Thereafter, returning to step 31, the PU 10 waits for an acknowledge pulse Yk and a data pulse Bd. The data pulse Bd does not indicate the logical value of the input B, but is an acknowledgment response message to the notification that “the value of the input B is don't care”, and may be a positive pulse signal or a negative pulse signal.

  In step 31, the operation of the PU 10 when the input signal Bd comes before the input signal Ad is just the exchange of the input signal Ad and the input signal Bd in the above. In the following, pulse signals propagated through the input lines A and B will be described as input signals Ad and Bd, and pulse signals propagated through the output line Y will be described as output signals Yd. The same applies to the acknowledge signals Ak, Bk and Yk.

  As can be seen from the above-described operation, in step 31, there may be an acknowledge signal Yk that is not intended for handshaking (protocol) indicating that the output signal has been confirmed. The acknowledge signal Yk in this case is a notification from the PU 10y on the output side that “the value of the output Y is don't care”. Therefore, in step 52, the PU 10 transmits a dummy output signal Yd as a don't care acknowledgment response. The pulse signal of the output signal Yd may be either plus or minus.

  Simultaneously with the output of the dummy output signal Yd, the PU 10 transmits an acknowledge signal Ak and / or Bk to the PU 10a and / or 10b on the input side that is to supply an unreceived input signal in step 57. For example, if the input signal Ad has been received, the PU 10 transmits an acknowledge signal Bk to the PU 10b. If the input signals Ad and Bd are not received, the PU 10 transmits the acknowledge signals Ak and Bk to the PUs 10a and 10b, respectively. These acknowledge signals are messages notifying the processing unit on the signal transmission side that “the values of signals A and B are don't care”. In step 31, the PU 10 waits for a dummy input signal Ad or Bd (a dummy output signal in the PUs 10a and 10b) of the corresponding don't care acknowledgment response.

Therefore, the PU 10 has the following four types as handshake protocols for confirming signal transmission / reception.
Type 1) When receiving the input signal Ad or Bd, the PU 10 transmits an acknowledge signal Ak or Bk to the PU 10a or 10b on the input side of the source of the input signal Ad or Bd.
Type 2) The PU 10 transmits an acknowledge signal Ak or Bk as an unnecessary notification (don't care notification) to the PU 10a or 10b on the input side of the supply source of the unreceived input signal Ad or Bd, and a dummy input from the PU 10a or 10b A signal Ad or Bd is received.
Type 3) The PU 10 transmits the output signal Yd, and receives the acknowledge signal Yk from the PU 10y on the output side of the transmission destination.
Type 4) When the acknowledge signal Yk is received when the output signal Yd is not transmitted, the PU 10 recognizes it as a don't care notification and transmits a dummy output signal Yd.

  Type 1 and type 3 handshakes relate to normal transmission and reception of data pulses. Type 2 and type 4 handshakes are intended to propagate a don't care notification using a data pulse and an acknowledge pulse.

  The PU 10b on the input side may output the normal input signal Bd, and at the same time, the PU 10 may output the acknowledge signal Bk for notification that “the value of the input B is don't care”. In that case, the sending PU 10b misunderstands the acknowledge signal Bk as a normal receipt response. The receiving PU 10 misunderstands the input signal Bd as a don't care acknowledgment response. Even if misunderstood each other in this way, the handshake for one cycle of the user clock is still completed, and there is no problem in the operation of the system 1. Therefore, it is not necessary to take any measures to prevent this misunderstanding.

  The flowchart shown in FIG. 6 will be described in more detail. In step 31, the PU 10 waits for a signal to be received. The signals received by the PU 10 are the input signals Ad and Bd and the acknowledge signal Yk as an output signal. Upon receiving any signal, the PU 10 determines in step 32 whether or not a handshake for one signal has been completed based on the signal. There are four types of handshaking as described above. If any signal has been sent in advance and the receipt confirmation signal has been received, the handshake (type 1 or type 3) for one cycle of the user clock is completed. Therefore, the PU 10 returns to step 31 and waits for the next signal.

  However, if the handshake is completed in step 32, in step 43, it is confirmed in the queuing memory 14 whether or not there is a signal waiting for transmission for the data line for which the handshake is completed. If there is a signal waiting for transmission, the PU 10 transmits the signal in step 44. For example, it is assumed that the input signal Ad is continuously received and the input signal Bd becomes don't care by the first and second input signals Ad. In this case, first, the PU 10 outputs the don't care notification acknowledge signal Bk to the uninput input signal Bd corresponding to the first input signal Ad, and the second input signal until the handshake is completed. The state may be held without outputting the acknowledge signal Ak to Ad.

  On the other hand, the PU 10 may transmit the acknowledge signal Ak prior to the second input signal Ad. In this case, the PU 10 can store the second don't care notification for the PU 10b on the input side in the memory 14 for queuing. As a result, processing proceeds in the PU 10a and the upstream processing unit. In this case, in step 32, when the PU 10 receives the input signal Bd with respect to the acknowledge signal Bk of the first don't care notification, in step 44, the PU 10 receives the next don't care notification stored in the queuing memory 14. An acknowledge signal Bk can be output. By this don't care notification, the processing of the PU 10b and the processing unit on the upstream side can be advanced.

  The same applies to the output signal Yd. If the input signal Bd is don't care with respect to the first and second input signals Ad, the first and second output signals Yd are determined by the first and second input signals Ad. Therefore, the first output signal Yd is transmitted and the second output signal Yd is stored in the queuing memory 14. When the PU 10 confirms the acknowledge signal Yk for the first output signal Yd in step 32, it can transmit the next output signal Yd in step 44.

  In addition, as shown below, there may be a signal that is held in the state of an event token without transmitting an acknowledge signal because the processing cannot proceed while receiving the signal. In that case, in step 48, processing of the held signal is started without waiting for reception of the next signal.

  If the handshake is not complete due to the received signal, a new cycle has started. First, in step 33, if the memory 14 for queuing is about to be full or the setting is such that continuous reception is not permitted, the PU 10 cannot perform handshake by performing an acknowledgment. Therefore, in step 49, the PU 10 stores the received signal as an event token in the queuing memory 14, and waits for the next signal. That is, the memory 14 stores a received input signal that requires another input signal in order to generate an output signal, and stores a signal that becomes another event token including the input signal.

  In step 34, if the received signal is the input signal Ad or Bd, it is a data input. If the received signal is an acknowledge signal Yk, it is a don't care notification. If it is an input signal, the PU 10 outputs an acknowledge signal Ak or Bk in step 35.

  In step 36, the PU 10 determines whether or not the received input signal is to make the other input signal unnecessary (don't care) (determination of the first factor). When the don't care input signal is generated, the PU 10 determines in step 37 whether or not the don't care notification can be transmitted for the unreceived input signal. For example, when the input signal Ad is continuously received as described above, the PU 10 outputs the acknowledge signal Bk that becomes the second don't care notification until the input signal Bd that is an acknowledge is received with respect to the PU 10b on the input side. Can not. Therefore, in step 45, the PU 10 stores a don't care notification for the PU 10b on the input side in the queuing memory 14, and transmits it in step 44. If the don't care notification can be sent to the processing unit on the input side that is the source of the input signal that has become don't care, the PU 10 sends an acknowledge signal in step 38.

  In step 39, the PU 10 determines whether or not the output signal Yd is determined. If none of the unreceived input signals are don't care according to the received input signal, the output signal Yd is not determined until the unreceived input signal is received. Therefore, in step 46, the PU 10 stores the input state in the memory 14 and waits for the next signal. Note that there is logic in which the output signal Yd is not determined even if one input signal of a plurality of unreceived input signals becomes don't care. For example, a selector. Also in this case, the PU 10 stores the input state in the memory 14 and waits for the next signal.

  If the output signal Yd is determined, the PU 10 checks in step 40 whether or not the output signal Yd can be transmitted. If it can be output, in step 41, the PU 10 transmits an output signal Yd. As described above, in a state where the output signal Yd is continuously determined by continuously receiving the input signal Ad, it may be determined in step 40 that the second output signal Yd cannot be transmitted. There is sex. In this case, in step 47, the PU 10 stores the output signal Yd that cannot be transmitted in the queuing memory 14, and transmits it in step 44.

  In step 41, the output signal is transmitted only to the processing unit on the output side that is not notified of the don't care notification. That is, the output signal is not transmitted to the processing unit on the output side that is notified of the don't care notification. At the same time, in step 54, which will be described later, the don't care notification from the processing unit on the other output side stored in the queuing memory is canceled. This function is a function that can be omitted in the one-output type and one fan-out PU 10 and a system using the same. On the other hand, this function is necessary for multi-output and multi-fanout PUs and systems including them. For example, when a don't care notification is received from one output side PU and a don't care acknowledgment response is returned, and the input signal Ad comes and the output signal is determined, only the other output side PU has a normal output signal. Is sent.

  At the same time as the PU 10 outputs the normal output signal Yd, the PU 10y on the output side may output the acknowledge signal Yk for notification that “the value of the output Y is don't care”. In that case, as in the case of the input signal, the handshake types are mistaken for each other. However, there is no problem in the operation of the system. Therefore, it is not necessary to take any measures to prevent this misunderstanding.

  As described above, if the received signal is the acknowledge signal Yk in step 34, it is a don't care notification (determination of the second factor). Therefore, in step 52, the PU 10 outputs a dummy output signal Yd for acknowledgement. At the same time, in step 57, the PU 10 transmits an acknowledge signal Ak and / or Bk that is a don't care notification to the PUs 10a and / or 10b that are the sources of the unreceived input signals. By the process of receiving the don't care notification and transferring it to the upstream (input side), the don't care notification can be propagated upstream or backward.

  In the process of flowing back the don't care notification, the don't care notification Yk may continuously arrive. In step 55 shown in FIG. 6, the PU 10 determines whether or not a don't care notification can be transmitted for each input processing unit that flows back the don't care notification. If the handshake for the preceding don't care notification has not been completed, the PU 10 stores the don't care notification in the queuing memory 14 at step 56. In that case, in step 57, the don't care notification is transmitted only to the processing unit for which the handshake has been completed for the preceding don't care notification.

  Steps 53 and 54 shown in FIG. 6 are functions that can be omitted in the PU 10 of one output type and one fan-out. In a multi-output or multi-fan-out processing unit, the input signal becomes don't care typically when all the output signals become don't care. Therefore, if the PU 10 is a multi-output processing unit, it is determined in step 53 whether or not a don't care notification can be transmitted to the upstream. If the don't care notification is not notified from all the output side processing units, the don't care notification from the output side is stored in the queuing memory 14 in step 54, and the next signal is awaited.

  If the logic of the logic unit 12 is a 2-input AND and the input signal Ad is “0 (false)”, the other input signal Bd is don't care. If the logic of the logic unit 12 is 2-input OR and the input signal Ad is “1 (true)”, the other input signal Bd is don't care. In these cases, the other input signal becomes don't care and the output signal Yd is determined. Therefore, the two-input PU 10 can perform determination of occurrence of don't care and determination of determination of an output signal in one step.

  Of these internal operations of the PU 10, the handshake function 17 performs control related to handshaking. In steps 36 to 38, the first determination function 18 performs control for generating a don't care notification. Further, the second determination function 19 performs control for reversing the don't care notification in steps 52 to 57.

  By combining a plurality of 2-input 1-output PUs 10, a processing unit that realizes multi-input logic can be configured. Alternatively, it is possible to prepare a multi-input processing unit. For example, it is possible to configure a processing unit in which the logic of the logic unit 12 is a 2to1 selector and three signals including a selector control signal are input as input signals. In this case, if the selector control signal selects the input signal Ad, the input signal Bd becomes don't care. However, the output signal Yd is not determined until the input signal Ad is received. Therefore, it is desirable to provide step 39.

  If the logic of the logic unit 12 is 2-input XOR, the output signal Yd is not determined unless both the input signals Ad and Bd are determined. Therefore, the other input signal does not become don't care by one input signal. For this reason, it is possible to omit the processing of steps 36 to 38 by the first determination function 18 in the internal operation of the PU 10, and the don't care notification mainly includes the processing of backflow after step 52.

  When the logic unit 12 is NOT, since only one input is used, only one input of the PU 10 is used. For this reason, the flow of internal processing is further simplified. That is, it is possible to omit steps 36 to 38 from the internal operation of the PU 10. With respect to the don't care notification, only the backflow processing after step 52 is performed. Further, when the NOT gate is mounted as a self-synchronous element, it is not necessary to adopt the PU 10 and make a circuit that executes this flowchart gracefully.

  FIG. 7 is a different example of mounting a NOT gate as a self-synchronous element. As shown in this figure, as the NOT gate, an element 61 including a voltage inverter 62 that converts a plus pulse into a minus pulse and a minus pulse into a plus pulse may be mounted. However, when the voltage reversal process takes time, it is advantageous for the performance of the entire system that the Ak acknowledge pulse can be returned earlier if the flowchart of FIG.

  Signal branching (multi-fanout) in a self-synchronous system is different from a normal synchronous circuit. In the case of a synchronous circuit, as shown in FIG. 8A, a signal can be branched by simply connecting lines. In the self-synchronous device, as shown in FIG. 8B, the logical signal is physically a pair of a data line and an acknowledge line, and the logical signal is branched by simply connecting the lines. It is not possible. One method is to install the functions of steps 53 to 54 in the PU 10 of the signal generation source to support multi-fanout. Another method is to connect a processing unit 63 for signal branching. The branch processing unit 63 has a logic unit 63c. The internal operation of the logic unit 63c includes the processing described in the flowchart shown in FIG. 6 after step 52, particularly for multi-output, and processing for determining the occurrence of don't care based on the input signal from step 36 to step 39. Does not include.

  A buffer circuit with one input and one output (one fan-out) has no logical function. However, the buffer circuit is used for assisting signal branching and long-distance signal transmission in a synchronous circuit in an actual implementation. In the self-synchronous system 1, such a buffer is used exclusively to assist in long-distance signal transmission. It is also possible to assign a PU10 with two inputs and one output for a buffer with one input and one output. Alternatively, as shown in FIG. 9, a processing unit 64 dedicated to the buffer circuit can be mounted. The processing unit 64 for a buffer with one input and one output (one fan-out) has a logic unit 64c. The operation of the logic unit 64c does not include the process of determining the occurrence of don't care based on the input signal from step 36 to step 39 in the flowchart shown in FIG. Is not included).

  The buffer processing unit 64 returns an acknowledge signal Ak when the input signal Ad arrives, and returns a don't care acknowledgment response (output signal) Yd when the don't care notification (acknowledge signal) Yk arrives. As a result, the handshake turnaround time can be reduced and the system can operate at a higher speed than when performing a long distance handshake without a buffer.

  The self-synchronous processing unit control method shown in FIG. 6 is also applicable to circuits that implement other logic, such as multi-input AND gates, NAND gates, and AND-OR composite gates. Therefore, the PU 10 can provide a self-synchronous service even when the logic of the logic unit 2 is flexibly changed by the reconfiguration function 16. Furthermore, the PU 10 can change the connection between the processing units on the input side and the output side via the input interface 11 and the output interface 13, and the system 1 can reconfigure the routing matrix 5. For this reason, the asynchronous system 1 can flexibly mount various circuits or data paths, and can execute various applications by dynamically reconfiguring the data paths.

  An example of the system 1 including a large number of PUs 10 can implement a multi-stage combinational logic circuit by changing the logic of the PUs 10. In this system, when evaluating a logic circuit, not only a handshake “data → acknowledge” is performed from the input stage to the output stage, but also “don't care notification → The handshake can also be reversed as “acknowledgment response”. For this reason, the handshake overhead problem which was the weak point of the conventional self-timed design mounting system can be reduced.

  This design approach not only guarantees that device pulses will not disappear or multiply during transmission, but also guarantees that two pulses will not interchange or merge during transmission. Also request. This is because, after a certain processing unit issues a data pulse of a dummy output signal Yd for don't care acknowledgment response for a certain clock cycle, and before the signal Yd reaches the PU 10y on the output side, the PU 10 This is because the data pulse of the normal output signal Yd may be output. In this situation, two pulses exist simultaneously on the data line that transmits the output signal Yd, and if these pulses are interchanged or merged during transmission, the receiving PU 10y malfunctions. Therefore, in order to prevent malfunctions, it is necessary to ensure that pulses are not interchanged or merged during transmission. However, the requirement to “guarantee that pulses are not interchanged or merged during transmission” is very reasonable and is not a constraint that is particularly burdensome for device manufacturers. In this system 1, overhead reduction by handshake backflow can be achieved only by designing a circuit in consideration of such restrictions.

  Further, in the system 1 using the PU 10 described above, the data line is described as a dual power supply specification of a positive power source and a negative power source so that the data line can be configured by one line (one). The system using the 2-wire self-synchronous element shown in FIG. 3, that is, the processing unit having a specification of two single-power-supply data lines, can be used as a “self-timed device for mounting a synchronous circuit with a handshake backflow function. It is possible to construct “elements”. However, in that case, the device manufacturer is requested to have the above-mentioned guarantee, and there is also a guarantee that “pulses sent one after another to the data line in one set reach the receiving side element in the same order”. Request.

  For example, consider a case where the output signal Yd is transmitted through a single power source data line of two signal lines Y0 and Y1. After sending the pulse signal Y0 as a dummy output signal for don't care acknowledgment response for a certain clock cycle on the sending side, before sending it to the receiving side element, the sending side element is used for the next clock cycle. There is a possibility that a normal pulse signal Y1 is output. There is a possibility that the data line for transmitting the pulse signal Y1 is extremely shorter than the data line for transmitting the pulse signal Y0, and the later-described pulse signal Y1 reaches the receiving side element first. In that case, the receiving side element regards the pulse signal Y1 as a dummy output signal for a don't care acknowledgment response, and regards the subsequently arrived pulse signal Y0 as a normal data pulse for the next clock cycle. For this reason, the system malfunctions. In order to prevent such a malfunction, manufacturing is performed by carefully aligning the wiring length and load capacity of the data line transmitting the signal Y0 and the data line transmitting the signal Y1 so that the subsequent pulse does not arrive first. There is a need.

  As in this example, if the data line has a two power supply specification, the output signal Yd is transmitted by one line. For this reason, there is no design or manufacturing problem as described above, and the demands on the device manufacturer can be relaxed. Depending on the type of device or manufacturer, in the case of dual power supply specifications, when the burden on the data line is greater than the careful manufacture of data line lengths and load capacities, a single power supply data line, one set system Should be adopted.

  Further, in the system 1 adopting the PU 10 described above, pulses (pulse signals) are used for exchanging signals through data lines and acknowledge lines. On the other hand, using a known 4-phase handshake or a 2-phase (transition signaling) handshake as a base handshake, it is possible to construct a “self-timed element for mounting a synchronous circuit with a handshake backflow function”. Is possible. However, the 4-phase handshake has a longer handshake turnaround time than the 2-phase handshake and the pulse method, and is not preferable in terms of performance. On the other hand, the two-phase handshake requires slightly forcible timing guarantee and timing adjustment when trying to realize it with the specification of two power sources (one data line). Therefore, in order to describe the self-timed element with a handshake backflow function in an easy-to-understand manner with a minimum timing constraint without failure, the above-described pulsed handshake method of the two power supply specification is suitable.

  Furthermore, the PU 10 is configured to proceed as much as possible with the received signals. One method is to store the fact as an event token when a signal is received continuously, as shown in steps 33, 48 and 49 of FIG. 6, but not to send an acknowledgment signal. It is.

  For example, when the output signal Yd is determined by the input signal Ad from the PU 10a on the input side, the acknowledge signal Bk for notifying the don't care is transmitted to the PU 10b on the input side, and the output signal Yd is transmitted to the PU 10y on the output side. The PU 10 waits for the acknowledge response output signal Bd or the acknowledge signal Yk. At this time, when the input signal Ad is further received from the PU 10a on the input side, the fact that the input signal Ad has come is temporarily stored in the memory 14 as an event token. Next, the PU 10 receives the desired input signal Bd and the acknowledge signal Yk, and the handshake in step 32 is completed. At this time, since the event token of the next input signal Ad already exists, the PU 10 immediately proceeds to step 34. At the same time, erase the token. There may be at most one event token for each of the signals Ad, Bd and Yk. This is because an unprocessed signal will not be repeatedly received unless an acknowledge signal for data reception or a response to acknowledge don't care is returned.

  In the PU 10, a queuing memory 14 is provided as a second measure for proceeding with processing based on each received signal. As long as the queuing memory 14 can be used, the PU 10 transmits an acknowledgment response to the received signal. That is, in step 33, for example, by not returning the receipt acknowledge signal Ak with respect to the input signal Ad, by utilizing the fact that the input Ad cannot come again because the acknowledge is not returned, other signals are used. For example, it waits for an acknowledge signal Yk. On the other hand, the PU 10a that has transmitted the input signal Ad waits for a reception acknowledge signal Ak. Therefore, the process of the PU 10a on the sending side can be advanced by returning the acknowledge signal Ak without waiting for the receipt of the acknowledge signal Yk. On the other hand, a signal to be output in response to the received input signal Ad is stored in the queuing memory 14 in step 45 or 47 and waits for transmission.

  Also, consider a case in which the don't care notification acknowledge signal Yk is continuously received. Specifically, the output signal Yd is transmitted as a don't care acknowledgment response to the first acknowledge signal Yk, and the input side don't care acknowledgment response is waited for the second don't care notification acknowledge signal Yk. . On the other hand, the processing of the output side PU 10y can be advanced by transmitting the output signal Yd as the don't care acknowledgment response also for the second acknowledge signal Yk. However, in Steps 55 and 56, the don't care notification for the processing unit for which no acknowledgment response has been obtained for the preceding don't care notification is stored in the queuing memory 14 and waits for transmission.

  10 to 13 show timings at which an input signal and an output signal are transmitted and received in the PU 64 of the buffer circuit shown in FIG. FIG. 10 is a time chart in which the operation of the PU 64 receiving the input signal Ad four times and transmitting it as the output signal Yd each time is repeated four times.

  In FIG. 11, the PU 64 processes the first data at the same straightforward timing as in FIG. When the PU 64 processes the second data, the third input signal Ad is received first from the second acknowledge signal Yk. In this case, it is set not to transmit the acknowledge signal in advance. Therefore, in step 49, the PU 64 queues as an event and waits for the second acknowledge signal Yk pulse. When receiving the second acknowledge signal Yk, in step 32, as soon as the PU 64 receives it, the process proceeds from step 48 to step 35 and step 39 to transmit the third acknowledge signal Ak and the third output signal Yd. The operation for the next third acknowledge signal Yk is the same. Since the fourth acknowledge signal Yk is received following the output signal Yd, the PU 64 does not queue as an event and processes it at a gentle timing.

  In FIG. 12, the PU 64 processes the first data at the same straightforward timing as in FIG. When the PU 64 processes the second data, the third input signal Ad is received first from the second acknowledge signal Yk. In this case, the queuing is performed in two stages, and the PU 64 transmits an acknowledge signal in advance to the second signal received during the processing related to the first signal, and the third signal is used as an event. It is set to queue. Therefore, the PU 64 waits for step 47, and then proceeds to step 44 from step 32 where the second acknowledge signal Yk is received, and transmits the third output signal Yd. Next, since the PU 64 receives the fourth input signal Ad in the same manner as described above before receiving the third acknowledge signal Yk, the PU 64 operates in the same manner as described above. The PU 64 receives the fifth input signal Ad before receiving the fourth acknowledge signal Yk, and subsequently receives the sixth input signal Ad. For this reason, the PU 64 transmits the fifth acknowledge signal Ak to the fifth input signal Ad, and waits for step 47. The PU 64 does not transmit the acknowledge signal Ak with respect to the sixth input signal Ad, and enters the wait of step 49. Thereafter, when the PU 64 receives the fourth acknowledge signal Yk, the PU 64 transmits the fifth output signal Yd in step 44. At the same time, the PU 64 proceeds from step 48 to step 35 and transmits an acknowledge signal Ak for the sixth input signal.

  Thereafter, the PU 64 receives the seventh input signal Ad before the fifth acknowledge signal Yk. Therefore, the PU 64 waits for step 49, waits for the fifth acknowledge signal Yk, transmits the sixth output signal Yd and the seventh acknowledge signal Ak, and the seventh output signal Yd Wait for. Next, the PU 64 waits for the sixth acknowledge signal Yk, transmits the seventh output signal Yd in step 44, and receives the seventh acknowledge signal Yk. Thus, even when the PU 64 receives the third input signal Ad immediately after returning the second acknowledge signal Ak, the PU 64 can perform processing without breaking the logic. The event token queuing process can refer to a technique called slack in a self-synchronous circuit design method.

  FIG. 13 is a diagram illustrating a state in which the don't care notification is reversed. In FIG. 13, the PU 10y on the output side operates ahead under the same queuing conditions as in FIG. Accordingly, FIGS. 13 and 12 can be described in the same manner except that the upper and lower sides are inverted, step 35 in FIG. 12 is changed to step 52, and step 47 is changed to step 56.

  Event token processing is important. This is because the process of outputting the acknowledge signal Ak and the output signal Yd also takes a predetermined time although it is minute, and the input signal Ad and the acknowledge signal Yk may be received during the minute period. In that case, those signals should be temporarily stored in the memory 14 as event tokens and immediately processed in the next step. Even when the input signal Ad and the acknowledge signal Yk are received simultaneously, only one of them can be received and the other cannot be ignored. Therefore, one signal that cannot be processed immediately is treated as an event token. In this case, regardless of which one is received first, the same result can be obtained by immediately processing the next step based on the remaining event token. It is only necessary to support at least one event token per input. However, if an acknowledge signal is returned and two or more cues are queued, it is possible to cope with slack and provide a higher-performance PU 10 and system 1.

  The above is a self-synchronous processing unit for implementing combinational logic. Therefore, by providing a self-synchronous element for mounting a flip-flop, a synchronous user circuit can be implemented in a self-synchronous system. The flip-flop starts from transmitting the output signal Yd with an initial value 0 in a 1-input 1-output processing unit similar to the buffer circuit, and then performs a handshake of the output signal Yd → acknowledge signal Yk and the input signal Ad → The handshake of the acknowledge signal Ak is performed once. Thereby, the operation of the flip-flop corresponding to one clock cycle of the synchronous user circuit that outputs the latched input signal by the acknowledge signal Yk can be realized.

  FIG. 14 is a flowchart of the basic internal operation of the flip-flop (FF). FIG. 15 is a flowchart of the internal operation of the flip-flop (FF) corresponding to the backflow handshake. First, as described above, in step 71, the FF starts from transmitting the output signal Yd with the initial value 0, and in step 72, the basic operation waits for the input signal Ad or the acknowledge signal Yk on the output side. In step 73, when the FF receives the input signal Ad prior to the output acknowledge signal Yk, in step 74, the FF transmits the input acknowledge signal Ak. In step 75, the FF waits for the output acknowledge signal Yk, and in step 76 transmits the output signal Yd. On the other hand, when the output acknowledge signal Yk is received prior to the input signal Ad, the FF waits for the input signal Ad in step 77. In step 78, the FF transmits the output signal Yd and the input acknowledge signal Ak.

  The handling of the input signals Ad and Ak is the same as the type 1 handshake handled in the basic flow of FIG. The handling of the output signals Yd and Yk is the same as that of the type 3 handshake in the basic flow of FIG. 6 when viewed from the outside, and an operation of “outputting data Yd for a certain cycle and receiving the corresponding acknowledge Yk” It is. However, in FIG. 14, it is as if “a transmission permission signal (transmission request signal in other words) indicating that preparation for receiving the next cycle data is ready is received, and a data signal Yd for the next cycle is received as a response thereto. As if it were a new type of handshake. Even so, the underlying idea is the same as that shown in FIG. Therefore, it is possible to incorporate a flip-flop function in the PU 10 that realizes the flow of FIG. In addition, it is possible to construct the system 1 including the PU 10 having a flip-flop function.

  In the basic flow of FIG. 14, the input value A received as the input signal Ad is output as the output signal Yd for the next clock cycle. Therefore, in the basic flow of FIG. 14 considered only within the range of one clock cycle, the input signal A is not handled as don't care, and the backflow of don't care notification due to handshaking does not occur. However, if the acknowledge signal Yk, which is a don't care notification pulse for the next clock cycle, comes in step 77 while waiting for the input signal Ad of a certain clock cycle, the output signal Yd of the next clock cycle is called don't care. That is, the input signal Ad in the current clock cycle is also don't care.

  FIG. 15 is a flowchart showing an internal operation for backflowing the handshake in that case. In step 81, when receiving the acknowledge signal Yk instead of the input signal Ad, the FF makes a determination in step 82, and in step 83, transmits a dummy output signal Yd of a don't care acknowledgment response and an acknowledge signal Ak of a don't care notification. In step 84, a dummy input signal Ad is received. Thereby, the backflow of the don't care notification is realized by the handshake. This internal operation is the same as the operation for reversing the don't care notification after step 52 of the PU 10 shown in FIG. 6, and the internal operation shown in FIG. 15 can also be realized by the PU 10.

  Even in the self-synchronous flip-flop, an undesired acknowledge signal Yk or input signal Ad may be received at the timing of waiting for the input signal Ad or acknowledge signal Yk to proceed the processing sequentially. These can be stored as event tokens in the PU 10. Further, it can be stored in the queuing memory 14 corresponding to the slack. A flip-flop is a buffer with a delay as is called a unit delay in the field of signal processing. Therefore, by introducing a self-synchronous flip-flop, the delay tolerance of the self-synchronous system can be enhanced.

FIG. 16 is a combinational logic circuit that realizes the following logical expression (1). FIG. 17 is a circuit in which the circuit shown in FIG. 16 is constructed by a two-input AND gate, a two-input OR gate, and a NOT gate, and is converted into a circuit that can be implemented in the system 1 having a plurality of PUs 10. As for signal branching, a dedicated signal branching processing unit 63 is used, which is clearly shown in the circuit diagram. The logic circuit shown in FIG. 16 can also be implemented by self-synchronous circuit elements such as multi-input gates and composite gates.
Z =! X1 & X2 & X3 + X1 &! X2 + X1 &! X3 (1)

  18 (a) to 18 (h) show, as a comparative example, the progress of handshaking when the circuit shown in FIG. 17 is executed in a self-synchronous manner without using the function of backflowing don't care notifications. Yes. One of the wires in the illustrated circuit is a set of a data line and an acknowledge line, and the handshake is completed when the data pulse (input signal and output signal) and the acknowledge pulse come and go. In the following, it is assumed that all wirings and processing in individual processing units have the same delay.

  As shown in FIG. 18, when there is no backflow function of don't care notification by handshake, each processing unit performs output handshake by determining the output value after the handshake of all inputs is completed. In this figure and the following, the wiring for which the handshake has been completed is indicated by a thick solid line when the value is “1” and by a thick dashed line when the value is “0”. Assuming that data pulses (1, 0, 1) are generated at inputs (X1, X2, X3) in FIG. 18 (a) and the handshake is completed, from FIG. 18 (b) to FIG. 18 (h) ), The handshake between the processing units is digested by one stage every unit time, and “1” is output as the output Z after 7 unit times.

  FIGS. 19A to 19E show the progress of handshaking when the backflow function of don't care notification by handshaking is used. The wiring in which the backflow handshake (don't care notification & understanding) has occurred is represented by a thick broken line. The operation up to FIG. 19B is the same as FIG. In FIG.19 (c), PU10c has generated the don't care notification using the handshake backflow function. Since the PU 10c is a 2-input AND and its lower input CB is found to be “0”, the output signal CYd is determined to be “0”. Therefore, in this cycle, the output signal CYd is output, and the unreceived input CA is treated as a don't care, and the handshake is reversed.

  In FIG. 19D, the input side of the PU 10c, that is, the upstream PU 10d receives the output don't care notification and treats the unreceived input DA as a don't care. Therefore, an acknowledge signal DAk for don't care notification is output. At this time, since the PU 10e on the input side is about to output a normal data pulse to the output EY, the acknowledge signal of the don't care notification and the normal output signal are mixed. That is, the PU 10d regards the normal output signal as a don't care acknowledgment response, and the PU 10e regards the don't care notification as an acknowledge signal for data reception.

  In FIG. 19 (e), the output FY is determined by the upper input FA in the PU10f of the last two-input OR. Therefore, a don't care notification is transmitted to the PU 10g on the input side of the lower input FB to reverse the handshake. Also in this case, since the PU 10g intends to transmit the output signal, the acknowledge signal of the don't care notification and the regular data pulse are mixed, and the handshake is completed in both PUs 10f and 10g.

  As can be seen from these figures, it takes 8 unit time to execute the circuit of FIG. 17 without the handshake backflow function, as shown in FIG. On the other hand, if there is a handshake backflow function, as shown in FIG. 19, the execution of the circuit of FIG. Whether handshake backflow occurs or not depends on the value of the signal. Therefore, if the handshake backflow function is provided, the circuit of FIG. 17 cannot always be executed in 5 unit times. For example, when the input (X1, X2, X3) is (1, 1, 0), it takes 8 unit time even if there is a handshake backflow function. However, in the self-synchronous system, unlike the concept of the synchronous circuit design, “Even if the handshake backflow function is present or not, it is necessary to secure a clock cycle corresponding to 8 unit hours. It is never judged. There is no global clock in a self-synchronous system. For this reason, there is no fixed clock cycle, and as soon as the handshake is completed according to the situation at that time, it can be considered that the processing corresponding to one cycle of the user clock is completed, and can proceed to the next. Accordingly, in the self-synchronous circuit 17, if the handshake backflow function is provided, when the input (X1, X2, X3) is (1, 0, 1), processing for one cycle of the user clock is performed in 5 unit times. The system performance can be improved according to the appearance frequency of the case.

  20 (a) to 22 (d) (FIGS. 20 (a) to (e), FIGS. 21 (a) to (d), FIGS. 22 (a) to (d)) are the same as those shown in FIG. The situation in which handshaking proceeds in a synchronous circuit is shown in more detail. In these figures, the triangles pointing rightward are data line pulses, that is, input signals and output signals (hereinafter, input data pulses and output data pulses). The black mark is a normal pulse representing logic “1”, and the hatched mark is a regular pulse representing logic “0”. The white mark is a dummy pulse for a don't care acknowledgment response. The triangle mark to the left is an acknowledge line pulse, that is, an acknowledge signal (hereinafter, an input acknowledge pulse and an output acknowledge pulse). Black marks are data reception response pulses of logic “1”, and hatched marks are data reception response pulses of logic “0”. The white mark is a don't care notification pulse.

  In these figures, it is assumed that it takes 1 unit time for the pulse to leave the sending processing unit and reach the receiving processing unit, and it takes 1 unit time for the processing unit to receive the pulse and take action. ing. Further, it is assumed that the processing unit can perform actions for all pulses in one unit time when a plurality of pulses are received simultaneously. Further, regarding the handshake backflow function, each processing unit assumes that the don't care process is given priority when the data pulse of the input signal and the acknowledge signal from the output side of the don't care notification are received simultaneously.

  Based on these assumptions, FIG. 20A to FIG. 22D will be described. 20A to 22D show state transitions per unit time. First, at time t1 in FIG. 20A, data pulses (1, 0, 1) are generated at the inputs (X1, X2, X3). At time t2 in FIG. 20B, these pulses arrive at the signal branch processing unit. At time t3 in FIG. 20 (c), the signal branching processing unit takes action to generate an input acknowledge pulse and an output data pulse. At time t4 in FIG. 20D, the input acknowledge pulse of the signal branch processing unit arrives at the input signal generation source. At the same time, the output data pulse of the signal branch processing unit arrives at the receiving processing unit. At time t5 in FIG. 20 (e), the PU 10c generates a don't care notification pulse and causes it to flow backward.

  At time t6 in FIG. 21A, a don't care notification pulse arrives at PU 10d, and at time t7 in FIG. 21B, PU 10d further reverses the don't care notification pulse. At time t8 in FIG. 21C, a handshake is established between the regular output data pulse and the don't care notification pulse between the PUs 10d and 10e, and the backflow of the don't care notification stops. At time t9 in FIG. 21 (d), the PU 10f at the final stage outputs an output data pulse and generates a don't care notification pulse to make it flow backward.

  At time t10 in FIG. 22A, a handshake is established between the regular output data pulse and the don't care notification pulse between the PUs 10f and 10g. At time t12 in FIG. 22 (c), the handshake between the final stage PU 10f and the output signal receiving side is completed, and the output signal of this circuit is determined at time t13 in FIG. 22 (d). In the above, it is assumed that all the wiring delays are the same. However, even if the wiring delays are different for each wiring, the circuit is executed correctly, and even if the delays of the same wiring vary depending on the situation, the circuit is executed correctly. Further, although the values of the inputs (X1, X2, and X3) are fixed for explanation, a new calculation can be started by inputting a new value after time t5 when the input handshake is completed.

  FIG. 23 shows an example of a sequential circuit with flip-flops. Specifically, FIG. 23 shows a 3-bit counter described in a normal synchronous design description. The circuit of FIG. 24 is obtained by converting the counter of FIG. 23 into a configuration including a two-input logic element, a NOT gate element, a signal branching element, and a flip-flop FF. Therefore, the circuit of FIG. 24 can be implemented in the system 1 including the self-synchronous PU 10 having two inputs and one output. In the circuit diagram of FIG. 24, it is the same as described above that one wiring represents a pair of a data line and an acknowledge line.

  25 (a) to 31 (d) (FIGS. 25 (a) to (d), FIGS. 26 (a) to (d), FIGS. 27 (a) to (d), and FIGS. 28 (a) to (d). ), FIGS. 29 (a) to (d), FIGS. 30 (a) to (d), and FIGS. 31 (a) to (d)), the circuit shown in FIG. The state executed using is shown. Fig.25 (a)-FIG.31 (d) have shown the state transition for every unit time. It should be noted that the counter circuit is not executed once, but is repeatedly executed. Therefore, the movement of the circuit is shown by the data pulse, the acknowledge pulse, and the don't care notification pulse. Also, the square representing the flip-flop indicates what cycle value of the user clock the flip-flop holds.

  The initial value 0 is output from the three flip-flops at time T1 shown in FIG. They reach the processing unit that receives the output signal at time T4 shown in FIG. At time T8 shown in FIG. 26 (d), a pulse arrives at the data input of the output Z1 flip-flop (counter LSB). At time T9 shown in FIG. 27A, only the flip-flop of output Z1 proceeds to the processing of user clock cycle 1.

  At time T11 shown in FIG. 27C, the flip-flop of the output Z2 is updated to the process of the user clock cycle 1. At time T15 shown in FIG. 28C, the flip-flop (counter MSB) of the output Z3 is updated to the processing of the user clock cycle 1. Meanwhile, the processing of the user clock cycle 1 proceeds in the processing unit of the NOT gate around the flip-flop of the output Z1. For this reason, at time T17 shown in FIG. 29A, the flip-flop of the output Z1 proceeds to the processing of the user clock cycle 2.

  At time T19 shown in FIG. 29C, the flip-flop of the output Z2 proceeds to the processing of the user clock cycle 2. The processing delay of the output Z2 flip-flop is small compared to the processing of the output Z1 flip-flop, but the processing delay of the output Z3 flip-flop is large. For this reason, at time T25 shown in FIG. 31A, the flip-flop of the output Z1 proceeds to the processing of the user clock cycle 3 in advance. In contrast, at time T27 shown in FIG. 31 (c), the flip-flop of the output Z3 finally proceeds to the processing of the user clock cycle 2. At time T27, the flip-flop of output Z2 proceeds to the processing of user clock cycle 3. For this reason, the flip-flop of the output Z3 is delayed by one turn with respect to the flip-flop of the output Z2 (a delay of one turn or more with respect to the flip-flop of the output Z1).

  As described above, in the circuit of the 3-bit counter mounted in the asynchronous system 1, the processing of the output Z1 flip-flop and the output Z2 flip-flop proceeds more rapidly than the output Z3 flip-flop. However, the difference does not grow indefinitely. When the difference in the processing of these flip-flops spreads to a certain extent, the signal branch processing unit (PUs 10h and 10i in FIG. 24) that connects the circuits related to the flip-flops of the outputs Z1 and Z2 and the flip-flop of the output Z3. ) Will not return an acknowledge pulse. For this reason, the flip-flop related circuits of the outputs Z1 and Z2 cannot proceed further. Therefore, after that, every time the flip-flop of the output Z3 advances by one cycle, the PU10h and 10i of the signal branch return an acknowledge pulse once, and the flip-flops of the outputs Z1 and Z2 process one cycle at a time accordingly. To proceed. By storing more than one event token in the memory 14 that queues the event tokens of the processing unit, it is possible to increase the limit that the flip-flops of the outputs Z1 and Z2 advance processing.

  In the operation of the self-synchronous system shown in FIGS. 25 (a) to 31 (d), the don't care notification pulse at time T7 shown in FIG. 26 (c), time T9 shown in FIG. 27 (a), etc. It can be seen that the handshake backflow function is effectively utilized. In particular, the don't care notification pulse generated by the PU 10j of the 2-input AND at time T19 in FIG. 29C is propagated as the input don't care notification pulse of the PU 10k of the 2-input AND at time T21 in FIG. From these figures, it can be seen that the handshake processing for executing the multi-stage logic flows backward from the output stage to the input stage. This handshake backflow function shortens the execution time of the entire multistage logic and improves the system performance.

  In the operation of the counter circuit shown in FIGS. 25 (a) to 31 (d), the three flip-flops moved at different timings because of the difference in the complexity of the logic for calculating the next value of each flip-flop. The main factor is that. In addition, there is a factor that the processing unit on the receiving side of the output signal of each flip-flop is handshaking each output signal at a different timing. The processing unit that receives the output signal may be configured to “not return an acknowledge until all three signals are ready”. With such a configuration, the signal branch processing unit immediately after the three flip-flops does not operate at different timings, and the processing of the three flip-flops does not proceed at different timings as described above.

  The same applies to input signals for a self-synchronous system. In the example of the counter circuit shown in FIGS. 23 and 24, there is no “input signal for the entire system”. If there are input signals for the entire system, the flip-flops in the system will not operate at an unlimited number of times as long as these input signals are handshaked synchronously. The difference falls to some extent. If the handshake of the input / output signal of the system 1 is stopped by using such an operation, the output of the output signal that cannot be output to a certain extent, that is, an amount that does not depend on the input signal that is no longer coming. Stall after proceeding until the process stops. Thereafter, when the handshake of the input / output signal of the system 1 is resumed, the system 1 resumes the processing from the next.

  As described above, in the synchronous circuit, the processing corresponding to stopping and restarting the global clock is partially configured in the system 1 or the system 1 in the self-synchronous system 1 in which no global clock exists. This can be realized by stopping or restarting the handshake of the input / output signal of the selected circuit. Therefore, in the self-synchronous system 1, the data flow implemented in the system 1 can be changed by temporarily stopping the data flow processing and changing the logic of the processing unit or changing the connection of the processing unit. Dynamic reconfiguration is possible.

  Further, in this system 1, the data lines and acknowledge lines that make up the routing matrix 5 to which the PU 10 is connected perform pulse transmission only once during the process corresponding to one cycle of the original synchronous circuit. Therefore, when the original synchronous circuit is normally mounted in a synchronous manner or when the self-synchronous circuit is mounted by a two-wire self-synchronous design method, a large amount of spikes are caused by imbalance of element delay and wiring delay. It is also possible to suppress the occurrence of power and power consumption.

  Thus, according to one embodiment of the present invention, circuit elements such as an AND gate, an OR gate, a NOT gate, and a flip-flop used in the synchronous design are mounted in a self-timed manner that does not require a global clock. For each signal of the synchronous user circuit, two signals of the data line and the acknowledge line are assigned in the self-timed element, and the data line uses two power sources, a positive power source and a negative power source. In the data line, one positive pulse represents a logic “1” for one clock cycle, and one negative pulse represents a logic “0” for one clock cycle. In the acknowledge line, one pulse represents an acknowledge for one clock cycle.

  A two-wire self-timed element using one power source transmits an output signal only when the output value must be changed. The one-wire self-timed device according to one aspect of the present invention changes the output value--regardless of whether or not, the output signal is transmitted once per one user clock cycle. This reflects the property of the synchronous user circuit that “all signal lines transmit a value once per clock cycle”. Therefore, in the circuit system constructed by combining the self-timed elements according to one aspect of the present invention, one cycle of the user clock of the synchronous user circuit is performed each time handshaking is performed once for all the data lines / acknowledge lines. It can be considered that the processing of minutes proceeds.

  Furthermore, handshaking usually involves a procedure in which a signal transmitting element first issues a data pulse to the signal receiving element, and the receiving element that receives the data pulse returns an acknowledge pulse to the transmitting element. Take. However, when the receiving side element is a multi-input element, the value of the signal of interest may be don't care depending on the value of other input signals. In that case, the receiving side element first issues an acknowledge pulse (meaning don't care notification) to the sending side element, and the sending side element receiving it sends an arbitrary data pulse (meaning don't care acknowledgment response). By returning, it is considered as one handshake.

  Each element not only sends a don't care notification to another input when the other input becomes don't care due to an input, but also an input signal when the don't care notification of the output signal comes before the input signal comes Send a don't care notification pulse. As a result, when executing multi-stage logic, not only a simple handshake in which values are determined one after another from the input stage to the output stage, but also as described above, one after another from the output stage to the input stage. A backflow handshake (handshake backflow function) in which don't care propagates occurs.

  According to an embodiment of the present invention, a clock synchronous circuit can be mounted without using a global clock, and therefore, the number of steps for clock skew adjustment and critical path adjustment can be omitted as compared with conventional clock synchronous mounting. Furthermore, compared with the two-wire self-timed design and mounting method, there is an effect that the circuit can be designed based on the concept of the synchronous design widely spread. When evaluating a multi-stage combinational logic circuit, not only is a handshake called “Data → Acknowledge” from the input stage to the output stage, but also “Don't Care Notification → Don't Care Acknowledgment” from the output stage to the input stage. The handshake “response” can be reversed. For this reason, the handshake overhead problem which was a weak point of the conventional self-timed design and implementation method is also reduced. Furthermore, since transmission is performed only once on each signal line within one logical clock cycle, a large amount of spikes are generated due to variations in element delays as in conventional clock synchronous mounting and self-timed design mounting. Therefore, it is possible to suppress the situation where power is consumed.

  In the above description, the internal operation of the self-synchronous PU 10 is shown in the form of a flowchart, but it can also be described by other notations such as a state transition diagram and a production rule. In addition, the system 1 having a general-purpose self-synchronous PU 10 has been described above. On the other hand, a self-synchronizing circuit having a handshake backflow function can be configured by combining a self-synchronizing processing unit or a self-synchronizing element having a dedicated logic. Furthermore, the self-synchronous processing unit or element may not be connected by wiring, and self-synchronous mounting can be realized by transmitting an electric signal or an optical signal by radio or wire. Self-synchronous systems can overcome the effects of wiring delay and device delay imbalance, and can be used in distributed large-scale systems in which multiple systems or processing units are connected by computer work such as the Internet. The above configuration can also be applied to this.

Claims (28)

A system having a plurality of self-synchronous processing units,
One processing unit of the plurality of processing units is
An input-side signal exchange unit for receiving a plurality of input signals respectively supplied from a plurality of input-side processing units;
A logic unit for generating an output signal based on the plurality of input signals;
An output side signal exchange for transmitting the output signal to at least one output side processing unit;
A first determination function that determines an unreceived input signal that is unnecessary for generating an output signal based on an input signal received by the signal exchange unit on the input side;
A second determination function for determining an unreceived input signal that is not required to be received by a use notification indicating that the output signal is not received, received by the signal exchange unit on the output side, and
The signal exchange unit on the input side transmits the waste notification to an input side processing unit that supplies an unreceived input signal that is judged not to be received by the first determination function or the second determination function. System. In Claim 1, the signal exchange unit on the output side transmits an output signal to a plurality of processing units on the output side,
The system in which the second determination function determines an unreceived input signal that is not required to be received when the unnecessary notification is received from all of the plurality of output-side processing units. 2. The system according to claim 1, wherein the processing unit has a handshake function for confirming signal transfer by any one of the following processes a1 to a4.
When the a1 input signal is received, a confirmation signal is transmitted to the input processing unit of the input signal supply source.
a2 The confirmation signal is transmitted as the non-use notification to the processing unit on the input side of the supply source of the unreceived input signal, and the dummy input signal is received from the processing unit on the input side of the transmission destination of the confirmation signal To do.
a3 An output signal is transmitted, and the confirmation signal is received from an output-side processing unit to which the output signal is transmitted.
a4 When the confirmation signal is received when the output signal is not transmitted, it is recognized as the unnecessary notification and a dummy output signal is transmitted.   2. The system according to claim 1, wherein the output side signal exchange unit transmits the output signal as a pulse signal each time the output unit generates the output signal.   2. The system according to claim 1, wherein the output-side signal exchange unit transmits the output signal as a signal that is displaced into three states.   6. The system according to claim 5, wherein the three states include a neutral state and two states that do not include the neutral state.   2. The system according to claim 1, wherein the processing unit further includes a memory for storing an input signal that cannot be processed by an unreceived input signal.   2. The system according to claim 1, wherein the processing unit further includes a memory for storing, as an event token, a signal that cannot be processed among received signals.   2. The system according to claim 1, wherein the logic unit has a function of changing logic for generating an output signal. In Claim 1, the signal exchange unit on the input side has a function of changing the processing unit on the input side,
The output-side signal exchange unit has a function of changing an output-side processing unit.   2. The system according to claim 1, further comprising a communication system that enables exchange of signals between the plurality of processing units, wherein the communication of the plurality of processing units can be reconfigured.   2. The system of claim 1, comprising an integrated circuit unit that includes the plurality of processing units and a routing matrix for transmitting signals between the plurality of processing units.   13. The system according to claim 12, wherein the routing matrix reconfigures circuits in the integrated circuit unit by changing connections between at least some of the processing units included in the plurality of processing units. A self-synchronous processing unit,
A signal exchange unit on the input side for receiving a plurality of input signals respectively supplied from other processing units on the plurality of input sides;
A logic unit for generating an output signal based on the plurality of input signals;
An output side signal exchange for transmitting the output signal to at least one other processing unit on the output side;
A first determination function that determines an unreceived input signal that is unnecessary for generating an output signal based on an input signal received by the signal exchange unit on the input side;
A second determination function for determining an unreceived input signal that is not required to be received by a use notification indicating that the output signal is not received, received by the signal exchange unit on the output side, and
The signal exchange unit on the input side sends the waste notification to another processing unit on the input side that supplies an unreceived input signal that is judged not to be received by the first determination function or the second determination function. Send the processing unit. In Claim 14, the signal exchange unit on the output side transmits an output signal to other processing units on the plurality of output sides,
The second determination function is a processing unit that determines an unreceived input signal that is not required to be received when the use notification is received from all of the other processing units on the output side. 15. The processing unit according to claim 14, further comprising a handshake function for confirming signal transfer by any one of the following processes b1 to b4.
When the b1 input signal is received, a confirmation signal is transmitted to another processing unit on the input side that is the source of the input signal.
b2 The confirmation signal is transmitted as the non-use notification to the other processing unit on the input side of the supply source of the unreceived input signal, and a dummy signal is transmitted from the other processing unit on the input side to which the confirmation signal is transmitted. Receive the input signal.
b3 An output signal is transmitted, and the confirmation signal is received from another processing unit on the output side of the transmission destination of the output signal.
b4 When the confirmation signal is received when the output signal is not transmitted, it is recognized as the unnecessary notification and a dummy output signal is transmitted.   15. The processing unit according to claim 14, further comprising a memory for storing an input signal that cannot be processed by an unreceived input signal.   15. The processing unit according to claim 14, further comprising a memory for storing, as an event token, a signal that cannot be processed among received signals. A self-synchronous processing unit,
A signal exchange unit on the input side for receiving an input signal from another processing unit on the input side;
An output side signal exchange unit for transmitting the input signal to at least one other processing unit on the output side;
The signal exchange unit on the input side transmits a waste notification to another processing unit on the input side that supplies an unreceived input signal based on the waste notification of the output signal received by the signal exchange unit on the output side. Processing unit. A plurality of processing units comprising at least one processing unit according to claim 14;
And a routing matrix for transmitting signals between the plurality of processing units.   21. The integrated circuit unit according to claim 20, wherein the plurality of processing units further include at least one processing unit according to claim 19.   21. The integrated circuit unit according to claim 20, wherein the routing matrix reconfigures a circuit in the integrated circuit unit by changing a connection between at least some of the processing units included in the plurality of processing units. A plurality of processing units, each processing unit is a processing unit according to claim 19,
An integrated circuit unit further comprising a routing matrix for transmitting signals between the plurality of processing units. A method for controlling a system having a plurality of self-synchronous processing units comprising:
One processing unit of the plurality of processing units includes an input-side signal exchange unit for receiving a plurality of input signals respectively supplied from a plurality of input-side processing units, and an output based on the plurality of input signals A logic unit for generating a signal; and an output side signal exchange unit for transmitting the output signal to at least one output side processing unit;
The method is
The first factor that an unreceived input signal that is unnecessary for generation of an output signal is generated by the input signal received by the input-side signal exchange unit, or the output signal received by the output-side signal exchange unit Due to a second factor that causes an unreceived input signal that is not required to be received due to a waste notification indicating that the signal is not used, the waste notification is transmitted to the processing unit on the input side that is scheduled to supply the input signal. Including methods.   25. The method of claim 24, further comprising transmitting the output signal as a pulse signal each time the output signal is generated by the logic unit. 25. The method of claim 24, comprising confirming transfer of signals between the plurality of processing units, wherein confirming transfer of the signals includes:
When an input signal is received, a confirmation signal is transmitted to the processing unit on the input side of the input signal supplier.
The confirmation signal is transmitted as the non-use notification to the processing unit on the input side of the supply source of the unreceived input signal, and the dummy input signal is received from the processing unit on the input side of the transmission destination of the confirmation signal. ,
Transmitting the output signal, receiving the confirmation signal from the processing unit on the output side of the output signal destination;
When the confirmation signal is received when the output signal is not transmitted, it is recognized as the unnecessary notification and a dummy output signal is transmitted. A method for communicating a signal, comprising: a self-synchronous processing unit confirming the transfer of a signal to another self-synchronous processing unit,
The self-synchronous processing unit includes an input-side signal exchange unit for receiving a plurality of input signals respectively supplied from a plurality of other input-side other processing units, and an output signal based on the plurality of input signals. A logic unit for generating the output signal, and an output-side signal exchange unit for transmitting the output signal to at least one other processing unit on the output side,
Confirming the transfer of the signal includes:
When an input signal is received by the signal exchange unit on the input side, a confirmation signal is transmitted to another processing unit on the input side of the input signal supply source,
Unnecessary reception due to a first factor that an unreceived input signal that is not necessary for generating an output signal is generated by the input signal, or a notification that indicates that the output signal is not received, which is received by the signal exchange unit on the output side. The confirmation signal is transmitted as the non-use notification to the other processing unit on the input side of the supply source of the unreceived input signal due to the second factor that causes the unreceived input signal to be Receiving a dummy input signal from another processing unit on the input side of the signal transmission destination;
Transmitting an output signal and receiving the confirmation signal from another processing unit on the output side of the transmission destination of the output signal;
If the confirmation signal is received when the output signal is not yet transmitted, the confirmation signal is recognized as the unnecessary notification, and a dummy output signal is transmitted.   28. The method of claim 27, comprising transmitting the output signal as a pulse signal each time the output signal is generated by the logic unit.

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