JP2000187641A - Information transmitting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inter-controller information transmitting circuit simple in circuit configuration and without imposing any weight on a controller. SOLUTION: A register 2 and a latch 3 are provided between processors A and B for transmitting information. When a writing timing from the processor A to a register 2 competes with a reading timing from the processor B, a latch timing control circuit 4 holds the output of the latch 3 so that any illegal data can be prevented from being read by the processor B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information transmission circuit for transmitting necessary information from a control unit of one subsystem to a control unit of another subsystem in a system including a plurality of subsystems.

[0002]

2. Description of the Related Art In recent years, control of electronic devices and systems is mostly performed using a control device such as a microprocessor. However, as electronic devices become more complicated, control becomes more complicated, and a plurality of controls are provided in one device. It is not uncommon to have a microprocessor. In this case, the processors may operate completely independently of each other, but generally, the processors in the apparatus perform control in cooperation with each other. In this case, it is necessary to transmit various setting information of each subsystem constituting the system and the apparatus, status information of each processor, and commands for operating the processors in cooperation with each other.
In addition, the necessity of this information transmission is not limited to the case of a general-purpose microprocessor, but similarly holds between control circuits independently configured by hardware logic, but in the following description,
A case in which a general-purpose processor that operates and controls based on software is used will be described.

It is not impossible for the information transmission between the processors to directly control the communication by the processors to transmit the information. In this case, however, the processing capability of the processor is considerably devoted to the communication between the processors. Control processing cannot be performed. Therefore, normally, a communication control circuit and a communication buffer memory are provided as shown in FIG. 7 to reduce the load on the processor.

FIG. 7 shows an example of an information transmission circuit for transmitting information from the processor A to the processor B. A buffer memory 101 and a communication control circuit 102 are provided in both the processor A on the data transmission side and the processor B on the reception side. The data is transmitted between the communication control circuit A and the communication control circuit B by serial transfer or the like.

When transmitting data from the processor A to the processor B, first, the processor A
Write data to 1A. The communication control circuit 102A
Sequentially sends the serial data to the communication control circuit 102B. The communication control circuit 102B is a communication control circuit 102A.
Is temporarily stored in the buffer memory 101B. Then, the processor B reads the data in the buffer memory 101B, whereby the processor A
From the processor to the processor B.

However, in the case where the buffer memory 101 is provided, the capacity of the buffer memory 101 is limited, so that the processor B must read the received data before the buffer memory 101 overflows. Therefore, for example, a method is generally used in which the control circuit 102B notifies the processor B that new data has been written to the buffer memory 101B as an interrupt signal, and the processor B reads data from the buffer memory 101B as interrupt processing.

As another method of information transmission, as shown in FIG.
There is a configuration in which a dual-port memory readable and writable from both sides B or a register 103 that can be written from the processor A and read from the processor B is provided. In the case of this configuration, when the writing from the processor A and the reading from the processor B are almost simultaneously performed, the reading is performed at the time when the data of the dual port memory or the register 103 is changing due to the writing. Reads incorrect data. Therefore processor A
In the case where the processor B performs a read after the start of writing, the access timing control circuit 104 issues a wait signal to the processor B. As a result, the read cycle of the processor B is extended, and after the write by the processor A is completed, the read by the processor B is performed. Conversely, if the processor A attempts to write while the processor B is reading, the access timing control circuit 104 issues a wait signal to the processor A so that the processor A performs the writing operation after the reading of the processor B is completed. I have to.

[0008]

These conventional information transmission circuits have the following problems.

First, in the case of the configuration shown in FIG. 7, a buffer memory 101 and a communication control circuit 102 are required for communication, and the circuit scale becomes large. In addition, it is necessary that processors that perform communication operate in synchronization to some extent using an interrupt or the like. Therefore, if an interrupt required for controlling the device other than the interrupt by communication is set separately, the processor needs to process a plurality of interrupts,
The software configuration becomes complicated.

In the case where the dual port memory or the register 103 shown in FIG. 8 is provided and the access timing of one processor is waited for simultaneous access of writing by the processor A and reading by the processor B, a necessary circuit scale is required. Is often smaller than the configuration of FIG. 7, but the usable processor is limited to the type that can give a wait to the access timing. How much weight should be applied depends on whether or not contention occurs at the time of access.However, depending on the processor, only a predetermined number of clocks can be applied. Cannot be used.

The timing signal for controlling the wait is generally required to synchronize with the clock of the processor and satisfy a setup time and a hold time specified for each processor. However, in this case, it is necessary to generate wait signals at timings synchronized with both of the two processors operating with separate clocks, so that the configuration of the circuit for controlling the wait timing is complicated.

In view of the above problems, it is an object of the present invention to provide an information transmission circuit between control devices which has a simple circuit configuration and does not require weighting of the control devices.

[0013]

SUMMARY OF THE INVENTION An information transmission circuit according to the present invention is based on the premise that information is transmitted between a plurality of control devices. Data holding means and holding timing control means.

The first data holding means is writable from the first control device and outputs the written value.

The second data holding means receives the output of the first data holding means as an input, and changes the second control device based on the input or irrespective of the change of the input. Hold and output.

The holding timing control means controls the hold of the output of the second data holding means and the release thereof. The control by the holding timing control means is performed, for example, for a period equal to or longer than the period from when the writing from the first control device and the reading from the second control device are both requested to when the request for the reading is canceled. , And the second data holding means holds the output.

Further, according to the present invention, there is provided a third data holding means which is writable from the second control device and outputs the written value, and an output of the third data holding means is provided as an input. A fourth data holding means for changing the first control device based on the input or holding and outputting the data irrespective of the change of the input, wherein the holding timing control means comprises: It is also possible to configure so as to control the hold of the output of the fourth data holding means and the release thereof.

According to the present invention, even when the first control device is writing data to the first data holding means, the output held by the second data holding means is given to the second control device. Therefore, the second control device does not read illegal information.

[0019]

FIG. 1 is a block diagram of an information transmission circuit according to an embodiment of the present invention.

In the circuit of FIG. 1, a latch 3 and a latch timing control circuit 4 for controlling the latch 3 are added after the register 2 to the circuit configuration using the register of FIG. There is no access timing control circuit 104 that waits for and controls access timing. FIG. 1 shows the decoder 1, the decoder 6, and the tri-state buffer 5, which are not shown in FIG. 8, but these are omitted in FIG. 8 and FIG. 7 as well as FIG.

When transmitting data from the processor A to the processor B, the processor A writes the transmission data to a specific address set for data transfer to the processor B. The address signal and the write signal of the processor A are decoded by the decoder 1, and as a result, if the address specified by the processor A is the specific address, the write signal is set to the register write signal / WR to the register 2
Output to

Write signal / WR from processor A
Is a control signal of negative logic, and a portion where the signal rises from the L level to the H level (hereinafter, referred to as a rising edge) indicates a data write timing. Register 2
Captures data from the data bus of processor A based on the edge timing of the / WR signal. Note that "/" added before the write signal WR and a read signal RD described later.
Indicates that the signal is negative logic.

When receiving the data from the processor A, the processor B reads the transmission data from the specific address set for receiving the data from the processor A. The address signal and the read signal of the processor B are decoded by the decoder 6. If the address specified by the processor B is the specific address, the read signal is output to the latch timing control circuit 4 and the tri-state buffer 5 as a register read signal / RD. . The tristate buffer 5 transmits the output of the latch 3 to the data bus of the processor B when the / RD signal is at the L level, and enters a high impedance state when the / RD signal is at the H level. The latch timing control circuit 4 generates a latch control signal based on the register read signal / RD,
The output control of the latch 3 is controlled so that the data is taken into the processor at the timing of the rising edge of the read signal / RD.

The writing from the processor A to the register 2 is a normal writing, and the writing to the register 2 is normally performed regardless of the presence or absence of the read request from the processor B. However, when the output of the register 2 is directly read by the processor B, the rising timing of the write signal and the rising timing of the read signal happen to occur, that is, the timing of the data writing by the processor A and the timing of the data reading by the processor B almost coincide. If so, the processor B may not be able to read the data correctly. Therefore, a latch 3 is provided at the subsequent stage of the register 2, and before and after the rising of the read signal / RD, that is, at the time of reading data by the processor B, holds the output so that the output data to the processor B does not change even if the data is written by the processor A. are doing.

A circuit for generating a control signal for controlling the latch 3 is a latch timing control circuit 4 in FIG. FIG. 2 shows a configuration example of the latch timing control circuit 4.

The latch timing control circuit 4 monitors the write signal / WR from the processor A and the read signal / RD from the processor B, that is, the competition between the writing by the processor A and the reading by the processor B.

The logical product 11 is obtained between the write signal / WR and the read signal / RD. When both / WR and / RD are at L level, that is, enabled, the set input S of the SR flip-flop 14 becomes H level. , SR flip-flop 14 are set. As a result, the output Q becomes H level, which is inverted by the logic inversion gate 15, and the L level is output as the latch control signal. Latch 3
Holds output data irrespective of a change in the input data when the latch control signal is at the L level. The output of the latch 3 is held until the processor B completes the fetching of the data and raises / RD, so that the processor B does not fetch the changing output data of the register 2 by the writing by the processor A.

Also, immediately after the rise of the / RD signal, the output data of the latch 3 must not change during the data hold time during which the processor B is reading data.
Therefore, the / RD signal and the delay circuit 13
The logical AND 12 of the signals after a certain time delay has been added, and this is applied to the reset input R of the SR flip-flop 14. As a result, after a lapse of the delay time by the delay circuit 13 from the rise of the / RD signal, the SR flip-flop 14 is reset, the latch control signal becomes H level, and the hold of the latch 3 is released. This allows
After a delay time from the rise of the / RD signal, the latch 3 outputs the input data as it is. The delay added to the / RD signal by the delay circuit 13 only needs to guarantee the data hold time of the processor B, and an accurate delay time is not required. Therefore, the delay circuit 13 inserts an even number of logical inversion gates, for example. Can be configured.

The register 2 shown in FIG. 1 is constructed by collecting D-type flip-flop circuits for the data bus width of the processor A, for example, 8 bits.
A data bus, a clock signal, and a write signal / WR to this register are connected as inputs to the processor A.

The write signal / WR is a signal of negative logic output from the result of decoding the address signal and the write signal of the processor A, and indicates that the processor A has issued a request to write the transmission data to the processor B. Writing to the register 2 is performed at the edge timing of the / WR signal. Input data from the processor A is taken into the register 2 based on the rising edge timing at which the / WR signal rises from the L level to the H level. , Which is output data of the register 2.

FIG. 3A shows the operation timing of the input / output signal of the register 2. Since the output value of the register 2 is determined by the rising edge of the clock, before and after the rising edge to determine the input value, a time zone in which the input data value must not be changed is defined as a setup time and a hold time. . Further, the output data changes within the output data within the output delay time from the rising edge of the clock and is determined.

The latch 3 at the subsequent stage of the register 2
Is constructed by collecting so-called D-type transparent latches for the data bus width. When the H level (disable) is input as the latch control signal, the latch 3 transmits and outputs the input data from the register 2 with a specific delay, but the latch control signal changes to the L level (enable). Then, even if the input data changes, the output value does not change and is held and output.

FIG. 3B shows the operation timing of the latch. In FIG. 3B, since the latch 3 determines the output data to be held by the falling edge of the control signal,
Before and after the falling edge are defined as a time zone in which the input data value must not be changed as a setup time and a hold time. When the control signal is at the H level, the output data changes within a specific delay time after the input data changes.

As described above, the circuit of FIG. 1 latches the latch 3 from the time when the write signal / WR from the processor A and the read signal / RD from the processor B are both enabled to the time when the reading by the processor B is completed. Will be held. The operation timing of each signal at this time will be described with reference to FIG. Although the period during which the / WR signal and the / RD signal are enabled has substantially the same length in the same figure, there is no problem if one is short and the other is long.

In FIG. 4, first, when the enable timing of the / WR signal and the / RD signal (the rising edge of each signal) is sufficiently separated, the latch 3 is switched from the register 2 as shown in FIG. And the processor B can read the data of the register 2 normally at the timing of the rising edge of the / RD signal.

In the case of FIG. 4B, the / RD signal is / WR
In this case, there is a period in which the signal is at the L level, that is, an enable state, and the output is held by the latch 3 so that the output before and after the rising edge of the / RD signal does not change. I can put it out. FIG. 4C shows a case where the / RD signal precedes the / WR signal but there is no period in which both are enabled. In this case, the data is not held by the latch 3 but the processor B reads the data without any problem. I can do it.

FIG. 4D shows a case where the / WR signal precedes the / RD signal and there is a period in which both are enabled. In this case, since the register 2 is rewritten at the timing of the rising edge of the / WR signal, without the latch 3, the data of the register 2 being changed is read by the processor B and cannot be read normally. However, in this embodiment, since the latch 3 holds the output data until the reading by the processor B is completed, the processor B can perform the normal reading. FIG. 4E shows a case where the / WR signal precedes the / RD signal but there is no period during which both are enabled. In this case, since neither the / WR signal nor the / RD signal is enabled, the latch is not held, and the processor B can normally read data at the rising timing of the / RD signal. FIG. 4
As shown in (e), immediately after the / WR signal rises, / R
When the D signal falls and when the control of holding the output of the latch 3 is performed only by the / RD signal, the output data of the register 2 being changed by the writing by the processor A is held as the output of the latch 3. Processor B cannot read normal data. Therefore, the latch timing control circuit 4 of the present embodiment outputs the / WR signal and the / RD signal.
The timing of holding the latch 3 is controlled based on a change in both signals.

As described above, in the information transmission circuit according to the present embodiment, the latch timing control circuit 4 controls the hold of the latch 3, so that the write timing from the processor A and the read timing from the processor B compete with each other. Even in such a case, there is no possibility of reading incorrect data.

Although the configuration of FIG. 1 has been described as including one register, the number of registers and latches can be increased according to the amount of data to be transmitted.

FIG. 5 shows a configuration in which two sets of registers 22 and latches 23 are provided. In the case of the configuration of FIG. 5, the processors A and B are, for example, registers 22-1 and 22-2 for two different parameters, respectively.
, And these registers 22 are selected by addressing to write or read data.

In the configuration shown in FIG. 5, the processor A and the processor B transmit the register 22-1 or 22-2 by the register write signal / WR and the register read signal / RD.
-2, it is sufficient to control so as to hold both outputs of the latches 23-1 and 23-2 when one of them is accessed. Therefore, one latch timing control circuit 24 is provided. And 26, a signal obtained by taking a logical sum 27, 28 of the decoding results from registers 26 and 26 may be input as a register write signal / WR and a register read signal / RD.

As described above, when the number of registers and latches is increased, the amount of data to be transmitted can be increased.

Also, in an actual system, the control device is clearly divided into a master side and a slave side, and it is often sufficient to be able to transmit information in one direction. The description has been made in consideration of only one-way information data transmission. However, the present invention can cope with a case where bidirectional data exchange is required. In order to realize this bidirectionality, a circuit for transmitting information from the processor A to B and a circuit for transmitting information from the processor B to A may be provided with two transmission paths. FIG. 6 shows an example of an information transmission circuit that realizes bidirectional information transmission having these two transmission circuits.

In this configuration, when sending data to the processor B, the processor A writes the transmission data by addressing the register 32-1. When data is received from the processor B, the data is read by specifying the address of the register 32-2. When the processor B sends data to the processor A, the register 32-
Address 2 Latch timing control circuit 34
Holds the output of the latch 33-1 or 33-2 when the access from the processors A and B to the same register conflicts.

As described above, when two transmission circuits are configured, bidirectional information transmission can be performed.

[0046]

As described above, according to the present invention, information can be transmitted with a simple circuit configuration. Further, information can be transmitted between control devices that cannot set the weight and control devices that operate asynchronously.

In each control device, there is no need to use an interrupt for information transmission. Therefore, information transmission between control devices can be performed with a simple software configuration.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an information transmission circuit between control devices in the present embodiment.

FIG. 2 is a diagram illustrating a configuration example of a latch timing control circuit;

3A is a diagram illustrating an operation timing of a register, and FIG. 3B is a diagram illustrating an operation timing of an input / output signal of a latch.

FIG. 4 is a diagram showing operation timings at the time of reading and writing data in the embodiment.

FIG. 5 is a configuration example when two sets of registers and latches are provided.

FIG. 6 is an example of an information transmission circuit when bidirectional information transmission is realized.

FIG. 7 is a configuration example of an information transmission circuit between conventional control devices.

FIG. 8 is another example of the configuration of a conventional information transmission circuit between control devices.

[Explanation of symbols]

 1, 6, 21, 26, 31, 36 decoder 2, 22, 32 register 3, 23, 33 latch 4, 24, 34 latch timing control circuit 5, 25, 35 tri-state buffer

Claims (3)

[Claims] An information transmission circuit for transmitting information between a plurality of control devices, a first data holding unit that is writable from a first control device and outputs the written value; A second data holding unit that receives an output of the first data holding unit as an input, and changes the data based on the input or holds and outputs the data regardless of a change in the input to a second control device; An information transmission circuit, comprising: a holding timing control unit that controls hold of an output of the second data holding unit and control of release thereof. 2. The holding timing control means according to claim 1, wherein a period from when the writing from the first control device and the reading from the second control device are both requested to when the request for the reading is canceled is performed. The information transmission circuit according to claim 1, wherein the output is held by the second data holding means. 3. A third data holding means that is writable from the second control device and outputs the written value, and an output of the third data holding means is input to the first data holding means. A fourth data holding means for changing the input based on the input or holding and outputting the data irrespective of the change of the input, the holding timing control means comprising: 3. The information transmission circuit according to claim 1, further comprising controlling the hold of the output of the data holding means and the release thereof.