JP2000029822A - Bridge device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bridge device capable of suppressing overhead at the time of data transfer even when a target side bus is not in a free state and improving bus application efficiency and burst transfer length. SOLUTION: The bridge device 100 is provided with data buses 110, 120 for temporarily storing transfer data, control parts 130, 140 for controlling the transmission/reception of data related to the data buses 110, 120, latency timer registers 150, 151 for storing maximum clock time capable of occupying each bus by one data transfer, an arbitration part 180 for arbitrating the using right of a transfer source bus, and a prediction part 160 consisting of a counter 161 for counting the number of clocks up to timing that the transferred bus becomes in a free state, a regulated value register 162 for storing a regulated value indicating the buffer capacity of the data buses 110, 120, a comparing part 163 for comparing the value of the counter 161 with the regulated value, and a bus state detection part 164 for monitoring whether the transferred bus is in a free state or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bridge device for connecting buses in a computer system having a plurality of buses.

[0002]

2. Description of the Related Art In recent computer systems, particularly personal computers and workstations, functions,
Many peripheral devices are connected to one CPU in order to improve both performances. In this case, devices such as a CPU and peripheral devices are connected by a common signal path called a bus.

[0003] Usually, an unlimited number of devices can be connected to a bus in a computer system, and the number of devices is limited by electrical load and stability. For example, in the case of a PCI (Peripheral Component Interconnect) bus, the limit is about 10 buses.

[0004] However, there may be a case where a device exceeding the above limit must be connected. In such a case,
As a method for connecting more devices, there is a method using a “bridge device”. This is a method in which a “bridge device” is arranged between two buses, and is used as an intermediary for data transfer between devices connected to both buses while utilizing a buffer provided inside. is there. By using this "bridge device", the electrical load is reduced, and stable data transfer becomes possible.

[0005] In the following, the "write operation" in the case of using a conventional bridge device will be mainly described, and the outline of the "read operation" will be added. FIG.
1 is a schematic block diagram of a computer system including a conventional bridge device 500. The system includes a primary PCI bus 510 and first and second devices 530 and 540 connected thereto, a secondary PCI bus 520 and third and fourth devices 550 and 560 connected thereto,
The bridge device 500 includes an arbitration unit 570 for arbitrating the right to use the primary PCI bus and an arbitration unit 580 for arbitrating the right to use the secondary PCI bus.

Here, "arbitrating the right to use the bus" means that the arbitration unit gives the right to use the bus temporarily and the right to use to which device based on a certain rule. It means to decide. Specifically, the following processing is performed. For example, the arbitration unit 580
Receives a bus use right request signal (hereinafter, referred to as REQ) 551 asserted (driven to “L” level) by the third device 550, which is a signal to use the secondary PCI bus 520. , REQ from other devices
If the secondary PCI bus 520 is empty,
A bus use permission signal (hereinafter referred to as GNT) 552 for permitting the third device 550 to use the secondary PCI bus 520 is asserted. If the secondary PCI bus 520 is not idle, the arbitration unit 580 determines the priority based on a certain rule in consideration of the priority with other devices.
GNT to the third device 550 at appropriate timing
552 is asserted to grant the right to use the secondary PCI bus 520.

The other REQ 501 and GNT 502, REQ 541 and GNT 542, RE shown in FIG.
The signals of Q571 and GNT572 are the same bus request signal and bus permission signal as described above.

The bridge device 500 includes the arbitration unit 5 described above.
80 and an internal buffer for the "write operation" (FIG.
Is not shown. ). For example, DEC
In the case of the company 21152, a storage area of 22 double words (hereinafter, referred to as DW) including addresses and data is provided as an internal buffer for "write operation". Note that 1DW is data composed of 32 bits.

The first device 530 to the fourth device 56
Reference numeral 0 denotes an input / output device such as a hard disk. When these devices use the connected PCI bus, they transmit REQ to the arbitration unit 570 or 580, receive GNT from each arbitration unit, and acquire the bus use right.

The arbitration unit 570 includes a primary PCI bus 510
Arbitrate for the right to use. Control signals 511a-51
1d is a signal for controlling the use state of the primary PCI bus 510, and is a cycle frame signal (hereinafter, referred to as FRAME) indicating that the bus is being used by any device. 511a, master
Initiator that indicates that the device is ready to transfer data
A ready signal (hereinafter, referred to as IRDY) 511b, a target ready signal (hereinafter, referred to as TRDY) 51 indicating that the target device can transfer data.
1c, a stop request signal (hereinafter, referred to as a STOP) for requesting stop of a process currently being executed by the target device.
511d are four types of signals.

The control signals 521a to 521d are
A control signal for the CI bus 520, which is a primary PCI
FRAME 521a, IR similar to bus 510
These are four types of signals, DY521b, TRDY521c, and STOP521d.

Next, using the conventional bridge device 500, the master device connected to the secondary PCI bus 520 is used.
From the third device 550, which is a device, to the primary PCI
A “write operation” for writing 64 DW data to the first device 530, which is a target device connected to the bus 510, will be described with reference to FIGS. In this case, the secondary PCI bus 520 is the master bus, and the primary PCI bus 510 is the target bus.

FIG. 6 is a timing chart showing the appearance of each signal in the "write operation" when data can be transferred continuously because both the secondary PCI bus 520 and the primary PCI bus 510 are idle. It is a chart. In FIG. 6, "A / D 520" is a secondary PCI bus 520 that shares transmission and reception of addresses and data.
(The same applies hereinafter).

First, the third device 550 has a secondary P
REQ551 is asserted to use the CI bus 520 (CLK1). In contrast, the arbitration unit 580
Assert GNT552 (CLK2). Accordingly, the third device 550 obtains the right to use the secondary PCI bus 520. Thereafter, the third device 550 determines that the secondary PCI bus 520 is idle at the timing of the clock 3 by the FRAME 521a and the IRDY 52.
1b is confirmed by the fact that both are in the deasserted state ("H" level), and the FRAME 521a is asserted (CLK3). At the same time, the third device 550 is “(first
Transmission of “1 DW address indicating device) + (64 DW data)” is started (CLK4).

In this case, since the primary PCI bus 510 is in an idle state, the bridge device 500 transfers the “64 DW data” transmitted from the third device 550 to the internal buffer for the “write operation”. To the primary side PCI bus 510 (CLK5 to CLK68).
, And writing to the first device 530 is performed (CLK18 to CLK81).

As described above, when both the master-side bus and the target-side bus are idle, continuous data transfer is possible. In general, the maximum burst transfer length in the master device, that is, the maximum data length that can be transferred with one transfer of address information is about 64 DW.

FIG. 7 shows the "write operation"
The secondary PCI bus 520 is empty, but the primary P
6 is a timing chart showing the state of each signal when continuous data transfer cannot be performed because the CI bus 510 is not in an empty state.

FIG. 7 differs from FIG. 6 in that the primary PCI bus 510 is not in an idle state, so that the data temporarily captured by the bridge device 500 is stored in the first device 53.
0, and when the internal buffer for the “write operation” in the bridge device 500 is completely filled with data, the capture of the data transmitted from the third device 550 must be temporarily interrupted. It is.

In this case, the bridge device 500 asserts STOP 521d (CLK25) to notify the third device 550 to interrupt the write operation.
As a result, the third device 550 suspends the transmission of the data after the clock 26. Thereafter, the primary PCI bus 510 becomes empty at the timing of the clock 27, so that the bridge device 500 asserts the FRAME 511a (CLK28) and transfers all data stored in the buffer for the "write operation" to the first. The data is transmitted to one device 530 (CLK30 to CLK50).

Finally, the bridge device 500 resumes taking in the remaining 43 DW data from the third device 550 (CLK 54 to CLK 96), and in parallel with this, the first device
Data is transmitted to the device 530 (CLK55 to CLK55).
CLK 97). As described above, even when the master-side bus and the target-side bus are not simultaneously idle, data can be written through the bridge device.

Next, using the conventional bridge device 500, the second device 540
An outline of a “delayed read operation” for reading 4DW data will be described mainly focusing on differences from the “write operation”. In this case, the transfer direction of the read data is the same as in the case of the “write operation”, but the primary PCI bus 510 becomes the master bus and the secondary PCI bus 520 becomes the target bus.

Here, "delayed reading" will be described. When a master device connected to one master-side bus reads data from a target device connected to the other target-side bus, the bridge device acquires the right to use the target-side bus and transfers the data. On behalf of the read, the master device once relinquishes the right to use the master side bus. Thereafter, while the master device again attempts to acquire the right to use the master bus for the read, the bridge device returns to the target device.
Data read from the device is sequentially stored in an internal “delayed read” buffer. When the master device acquires the use right again, the master device sequentially receives the data transmitted from the bridge device. in this way,
The data read executed in two stages via the bridge device is called “delayed read”.

The difference between the “delayed read operation” and the “write operation” is that the master device transmits the “target device address” to the target device, and then transmits the read operation to the bridge device. Is a point of relinquishing the right to use the master side bus, except that the transfer direction of each data on the master side and the target side is reversed, and is basically the same as the “write operation”. is there.

As described above, the "delayed read operation"
Also, in the case where both the master side bus and the target side bus are empty, a continuous read operation from the target device to the master device becomes possible, even if the master side bus is not empty. As in the case of the “write operation”, the target
By performing the process of interrupting the data fetch from the device to the bridge device, the data can be read through the bridge device.

[0025]

However, according to the conventional bridge device described above, when the target side bus is not idle, the overhead in data transfer increases and the bus use efficiency decreases. There is a point. For example, in the case of the "write operation" as shown in FIG. 7, overhead occurs when the write operation is interrupted and resumed, and the bus use efficiency is reduced due to a period during which data transfer cannot be performed. . Also,
Since the "write operation" is interrupted as described above, the burst transfer length in this case is limited by the buffer capacity in the bridge device, and data transfer with the maximum burst transfer length cannot be performed.

On the other hand, in the read operation, for the same reason as in the write operation, the overhead increases and the bus use efficiency decreases. Therefore, the present invention has been made in view of the above problems, and a bridge device that suppresses data transfer overhead and improves bus use efficiency and burst transfer length even when a target-side bus is not idle. The purpose is to provide.

[0027]

In order to achieve the above object, a bridge device according to the present invention comprises a transmitting bus connected to a transmitting device having data to be transmitted, and a receiving device capable of receiving the data. A bridge device that is provided in a computer system having a receiving bus connected to a receiving device, captures the transmitted data on the transmitting bus into a buffer, and outputs the data to the receiving bus to transfer data. There is provided prediction means for predicting a timing at which the reception-side bus becomes empty, and permission means for permitting transmission to a transmission-side device that has requested data transfer based on the timing predicted by the prediction means.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a bridge device according to the present invention will be described with reference to the drawings. The first embodiment describes a “write operation” via a bridge device, and the second embodiment describes a “read operation” via a bridge device.

(First Embodiment) FIG. 1 is a schematic block diagram of a computer system 1 provided with a bridge device 100 according to a first embodiment of the present invention. For convenience, the “write operation” in the present embodiment is assumed to write 64 DW data from the third device 50 to the first device 30 via the bridge device 100.

The computer system 1 shown in FIG.
A bus 10, a secondary PCI bus 20, a first device 30,
Second device 40, third device 50, fourth device 6
0, an arbitration unit 70, and a bridge device 100. In addition, as shown in FIG.
Has an arbitration unit 180 that arbitrates the right to use the secondary PCI bus 20.

Here, "device" is a general term for various input / output devices constituting the computer system. In addition, "P
The “CI bus” is a general-purpose local bus that does not assume a specific CPU, and is based on a 32-bit bus width and realizes address transfer and data transfer in a time-division manner using the same 32 signal lines. I have. In this PCI bus, if the overhead such as address transmission is ignored, 1 DW data transfer can be performed in one clock period. In addition, PC
The I (Peripheral Component Interconnect) bus is described in detail in "PCI Local Bus Specification, Rev. 2.1" and the like.

The primary PCI bus 10 is one of the two PCI buses of the computer system 1, and connects the first device 30, the second device 40, the arbitration unit 70 and the bridge device 100. ing. The secondary PCI bus 20 is the other of the two PCI buses of the computer system 1, and is connected to the third device 50, the fourth device 60, and the bridge device 100. The specifications and the like relating to the secondary PCI bus 20 are as follows.
It is the same as the next PCI bus 10.

From the first device 30 to the fourth device 60
Are various input / output devices. When performing data transfer, these devices assert REQ to the arbitration units 70 and 180 relating to the buses to which they are connected.
Each of them receives the GNT to acquire the right to use the bus.
The bridge device 100 is a device that mediates the exchange of data between the primary PCI bus 10 and the secondary PCI bus 20 and internally has a 22D for “write operation”.
W buffer.

The arbitration unit 70 arbitrates the right to use the bus on the primary PCI bus 10. FIG. 2 shows a bridge device 1
00 is a detailed block diagram of FIG. Bridge device 100
Are the data paths 110 and 120 and the control units 130 and 14
0, latency timer registers 150 and 151, prediction units 160 and 170, and arbitration unit 180.

Each of the data paths 110 and 120 has a buffer for temporarily storing data when data is transferred from one bus to the other bus. The buffers of these data paths 110 and 120 have 22 DW,
There is a storage area of 18 DW for “delayed read operation”.

In the course of the "write operation" or the "delayed read operation", when the buffer of the data path 110 is completely filled with data, the control unit 130 asserts STOP to perform the "write operation" or the "delayed read operation". ”Is requested. The control unit 140 has the same function as the control unit 130. When the buffer of the data path 120 is completely filled with data, the control unit 140 asserts STOP and requests to stop the operation being executed.

Latency timer registers 150 and 151
Is a register for storing an initial counter value indicating the longest time that the master device can use in one data transfer in the use of the primary PCI bus 10 and the secondary PCI bus 20, respectively. In this embodiment, the initial value of the counter is “80”. The counter initial value is set to the value of the counter 16 when FRAME is asserted.
Transferred to 1.

The prediction units 160 and 170 have a function of detecting an empty state and estimating a time at which an empty state is established in the primary PCI bus 10 and the secondary PCI bus 20, respectively. Since the prediction unit 160 and the prediction unit 170 have the same function, the following mainly describes the prediction unit 160. The prediction unit 160 includes a counter 161, a prescribed value register 162, a comparison unit 163, a bus state detection unit 164,
It is composed of a judgment unit 165.

The counter 161 is connected to the primary PCI bus 10
When the FRAME 11a is asserted by any of the devices in the above, the latency timer register 15
The operation is started by loading the counter initial value “80” from 0, and the countdown is performed at every rising edge of the clock. Therefore, as described above, when this value is “80”, the master device is in a state of up to 80 clocks,
The bus can be occupied.

The specified value register 162 includes a counter 161
Stores a specified value to be compared with the value counted down by. This prescribed value is a value determined by the buffer capacity of the data path 110, and is a value determined from a clock time until all the buffers of the data path 110 are filled with data. However, in order to perform data transfer with the maximum burst transfer length, it is necessary to start transmitting data to the transfer destination bus before all buffers of the data path 110 are filled with data. For this reason, the buffer capacity for the "write operation" is 22 DW, but a time margin of two clocks is secured. Therefore, the specified value for the “write operation” in the present embodiment is “20”.

The comparing section 163 compares whether the value of the counter 161 and the value of the specified value register 162 are the same, and notifies the judging section 165 when the value becomes "the same". Therefore, for example, when the counter 161 starts counting down from “80”, the specified value register 162
Is determined to be “identical” when the value of “” becomes “20”, and the determination unit 165 is notified.

The bus state detector 164 detects an empty state in the primary PCI bus 10. In this detection, of the control signals, the case where both FRAME and IRDY are in a deasserted state is detected as an “empty state”, and the other case is detected as a “used state”. When an “empty state” is detected, the bus state detection unit 164 notifies the determination unit 165 of the detection.

When one of the following two conditions is satisfied, the determination unit 165 determines that one of the following conditions is satisfied.
Notify. (Condition 1) A notification from the bus state detection unit 164 that the primary PCI bus 10 has become “free”. (Condition 2) The comparing unit 163 has notified that the value of the counter 161 and the specified value of the specified value register 162 have become “identical”.

The arbitration unit 180 arbitrates the right to use the bus on the secondary PCI bus 20. Specifically, the secondary side P
When REQ is asserted from each device connected to the CI bus 20, the GNT of each device is asserted based on a certain rule, and a bus use right is granted to any device. In this case, the FRAME 11a and the IRDY 11b detect whether or not the primary PCI bus 10 is in an empty state. If not, the GRAM is asserted to give a bus use right after waiting for a notification from the determination unit 165.

Next, the operation of the bridge device 100 according to the present invention will be described with reference to the drawings. FIG.
In the computer system 1 including the present apparatus 100, the third device 50 connected to the secondary PCI bus 20
6 is a timing chart showing states of respective signals in a “write operation” for writing 64 DW data to the first device 30 connected to the primary PCI bus 10 via the bridge device 100. The “writing operation”
In the above, the secondary PCI bus 20 is the master bus, the third device 50 is the master device, the primary PCI bus 10 is the target bus, and the first device 30 is the target device. First, the third device 50
To use the next PCI bus 20, the REQ 51 is asserted at an arbitrary timing, for example, the timing of the clock 3.

On the other hand, the counter 161 constantly monitors whether or not the FRAME 11a is asserted among the control signals related to the primary PCI bus 10, and the FRAME 11a is asserted at the timing of the clock 2. Is detected (T30). This FRAME11
The assertion of a means that the use of the primary PCI bus 10 has been started by another device.
As a result, the counter 161 loads the counter initial value “80” from the latency timer register 150 and starts counting down.

Further, the bus state detecting section 164 detects the primary P
Among the control signals related to the CI bus 10, FRAME 11a
And IRDY 11b are constantly monitoring whether or not both are in a deasserted state. In the case of the present embodiment, as shown in FIG. 3, between the clock 2 and the clock 83, the primary PCI bus 10 is used by another device.

Next, at the timing of the clock 62, the comparator 163 compares the value of the counter 161 with the specified value register 1
Since the value of 62 is the same at “20” (T31), the fact is notified to the arbitration unit 180 via the determination unit 165.
Thereby, the determination unit 180 determines that the third device 50
To grant the right to use the secondary PCI bus 20, the GNT 52
Is asserted (T32).

As a result, the third device 50 sets “(1D indicating the first device) from the timing of the clock 64.
The transmission of “(address of W) + (data of 64 DW)” is started, and the bridge device 100 starts taking in these data. Further, the bridge device 100 uses the primary PCI bus 10 so that the
Assert EQ71.

On the other hand, the arbitration unit 70 includes the counter 16
At the timing of the clock 82 when the value of 1 becomes “0”, (T
33) Since the FRAME 11a is deasserted by another device and the primary PCI bus 10 becomes empty, the GNT 72 is asserted (T34), and the bridge device 100 is given the right to use the primary PCI bus 10.

Finally, the bridge device 100 sends the first device 30 “(1DW address indicating the first device) + (64D
W data) ”to end the“ write operation ”.

As described above, in the "write operation", even when the master-side bus and the target-side bus are not idle at the same time, the timing is expected to be such that the target-side bus is expected to be idle. Since the "write operation" of the master device is started, continuous data transfer becomes possible, and the burst transfer length and the bus use efficiency can be improved. If the target bus becomes empty before the timing at which the target bus is predicted to be empty, the "write operation" of the master device is started at this timing. A long waiting time can be eliminated.

(Embodiment 2) In Embodiment 2 of the present invention, a "read operation" by "delayed read" will be described. In the present embodiment, the second device 40 communicates with the fourth device 60 via the bridge device 100 to 64DW.
Is assumed to be "delayed read" the data of FIG. The outline of the “delayed reading” method is as described above.

Note that the computer system and the bridge device in the present embodiment are basically the same as those in the first embodiment. However, it is assumed that an 18 DW buffer is provided inside the data paths 110 and 120 for “delayed reading”. The specified value of the specified value register 162 is set to “16” for the same reason as in the case of the “write operation”.

FIG. 4 is a timing chart showing the state of each signal in the "read operation". In the “read operation”, the primary PCI bus is the master bus, the second device 40 is the master device,
The secondary PCI bus 20 is a target bus, and the fourth device is a target device.

First, the second device 40 is a primary PC
In order to use the I bus 10, the REQ 41 is asserted at an arbitrary timing, for example, the timing of the clock 1. On the other hand, the arbitration unit 70 asserts the GNT 42 and gives the second device 40 the right to use the primary PCI bus 10. Accordingly, the second device 40 transmits the “1DW address indicating the fourth device” at the timing of the clock 4.

As a result, the bridge device 100 takes in the “1DW address indicating the fourth device” and asserts the STOP 11d at the timing of the clock 4 to temporarily suspend the “read operation”. Thereafter, the FRAME 11a and the IRD
Y11b is deasserted, and the primary PCI bus 10 becomes "empty". In this case, the bridge device 100
Asserts REQ101 at the timing of clock 4 to use the secondary PCI bus 20.

Next, the counter 161 indicates that the second device 4
0 is temporarily released by another device at the timing of the clock 18 after the use right of the primary PCI bus 10 is relinquished.
It detects that the FRAME 11a of the next PCI bus 10 has been asserted (T40), loads the counter initial value "80" from the latency timer register 150, and starts counting down.

After that, the arbitration unit 180 sends the bridge device 100 2 at the timing of the clock 82 based on the notification from the determination unit 165 that the value of the counter 161 and the value of the specified value register have become the same (T41). Secondary PCI bus 2
Assert GNT 102 to use 0 (T4
2) Give the right to use the bus.

As a result, the bridge device 100
The 64 DW data read from the device 60 starts to be taken into the buffer for “delayed reading” of the data path 120 (CLK99 to CLK162). On the other hand, the second device 40 asserts the REQ 41 at the timing of the clock 82 at which the value of the counter 161 becomes equal to the specified value “16”.

During this time, the bus state detection unit 164 outputs the FRAME1 among the control signals on the primary PCI bus 10.
1a and IRDY 11b are monitored to see if they are both deasserted. At the timing of the clock 84 before the value of the counter 161 becomes "0", the primary PCI bus 10
Is detected as being “vacant” (T43, T4).
4).

As a result, the arbitrating unit 70 asserts the GNT 42 (T45) and causes the second device 40 to send the primary PC
The right to use the I bus 10 is given. Finally, the second device 4
0 receives “64 DW data” read from the fourth device and transmitted from the bridge device 100, and ends the “read operation”.

As described above, in the “read operation” by the “delayed read”, even if the master bus and the target bus are not idle at the same time, it is predicted that the master bus will be idle. Since the “read operation” of the target device is started at the same timing as the target device, continuous data transfer becomes possible, and the burst transfer length and the bus use efficiency can be improved. Also, if the master-side bus becomes empty before the timing at which the master-side bus is expected to be empty, a “read operation” from the target device is started in accordance with this timing, Unnecessary waiting time can be eliminated.

In the above embodiments, the specified value of the specified value register 162 is set to “20” for “write operation” and “16” for “read operation” by securing a time margin of two clocks. However, the specified value may be set by securing a time margin other than two clocks.

[0065]

As is apparent from the above description, the bridge device according to the present invention includes a transmitting bus connected to a transmitting device having data to be transmitted, and a receiving device capable of receiving such data. A bridge device that is provided in a computer system having a connected receiving-side bus and captures the transmitted data on the transmitting-side bus in a buffer, and transfers the data by outputting the data to the receiving-side bus. The prediction device includes a prediction unit that predicts a timing at which the reception-side bus becomes empty, and a permission unit that permits transmission to a transmission-side device that has requested data transfer based on the timing predicted by the prediction unit.

As a result, the data transfer can be started from the transmitting device at the timing when the receiving bus becomes empty, so that continuous data transfer can be performed without interruption.

Further, the predicting means includes a detecting unit for detecting the start of data transfer by another device on the receiving bus, and a timing unit for measuring a time from the start of the data transfer. The permitting means permits the transmitting device to transmit when the timer measures a certain time, and is allowed to continuously occupy the bus in one data transfer during the certain time. It may be configured as a time obtained by subtracting the time required to transfer data of the size of the buffer to the buffer from the longest time.

Thus, at the timing when the data transfer of the buffer size is completed from the transmitting device to the bridge device, the time during which the other device can occupy the receiving bus ends. While outputting the data in the buffer, the capture of the subsequent data transmitted from the transmitting device can be continued.

Further, the predicting means includes a detecting section for detecting the start of data transfer by another device on the receiving side bus, and when detecting the start of data transfer, continuously connects the bus in one data transfer. A timer that measures the longest time allowed to be occupied, a retaining unit that retains the time required to transfer data of the size of the buffer to the buffer, and a timer that measures the time. It may be configured to include a comparing unit that compares the remaining time up to the longest time with the time held in the holding unit and detects a coincidence time.

As a result, as described above, at the timing when the data transfer of the buffer size is completed from the transmitting device to the bridge device, the time during which the receiving device can occupy the receiving bus ends. While outputting the data in the buffer to the receiving bus,
The capture of the subsequent data transmitted from the transmitting device can be continued.

The permitting means includes a bus state detecting unit for detecting an empty state of each of the transmitting bus and the receiving bus, a receiving means for receiving a data transfer request from the transmitting device, and a transmitting means for requesting the data transfer. For the side device, if it is detected that both buses are free, transmission is immediately permitted, and if it is detected that only the transmission side bus is free, as a result of comparison by the comparing unit, It is also possible to configure so that transmission is permitted at the time of matching.

In this way, the vacant state of the transmitting bus and the receiving bus is constantly monitored, and data transmission is started from the transmitting device as soon as the receiving bus becomes vacant. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a computer system 1 including a bridge device 100 according to the present invention.

FIG. 2 is a detailed block diagram of a bridge device 100 according to the present invention.

FIG. 3 is a timing chart showing a state of each signal in a write operation according to the first embodiment.

FIG. 4 is a timing chart showing a state of each signal in a read operation according to the second embodiment.

FIG. 5 is a schematic block diagram of a computer system including a conventional bridge device.

FIG. 6 shows a write operation using a conventional bridge device;
5 is a timing chart showing the state of each signal when the target side bus is empty.

FIG. 7 shows a write operation using a conventional bridge device;
6 is a timing chart showing the state of each signal when the target bus is not empty.

[Explanation of symbols]

 1 Computer System 10, 510 Primary PCI Bus 20, 520 Secondary PCI Bus 30, 530 First Device 40, 540 Second Device 50, 550 Third Device 60, 560 Fourth Device 70, 180 Arbitration Unit 570, 580 Arbitration unit 100 Bridge device 110, 120 Data path 130, 140 Control unit 150, 151 Latency timer register 160, 170 Prediction unit 161 Counter 162 Prescribed value register 163 Comparison unit 164 Bus state detection unit 165 Judgment unit

Claims (4)

[Claims] 1. A computer system having a transmitting bus connected to a transmitting device having data to be transmitted and a receiving bus connected to a receiving device capable of receiving such data, and comprising: A bridge device for receiving data on the transmission-side bus into a buffer and outputting the data to the reception-side bus to transfer data, and a prediction unit for predicting a timing at which the reception-side bus becomes empty, Based on the timing predicted by the prediction means,
A permission unit for permitting transmission to a transmission-side device that has requested data transfer. 2. The predicting means includes: a detecting unit that detects a start of data transfer by another device on a receiving-side bus; and a timing unit that counts time from when the start of the data transfer is detected. The permitting means permits the transmitting device to transmit when the timer measures a predetermined time, and is allowed to continuously occupy the bus in one data transfer during the predetermined time. 2. The bridge device according to claim 1, wherein the time is obtained by subtracting a time required for transferring data of the size of the buffer to the buffer from a longest time. 3. The detecting means for detecting the start of data transfer by another device on a receiving-side bus, and when the start of data transfer is detected, continuously connects the bus in one data transfer. A timer that measures the longest time allowed to be occupied; a retaining unit that retains the time required to transfer data of the size of the buffer to the buffer; and a timer that measures the time. The bridge device according to claim 1, further comprising: a comparing unit configured to compare a remaining time up to a longest time with a time held in the holding unit and detect a coincidence time. 4. The transmission device according to claim 1, wherein the permission unit includes a bus state detection unit configured to detect an empty state of each of the transmission-side bus and the reception-side bus; a reception unit configured to receive a data transfer request from the transmission-side device; If both buses are detected to be free for the transmitting device, transmission is immediately permitted.If only the transmitting bus is detected to be free,
4. The bridge device according to claim 3, wherein transmission is permitted at the time when the result of the comparison by the comparison unit matches.