JP2001266577A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which power consumption is reduced, access control can be performed, while increasing operation speed. SOLUTION: An address signal generating section 4 outputs an address signal Add with the prescribed cycle and extends an output cycle of the address signal Add based on an input of a waiting signal WAIT. An address decoder 5 decodes an address signal Add and outputs a decoding signal DEC. An activating signal generating section 6 generates an activating signal CS based on the decoding signal DEC. A memory region 1 performs write-in operation or read-out operation based on the activating signal CS and the address signal Add. A waiting signal generating section 3 outputs the waiting signal WAIT for extending an output cycle of an initial address signal Add outputted from the address signal generating section 4 to the address signal generating section 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an access control circuit for controlling an access operation of a semiconductor memory device.

[0002] In recent years, portable electronic devices such as digital cameras are equipped with large-capacity semiconductor storage devices, and the operating speed thereof has been further increased. In these electronic devices, since a dry battery or a rechargeable battery is used as a power source, it is necessary to reduce the power consumption in order to secure a sufficient operation continuation time. Therefore, in a semiconductor storage device mounted on such an electronic device, it is necessary to increase the operation speed while reducing power consumption.

[0003]

2. Description of the Related Art Conventionally, in a semiconductor memory device having a plurality of banks, in order to reduce the power consumption, a bank which is not accessed is made inactive and only the bank selected based on an address signal has its address. In some cases, access control is performed such that a write operation or a read operation is performed based on activation based on a signal.

The operation of such a semiconductor memory device will be described with reference to FIG. 5. In a bank selected based on an address signal Add, an L-level selection signal CS is input and activated.

At the time of a read operation, for example, cell information is read as read data Data from the memory cell selected based on the input of the clock signal CK. By such an operation, each bank is selected and activated based on the address signal Add, and the unselected banks are maintained in an inactive state, so that power consumption can be reduced.

[0006]

As described above, in a semiconductor memory device that performs a read operation by activating each bank based on the address signal Add, the read data Data is output based on the input of the address signal Add. By the time, the decoding time t1 until the activation signal CS falls to the L level based on the input of the address signal Add
And the setup time t2 from when the activation signal CS falls to the L level to when the clock signal CK rises.
In addition, an access time t3 from when the clock signal CK rises to the H level to when the output of the read data Data is started, and a hold time t4 for maintaining the output of the read data Data are required.

The sum of the times t1, t2, t3, and t4 must be within an input cycle of the address signal Add, that is, one cycle of the clock signal CK. In such a semiconductor memory device, when the frequency of the clock signal CK is increased in order to increase the operation speed, the input cycle of the address signal is shortened.

However, since the times t1 to t4 are constant irrespective of the input cycle of the address signal Add, the input cycle of the address signal Add is changed to the times t1 and t4.
It cannot be shorter than the sum of t2, t3 and t4.
Therefore, there is a problem that the operation speed cannot be sufficiently increased.

On the other hand, if each bank is always activated irrespective of the address signal Add, the setup time t2 can be omitted in each cycle, so that the input cycle of the address signal Add can be shortened and the operation can be shortened. The speed can be increased.

However, if all banks are always activated regardless of the address signal, there is a problem that power consumption increases. An object of the present invention is to provide a semiconductor memory device capable of performing access control capable of reducing power consumption while increasing operating speed.

[0011]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the address signal generation unit 4 outputs the address signal Add in a predetermined cycle,
Address signal Add based on the input of standby signal WAIT
Extend the output cycle. The address decoder 5 decodes the address signal Add and decodes the decoded signal DE.
Output C. The activation signal generator 6 generates an activation signal CS based on the decode signal DEC. The memory area 1 stores the activation signal CS and the address signal A
A write operation or a read operation is performed based on dd. The standby signal generation unit 3 generates a standby signal WAIT for extending an output cycle of the first address signal Add output from the address signal generation unit 4 based on the input of the activation signal CS. Output to 3.

Further, in the configuration shown in FIG. 4, the address signal generating section generates and continuously outputs an address signal for a preset number of accesses, and sets the access frequency value before outputting the address signal. Is output. The address decoder decodes the address signal and outputs a decoded signal. The access count determination unit is
An activation signal is output based on the input of the address count value, and an access count is counted based on the input of the decode signal. When the access count matches the access count value, the output of the activation signal is output. To stop. The memory area performs a write operation or a read operation based on the activation signal and the address signal.

[0013]

(First Embodiment) FIG. 2 shows a first embodiment of the present invention. The semiconductor memory device according to this embodiment includes first to third memory regions 1a to 1c each including a plurality of banks, and includes a frequency determination unit 2, a standby signal generation unit 3, a CPU 4, an address decoder 5 And an activation signal generation unit 6 constitute an access control circuit.

The frequency judging section 2 receives the external clock signal CLK and judges whether or not the input cycle of the address signal based on the external clock signal CLK is longer than a preset time. Output as the determination signal HCK.

That is, when the external clock signal CLK is higher than the operation guarantee frequency of each of the memory regions 1a to 1c, the frequency judgment unit 2 outputs the H level frequency judgment signal HCK.
Is output. External clock signal CLK is applied to each memory area 1
When the frequency is lower than the operation guarantee frequency of a to 1c, the frequency determination unit 2 outputs an L level frequency determination signal HCK.

The standby signal generator 3 includes a latch circuit 7
, And flip-flop circuits 8 a to 8 c and an OR circuit 9. The frequency determination signal HCK is input as data D to the flip-flop circuits 8a to 8c. The activation signals CS1 to CS1 output from the activation signal generator 6 are applied to the flip-flop circuits 8a to 8c.
CS3 is input as clock signal CK, and outputs data D as output signal Q based on the fall of activation signals CS1 to CS3 to L level.

The output signals Q of the flip-flop circuits 8a to 8c are input to the OR circuit 9. And O
The output signal of the R circuit 9 is the standby signal WAIT as the CP
The signal is input to U4 and is input to the latch circuit 7 as data D.

The latch circuit 7 receives, for example, an internal clock signal CK having the same frequency as the external clock signal CLK from the CPU 4 and outputs the internal clock signal C
Based on the rise of K to H level, data D is latched and output as output signal Q.

The output signal Q of the latch circuit 7 is input to the flip-flop circuits 8a to 8c as a reset signal PR. The flip-flop circuits 8a to 8a
8c resets its output signal Q to L level when the reset signal PR rises to H level.

The CPU 4 generates an address signal,
The address signals are sequentially output at a cycle equal to the cycle of the clock signal CK. Of the address signals, the first to
Upper address signals A12 to A15 for selecting any of the third memory areas 1a to 1c are input to the address decoder 5. The first to third memory areas 1
lower address A for selecting a storage cell in a to 1c
xx is input to the address decoders in the first to third memory areas 1a to 1c.

The CPU 4 outputs an H level standby signal WA.
When the IT is input, the same upper address signals A12 to A15 and lower address signal Axx as in the previous cycle are continuously output.

The address decoder 5 includes a NOR circuit 1
The upper address signals A12 to A15 are input to 0a to 10c directly or via an inverter circuit, respectively.

The NOR circuits 10a to 10c correspond to the first to third memory areas 1a to 1c, respectively. When upper address signals A12 to A15 for selecting the first memory area 1a are input to the address decoder 5,
All the input signals of the NOR circuit 10a become L level,
H level decode signal DE from NOR circuit 10a
C1 is output.

Similarly, upper address signals A12 to A15 for selecting the second memory area 1b are applied to the address decoder 5
, All the input signals of the NOR circuit 10b become L level, and the H level decode signal DEC2 is output from the NOR circuit 10b.

Similarly, the upper address signals A12 to A15 for selecting the third memory area 1c are supplied to the address decoder 5
, All the input signals of the NOR circuit 10c become L level, and the NOR circuit 10c outputs the decode signal DEC3 of H level.

The activation signal generator 6 comprises three latch circuits 11a to 11c.
The decode signals DEC1 to DEC3 are input to 11c, respectively.

Then, the decode signals DEC1 to DEC3
Becomes H level, L-level activation signals CS1-C
S3 is output, and the decode signals DEC1-D
When EC3 becomes L level, H level activation signal CS
1 to CS3 are output.

The activation signals CS1 to CS3 are input to the flip-flop circuits 8a to 8c of the standby signal generation unit 3 and the first to third memory areas 1a to 1c.
1c.

In the first to third memory areas 1a to 1c,
When the L-level activation signals CS1 to CS3 are input, they are activated and the clock signal CK and address signal Axx are activated.
Performs a read operation or a write operation on the basis of. At the time of a read operation, the read data is output to the CPU 4.

Next, the operation of the access control circuit of the semiconductor memory device configured as described above will be described with reference to FIG. External clock signal CLK is applied to each of memory areas 1a-1c.
When the frequency is higher than the operation guarantee frequency,
A level frequency determination signal HCK is output.

In this state, for example, the first memory area 1a
When the address signal Add is output from the CPU 4 when the cell information is read out by successive access to the memory cell, the decode signal DEC1 output from the address decoder 5 based on the upper address signals A12 to A15. To DEC3, the decode signal DEC1 is H
Level.

Then, the activation signal CS1 becomes L level, the first memory area 1a is activated, and a read operation is performed based on the lower address signal Axx and the clock signal CK input from the CPU 4. Activation signal C
S1 is maintained at the L level while the first memory area 1a is continuously selected.

At this time, based on the fall of the activation signal CS1 to the L level, the output signal Q of the flip-flop circuit 8a of the standby signal generator 3 becomes the H level, and
The circuit 9 outputs the H-level standby signal WAIT.
Then, the CPU 4 outputs the address signal Add in the next cycle.
Is stopped, and the output of the first address signal Add is maintained.

After the H-level standby signal WAIT is output, the output signal Q of the latch circuit 7 goes high based on the next rising edge of the clock signal CK, and based on the output signal Q of the latch circuit 7 Output signal Q of flip-flop circuit 8a is reset to L level, and standby signal WAIT returns to L level.

Then, in the first memory area 8a, the address signal Add input in the first read cycle becomes 2
It is maintained during the cycle, and the read data Data is read and output to the CPU 4.

The address signal Add in the first cycle is 2
After being maintained during the cycle, the wait signal WAIT has returned to the L level, so that the CPU 4 outputs the next address signal Add for selecting a memory cell in the first memory area 1a in the next cycle.

At this time, the activation signal CS1 is maintained at L level, and based on the lower address signal Axx of the newly input address signal Add, the first memory area 1a
Outputs read data Data.

This operation is repeated while the memory cells in the first memory area 1a are continuously selected. On the other hand, if the address signal Add output from the CPU 4 is an address signal for continuously selecting the second memory area 1b, the activation signal CS2 goes low and the activation signals CS1 and CS3 go high. , Only the second memory area 1b is activated.

In the same manner as described above, the first address signal Add is maintained for two cycles to perform a read operation for the address, and the subsequent address signal Add is switched every cycle to read data Data.
Are sequentially read.

If the address signal Add output from the CPU 4 is an address signal for continuously selecting the third memory area 1c, the activation signal CS3 goes low and the activation signals CS1 and CS2 go high. As a result, only the third memory area 1c is activated.

In the same manner as described above, the first address signal Add is maintained for two cycles to perform a read operation for the address, and the subsequent address signal Add is switched every cycle to read data Data.
Are sequentially read.

When the external clock signal CLK is lower than the guaranteed operation frequency of each of the memory areas 1a to 1c, the frequency judgment section 2 outputs the L level frequency judgment signal HCK.

In this state, the standby signal WAIT is always low.
Since it is maintained at the level, the first address signal Add is switched to the next address signal in one cycle. At this time, the activation signals CS1 to CS in each read cycle
There is no problem because there is room to secure the setup time of No. 3.

With the access control circuit configured as described above, the following operational effects can be obtained. (1) When memory cells in any one of the address areas are continuously selected from the plurality of memory areas 1a to 1c,
Since the unselected memory areas are maintained in an inactive state, power consumption can be reduced as compared with a case where all memory areas are always activated.

(2) In the memory areas continuously selected, the activation signals CS1 to CS3 are maintained at the L level, and the activated state is maintained. Therefore, in the read cycle based on the second and subsequent address signals Add, except for the read cycle based on the first input address signal Add, the signal is secured from the fall of the activation signals CS1 to CS3 to the rise of the clock signal CK. The setup time to be done can be omitted.

Therefore, the frequency of the input cycle of the address signal Add, that is, the clock signal CK is increased, and the read operation of the cell information can be accelerated. (3) The first address signal Add input to the selected memory area is maintained for twice as long as a normal read cycle. That is, the read cycle by the first address signal Add secures twice the time of the subsequent read cycle.

Therefore, even if the read cycle is shortened by increasing the frequency of the clock signal CK, the first read cycle starts from the fall of the activation signals CS1 to CS3.
The setup time t2 until the rise of the clock signal CK can be sufficiently ensured. (Second Embodiment) FIG. 4 shows a second embodiment. The CPU 12 of this embodiment outputs an address signal Add to the address decoder 13 and the memory area 14 in a predetermined read cycle.

The CPU 12 has a program for continuously outputting the address signal Add for a predetermined cycle set in advance. Before executing the program, the number of times the address signal Add is output to the register 15, ie, the memory area, 14 is output.

When the number of accesses AC is input from the CPU 12, the register 15 outputs the value to the down counter 16 and outputs an activation signal CS to the memory area 14.

The address decoder 13 comprises a CPU 12
When an address signal Add for selecting a storage cell in the memory area 14 is input from the controller, a decode signal DEC is output to the down counter 16.

The down counter 16 receives an internal clock signal CK. Then, the decode signal DEC
Is input, the number of times of access output from the register 15 is down-counted based on the rise of the clock signal CK, and the counted value is stored in the register 15.
Output to

The register 15 includes a down counter 16
It detects whether or not the count value output from is zero, and if it is zero, stops outputting the activation signal CS. In the access control circuit configured as described above, when continuous access to the memory area 14 is started by the CPU 12, a preset number of accesses is output from the CPU 12 to the register 15 prior to the start, and the access The memory area 14 is activated by an activation signal CS output from the register 15 based on the input of the number of times.

Then, the address signal Ad is sent from the CPU 12.
When d is output in a predetermined read cycle, a read operation of cell information is sequentially performed in the memory area 14, and read data is output.

At this time, the down counter 16 counts down the number of accesses input from the register 15. When the predetermined number of accesses to the memory area 14 is completed, the count value of the down counter 16 becomes 0, and the output of the activation signal CS from the register 15 is stopped. As a result, the memory area 14 is inactivated.

With the access control circuit configured as described above, the following operational effects can be obtained. (1) Since the memory area 14 is activated only when the access to the memory area 14 occurs, power consumption can be reduced as compared with the case where the memory area 14 is always activated.

(2) The activation signal CS for activating the memory area 14 is input prior to the input of the address signal Add to the memory area 14, and the activation signal CS is activated.
While d is being input to the memory area 14, the input is continued.

Then, the setup time can be omitted in all read cycles from the input of the first address signal Add to the end of the read operation.

Therefore, the frequency of the input cycle of the address signal Add, that is, the clock signal CK is increased, and the read operation of the cell information can be accelerated. (3) The frequency of the clock signal CK can be increased while the first read cycle and the subsequent read cycle have the same time, thereby speeding up the cell information read operation.

The above embodiment can be modified as follows. -In the first embodiment, the memory area is one,
The address decoder, the activation signal generator, and the standby signal generator may be configured to correspond to one memory area. In the second actual output mode, a plurality of memory areas may be provided, and the address decoder and the register may be configured to correspond to the plurality of memory areas.

[0060]

As described above in detail, the present invention can provide a semiconductor memory device which enables access control capable of reducing power consumption while increasing the operating speed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram illustrating an access control circuit according to the first embodiment.

FIG. 3 is a timing waveform chart showing an operation of the first embodiment.

FIG. 4 is a block diagram showing a second embodiment.

FIG. 5 is a timing waveform chart showing the operation of the conventional example.

[Explanation of symbols]

 Reference Signs List 1 memory area 3 standby signal generation section 4 address signal generation section (CPU) 5 address decoder Add address signal WAIT standby signal DEC decode signal CS activation signal

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Claims (5)

[Claims] An address signal generator for outputting an address signal in a predetermined cycle and extending an output cycle of the address signal based on an input of a standby signal; an address decoder for decoding the address signal and outputting a decoded signal An activation signal generation unit that generates an activation signal based on the decode signal; a memory area that performs a write operation or a read operation based on the activation signal and the address signal; and an input of the activation signal. A standby signal generator for outputting a standby signal to the address signal generator for extending an output cycle of an initial address signal output from the address signal generator based on the semiconductor memory. apparatus. 2. A frequency determination circuit for outputting a frequency determination signal when a frequency of a clock signal for setting an output cycle of the address signal is equal to or higher than a predetermined frequency. 2. The semiconductor memory device according to claim 1, wherein said standby signal can be output by being activated based on a signal. A plurality of memory regions operating independently, a plurality of address decoders outputting decode signals for selecting each of the memory regions based on the address signals, and a plurality of address decoders outputting the decode signals based on the decode signals. A plurality of the activation signal generators each outputting an activation signal to a plurality of memory areas; and the standby signal is output based on the activation signal output from at least one of the plurality of the activation signal generators. 3. The semiconductor memory device according to claim 1, further comprising: said standby signal generating unit for outputting. 4. An address signal generator for generating and continuously outputting address signals for a preset number of accesses, and outputting the number of accesses before outputting the address signal; An address decoder for decoding a signal and outputting a decode signal; outputting an activation signal based on the input of the address count value; counting an access count based on the input of the decode signal; An access frequency determining unit for stopping the output of the activation signal when the number of accesses matches, and a memory area for performing a write operation or a read operation based on the activation signal and the address signal. A semiconductor memory device characterized by the following. 5. The access number determination unit includes: a counter circuit that counts down the access number; and a register that stops outputting the activation signal when a count value of the counter circuit becomes 0. 5. The semiconductor memory device according to claim 4, wherein: