JP4568299B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to an access control circuit for controlling an access operation of a semiconductor memory device.
In recent years, a portable electronic device such as a digital camera is equipped with a large-capacity semiconductor memory device, and its operation speed is further increased. Since these electronic devices use a dry battery or a rechargeable battery as a power source, it is necessary to reduce power consumption in order to ensure a sufficient operation duration. Therefore, it is necessary to increase the operation speed of a semiconductor memory device mounted on such an electronic device while reducing power consumption.

  Conventionally, in a semiconductor memory device having a plurality of banks, in order to reduce power consumption, a bank that is not accessed is inactivated, and only a bank selected based on the address signal is activated based on the address signal. In some cases, access control is performed to perform a write operation or a read operation.

The operation of such a semiconductor memory device will be described with reference to FIG. 5. In the bank selected based on the address signal Add, an L level selection signal CS is input and activated.
For example, during the read operation, cell information is read as read data Data from the memory cell selected based on the input of the clock signal CK.

  By such an operation, each bank is selected and activated based on the address signal Add, and the bank that is not selected is maintained in an inactive state, so that power consumption can be reduced.

  As described above, in a semiconductor memory device that performs a read operation by activating each bank based on the address signal Add, the address signal Add is input before the read data Data is output based on the input of the address signal Add. Based on the decoding time t1 until the activation signal CS falls to the L level, the setup time t2 until the activation of the clock signal CK after the activation signal CS falls to the L level, and the clock signal CK at the H level An access time t3 from when the read data starts to be output until a start of output of the read data Data and a hold time t4 for maintaining the output of the read data Data are required.

The sum of the times t1, t2, t3, and t4 needs to be within the time of the input cycle of the address signal Add, that is, one cycle of the clock signal CK.
In such a semiconductor memory device, when the frequency of the clock signal CK is increased in order to increase the operation speed, the address signal input cycle is shortened.

  However, since the times t1 to t4 are constant regardless of the input cycle of the address signal Add, the input cycle of the address signal Add cannot be made shorter than the sum of the times t1, t2, t3, and t4. Therefore, there is a problem that the operation speed cannot be sufficiently increased.

  On the other hand, if each bank is always activated regardless of the address signal Add, the setup time t2 can be omitted in each cycle. Therefore, the input cycle of the address signal Add is shortened and the operation speed is increased. Can be achieved.

However, there is a problem that power consumption increases if all banks are always activated regardless of the address signal.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of access control capable of reducing power consumption while increasing the operation speed.

  In order to achieve the above-mentioned object, the invention according to claim 1 generates an address signal for a predetermined number of accesses and outputs the address signal continuously, and outputs the access number value, and the address An address decoder that decodes the signal and outputs a decode signal; outputs an activation signal based on the input of the access count value; counts the access count based on the decode signal; An access number determination unit that stops the output of the activation signal when it coincides with a numerical value, and a memory area that performs a write operation or a read operation based on the activation signal and the address signal.

  According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the access count determination unit includes a counter circuit that counts the access count, and the count value of the counter circuit becomes a predetermined value. At this time, the output of the activation signal is stopped.

  As described above, according to the present invention, it is possible to provide a semiconductor memory device capable of access control capable of reducing power consumption while increasing the operation speed.

(First embodiment)
FIG. 2 shows a first embodiment embodying the present invention. The semiconductor memory device of this embodiment includes first to third memory areas 1a to 1c composed of a plurality of banks, a frequency determination unit 2, a standby signal generation unit 3, a CPU 4, and an address decoder 5. And the activation signal generator 6 constitute an access control circuit.

  The frequency determination unit 2 receives an external clock signal CLK, determines whether an input cycle of an address signal based on the external clock signal CLK is longer than a preset time, and determines the determination result as a frequency determination signal HCK. Output as.

  That is, when the external clock signal CLK is higher than the operation guarantee frequency of each of the memory regions 1a to 1c, the frequency determination unit 2 outputs the H level frequency determination signal HCK. When the external clock signal CLK is lower than the operation guarantee frequency of each of the memory regions 1a to 1c, the frequency determination unit 2 outputs an L level frequency determination signal HCK.

The standby signal generator 3 includes a latch circuit 7, flip-flop circuits 8 a to 8 c, and an OR circuit 9.
The frequency determination signal HCK is input as data D to the flip-flop circuits 8a to 8c. The activation signals CS1 to CS3 output from the activation signal generator 6 are input to the flip-flop circuits 8a to 8c as the clock signal CK, respectively, and the activation signals CS1 to CS3 fall to the L level. Based on the above, the data D is output as the output signal Q.

  The output signal Q of the flip-flop circuits 8a to 8c is input to the OR circuit 9. The output signal of the OR circuit 9 is input to the CPU 4 as the standby signal WAIT and is input to the latch circuit 7 as data D.

  For example, the internal clock signal CK having the same frequency as the external clock signal CLK is input from the CPU 4 to the latch circuit 7, and the data D is latched and output based on the rising of the internal clock signal CK to the H level. Output as signal Q.

  The output signal Q of the latch circuit 7 is input as a reset signal PR to the flip-flop circuits 8a to 8c. When the reset signal PR rises to H level, each flip-flop circuit 8a-8c resets its output signal Q to L level.

  The CPU 4 generates an address signal and sequentially outputs the address signal in a cycle equal to the cycle of the clock signal CK. Upper address signals A12 to A15 for selecting one of the first to third memory areas 1a to 1c among the address signals are input to the address decoder 5. A lower address Axx for selecting a memory cell in the first to third memory areas 1a to 1c is input to an address decoder in the first to third memory areas 1a to 1c.

  Further, when the H level standby signal WAIT is input, the CPU 4 continues to output the upper address signals A12 to A15 and the lower address signal Axx that are the same as those in the previous cycle.

In the address decoder 5, the upper address signals A12 to A15 are input to the NOR circuits 10a to 10c directly or via an inverter circuit, respectively.
The NOR circuits 10a to 10c correspond to the first to third memory areas 1a to 1c, respectively. When the upper address signals A12 to A15 for selecting the first memory area 1a are input to the address decoder 5, all the input signals of the NOR circuit 10a become L level, and the H level decode signal DEC1 is output from the NOR circuit 10a. Is done.

  Similarly, when the upper address signals A12 to A15 for selecting the second memory area 1b are input to the address decoder 5, all the input signals of the NOR circuit 10b become L level, and the decode signal of H level from the NOR circuit 10b. DEC2 is output.

  Similarly, when the upper address signals A12 to A15 for selecting the third memory area 1c are input to the address decoder 5, all the input signals of the NOR circuit 10c become L level, and the NOR circuit 10c outputs an H level decode signal. DEC3 is output.

The activation signal generator 6 includes three latch circuits 11a to 11c, and the decode signals DEC1 to DEC3 are input to the latch circuits 11a to 11c, respectively.
When the decode signals DEC1 to DEC3 become H level, L level activation signals CS1 to CS3 are output, and when the decode signals DEC1 to DEC3 become L level, H level activation signals CS1 to CS3 are output. Is done.

The activation signals CS1 to CS3 are input to the flip-flop circuits 8a to 8c of the standby signal generation unit 3 and to the first to third memory areas 1a to 1c.
In the first to third memory areas 1a to 1c, when the L level activation signals CS1 to CS3 are input, the first to third memory areas 1a to 1c are activated and perform a read operation or a write operation based on the clock signal CK and the address signal Axx. . During the read operation, read data Data is output to the CPU 4.

Next, the operation of the access control circuit of the semiconductor memory device configured as described above will be described with reference to FIG.
When the external clock signal CLK is higher than the operation guarantee frequency of each of the memory areas 1a to 1c, the frequency determination unit 2 outputs an H level frequency determination signal HCK.

  In this state, for example, when the first memory area 1a is continuously accessed and the cell information read operation is performed, when the CPU 4 outputs the address signal Add, the first memory area 1a is based on the upper address signals A12 to A15. Among the decode signals DEC1 to DEC3 output from the address decoder 5, the decode signal DEC1 becomes H level.

  Then, the activation signal CS1 becomes L level, the first memory area 1a is activated, and a read operation is performed based on the lower address signal Axx and the clock signal CK input from the CPU 4. The activation signal CS1 is maintained at the L level while the first memory area 1a is continuously selected.

  At this time, based on the fall of the activation signal CS1 to the L level, the output signal Q of the flip-flop circuit 8a of the standby signal generation unit 3 becomes the H level, and the standby signal WAIT at the H level is output from the OR circuit 9. The Then, the CPU 4 stops switching of the address signal Add in the next cycle and maintains the output of the first address signal Add.

  Further, after the standby signal WAIT at H level is output, the output signal Q of the latch circuit 7 becomes H level based on the next rising edge of the clock signal CK, and the flip-flop circuit based on the output signal Q of the latch circuit 7 The output signal Q of 8a is reset to L level, and the standby signal WAIT returns to L level.

  Then, in the first memory area 8a, the address signal Add input in the first read cycle is maintained for two cycles, and the read data Data is read and output to the CPU 4.

  After the address signal Add of the first cycle is maintained for two cycles, the standby signal WAIT has returned to the L level, so that the CPU 4 selects the memory cell in the first memory area 1a in the next cycle. An address signal Add is output.

  At this time, the activation signal CS1 is maintained at the L level, and the read data Data is output from the first memory area 1a based on the lower address signal Axx of the newly input address signal Add.

Such operations are repeated while the memory cells in the first memory area 1a are continuously selected.
On the other hand, if the address signal Add output from the CPU 4 is an address signal that continuously selects the second memory area 1b, the activation signal CS2 becomes L level and the activation signals CS1 and CS3 become H level. Only the second memory area 1b is activated.

  Similarly to the above, the first address signal Add is maintained for two cycles, the read operation for the address is performed, the subsequent address signal Add is switched every cycle, and the read data Data is sequentially read.

  If the address signal Add output from the CPU 4 is an address signal that continuously selects the third memory area 1c, the activation signal CS3 becomes L level and the activation signals CS1 and CS2 become H level. Only the third memory area 1c is activated.

  Similarly to the above, the first address signal Add is maintained for two cycles, the read operation for the address is performed, the subsequent address signal Add is switched every cycle, and the read data Data is sequentially read.

Further, when the external clock signal CLK is lower than the guaranteed operating frequency of each of the memory regions 1a to 1c, the frequency determination unit 2 outputs an L level frequency determination signal HCK.
In this state, since the standby signal WAIT is always maintained at the L level, the first address signal Add is switched to the next address signal in one cycle. At this time, there is no problem because the setup time of the activation signals CS1 to CS3 can be secured in each read cycle.

In the access control circuit configured as described above, the following operational effects can be obtained.
(1) Among the plurality of memory areas 1a to 1c, when the memory cells in any one of the address areas are continuously selected, the memory areas not selected are maintained in an inactive state. Power consumption can be reduced as compared with the case of always activation.

  (2) In continuously selected memory regions, the activation signals CS1 to CS3 are maintained at the L level and the activated state is maintained. Therefore, except for the read cycle by the address signal Add that is input first, the read cycle based on the second and subsequent address signals Add is ensured from the fall of the activation signals CS1 to CS3 to the rise of the clock signal CK. The setup time should be omitted.

Therefore, the input cycle of the address signal Add, that is, the clock signal CK can be increased in frequency, and the cell information read operation can be speeded up.
(3) The first address signal Add input to the selected memory area is maintained for twice the normal read cycle. That is, the read cycle by the first address signal Add is secured twice as long as the subsequent read cycle.

Therefore, even if the frequency of the clock signal CK is increased and the read cycle is shortened, the setup time t2 from the fall of the activation signals CS1 to CS3 to the rise of the clock signal CK is sufficiently secured in the first read cycle. Can do.
(Second embodiment)
FIG. 4 shows a second embodiment. The CPU 12 of this embodiment outputs an address signal Add to the address decoder 13 and the memory area 14 in a predetermined read cycle.

  The CPU 12 includes a program for continuously outputting a predetermined cycle of the address signal Add for a predetermined cycle, and the number of times the address signal Add is output to the register 15 prior to execution of the program, that is, the memory area 14 The access count AC is output.

  When the access count AC is input from the CPU 12, the register 15 outputs the numerical value to the down counter 16 and outputs the activation signal CS to the memory area 14.

  The address decoder 13 outputs a decode signal DEC to the down counter 16 when an address signal Add for selecting a memory cell in the memory area 14 is input from the CPU 12.

  The down counter 16 receives an internal clock signal CK. When the decode signal DEC is input, the access count value output from the register 15 is down-counted based on the rising edge of the clock signal CK, and the count value is output to the register 15.

The register 15 detects whether or not the count value output from the down counter 16 is 0. When the count value is 0, the output of the activation signal CS is stopped.
In the access control circuit configured as described above, when continuous access to the memory area 14 is started by the CPU 12, the number of accesses set in advance prior to the start is output from the CPU 12 to the register 15. The memory area 14 is activated by the activation signal CS output from the register 15 based on the input of the number of times.

  When the address signal Add is output from the CPU 12 in a predetermined read cycle, cell information read operations are sequentially performed in the memory area 14 and read data is output.

  At this time, the down counter 16 performs a down count operation for the number of accesses input from the register 15. When the predetermined number of accesses to the memory area 14 ends, the count value of the down counter 16 becomes 0, and the output of the activation signal CS from the register 15 is stopped. As a result, the memory area 14 is inactivated.

In the access control circuit configured as described above, the following operational effects can be obtained.
(1) Since the memory area 14 is activated only when access to the memory area 14 occurs, power consumption can be reduced as compared with the case where the memory area is always activated.

  (2) The activation signal CS for activating the memory area 14 is input prior to the input of the address signal Add to the memory area 14 and is input while the address signal Add is input to the memory area 14. Continue to be.

Then, the setup time can be omitted in all read cycles from when the first address signal Add is input to when the read operation is completed.
Therefore, the input cycle of the address signal Add, that is, the clock signal CK can be increased in frequency, and the cell information read operation can be speeded up.

  (3) While the first read cycle and the subsequent read cycle are set to the same time, the clock signal CK can be increased in frequency, and the cell information read operation can be speeded up.

The above embodiment can be modified as follows.
In the first embodiment, the number of memory areas may be one, and the address decoder, the activation signal generation unit, and the standby signal generation unit may be configured to correspond to one memory area.
In the second embodiment, a plurality of memory areas may be provided, and the address decoder and the register may be configured to correspond to the plurality of memory areas.

It is a principle explanatory view of the present invention. It is a circuit diagram showing an access control circuit of the first embodiment. It is a timing waveform diagram which shows operation | movement of 1st embodiment. It is a block diagram which shows 2nd embodiment. It is a timing waveform diagram which shows operation | movement of a prior art example.

Explanation of symbols

1 Memory area 3 Standby signal generator 4 Address signal generator (CPU)
5 Address decoder Add Address signal WAIT Wait signal DEC Decode signal CS Activation signal

Claims (2)

An address signal for a predetermined number of accesses is generated and output continuously, and an address signal generator for outputting the access count value;
An address decoder that decodes the address signal and outputs a decoded signal;
The activation signal is output based on the input of the access count value, the access count is counted based on the decode signal, and the output of the activation signal is stopped when the access count matches the access count value. An access count determination unit,
A semiconductor memory device comprising: a memory region that performs a write operation or a read operation based on the activation signal and the address signal. The access count determination unit
A counter circuit for counting the number of accesses;
2. The semiconductor memory device according to claim 1, wherein when the count value of the counter circuit reaches a predetermined value, output of the activation signal is stopped.

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