JPH096490A - Microcomputer and data processing unit - Google Patents

Abstract

PURPOSE: To provide a microcomputer suitable for reducing the power consumption of the data processing unit. CONSTITUTION: The processing unit has an access state flag register 13 storing a access state to a memory and a control logic 12 generating a signal for low power consumption mode command with respect to a memory not accessed for a prescribed period based on the storage content of the access state flag register 13 to form a bus controller 21. Since the signal for commanding low power consumption mode to the memory not accessed for a prescribed period is obtained, the transit of a peripheral device to the low power consumption mode is made proper.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing power consumption in a microcomputer and a data processing device including the same.

[0002]

2. Description of the Related Art A microcomputer and a peripheral device such as a semiconductor memory accessible by the microcomputer are combined with each other and a predetermined program is executed to enable desired data processing. There is. A computer system is an example of such a data processing device, in which a microcomputer and various semiconductor memories are coupled by a bus so that signals can be exchanged, and further, an input device such as a keyboard and a CRT.
A display device such as a display device is provided. A microcomputer is a logical core of a computer system and has functions such as addressing, reading and writing of information, data operation, sequence of instructions, acceptance of interrupts, and activation of information exchange between a storage device and an input / output device. Have.

In recent years, many data processing devices such as portable personal computers and electronic notebooks that can be operated by a battery have been commercialized.

An example of a document describing a microcomputer is "LSI Handbook (Page 540-)" issued by Ohm Co., Ltd. on November 30, 1984.

[0005]

The power consumption of the data processing device should be as low as possible. Particularly in a system using a battery as an operating power source, such as a portable personal computer, it is extremely important to reduce power consumption because a smaller battery enables operation for a long time. When the present inventor examined the reduction of power consumption, peripheral devices such as a semiconductor memory are
Since it is not necessary to keep it in the normal operation state, it has been found that shifting it to the low power consumption mode at an appropriate timing is effective in reducing the power consumption of the entire data processing device.

An object of the present invention is to provide a microcomputer suitable for reducing the power consumption of a data processing device. Another object of the present invention is to provide a data processing device equipped with such a microcomputer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a holding means (13) capable of holding the access status to the peripheral device and a control for forming a signal for instructing the low power consumption mode to the peripheral device which is not accessed for a predetermined period based on the held contents of the holding means. A logic (12) is included to configure a microcomputer.

At this time, it is possible to include a central processing unit (24) for shifting the corresponding peripheral device to the low power consumption mode by executing software based on the signal for instructing the low power consumption mode.

Further, terminals (P1 to P) capable of outputting the detection result of the detecting means to the microcomputer are externally output.
7) can be provided.

Further, a counter (14) for counting the number of bus accesses is provided in order to easily determine the period from when the peripheral device is no longer accessed until the signal for instructing the low power consumption mode is formed. it can.

A data processing apparatus is constituted by including the microcomputer having the above-mentioned configuration and a semiconductor memory device as a peripheral device accessible by the microcomputer.

[0014]

According to the above-mentioned means, the control logic forms a signal for instructing the low power consumption mode for the peripheral device which is not accessed for a predetermined period based on the contents held by the holding means. This achieves proper transition of the peripheral device to the low power consumption mode.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 shows a data processing apparatus including a microcomputer according to an embodiment of the present invention.

This data processing device has a system bus BU.
Via S, microcomputer 31, SDRAM
(Synchronous dynamic random access
A memory) 32, an SRAM (static random access memory) 33, a ROM (read only memory) 34, a peripheral device control unit 35, a display control unit 36, etc., are connected to each other so that signals can be exchanged, and are determined in advance. It is configured as a computer system that performs predetermined data processing according to the program. The microcomputer 31 is the logical core of this system, and mainly addresses, reads and writes information, operates data, sequences instructions, accepts interrupts, and activates information exchange between a storage device and an input / output device. It has functions such as, and is composed of an arithmetic control system, a bus control system, a memory access control system and the like. The SDRAM 32, SRAM 33, and R
The OM 34 is positioned as an internal storage device. S
Various data is stored in the DRAM 32, and a program required for calculation and control in the CPU 30 is stored in the ROM 34. The SRAM 33 is used as a main memory, a cache memory, or the like, making use of the high-speed read / write operation. The peripheral device control unit 35 controls the operation of the external storage device 38 and the information input control from the keyboard 39, and further, the display control unit 36 controls the CRT display 40 to display information. In this example system, in order to reduce power consumption,
When a peripheral device is not accessed for a predetermined period, the device is put into a low power consumption mode to reduce the power consumption of the entire system. Such control is performed by the microcomputer 31.

FIG. 2 shows a configuration example of the microcomputer 31.

As shown in FIG. 2, the microcomputer 31 is not particularly limited, but includes a bus controller 21 for bus control, an interrupt controller 23 for interrupt control, and a CPU (central processing unit) for arithmetic processing.
24, timer 25 for measuring time, and CPU2
Built-in R in which the micro program executed in 4 is stored
An OM 26, a built-in RAM 27 used as a work area for arithmetic processing in the CPU 24, and an A / D (analog / digital) converter 28 for converting an analog signal into a digital signal, which can exchange signals. To an internal bus 22. Internal bus 2
Reference numeral 2 includes an address bus for transmitting an address signal, a data bus for transmitting data, and a control bus for transmitting a control signal. The bus controller 21 uses the internal bus 22 and the system bus BU.
S is coupled to S to perform bus control for signal transmission, and as described later in detail, a signal for instructing a low power consumption mode to a peripheral device that is not accessed for a predetermined period (referred to as a low power consumption mode instruction signal) Has the function of forming. Here, the peripheral devices are not particularly limited, but SDRAM 32, SRAM 33,
The ROM 34 and the like are included. Further, the low power consumption mode instruction signal is input to the interrupt controller 23.

FIG. 1 shows a configuration example of the bus controller 21.

As shown in FIG. 1, the bus controller 21 includes, but is not limited to, a control logic 12, an access status flag register 13, a counter 14, and a bus control circuit 15.

The bus control circuit 15 generates a bus cycle for accessing a memory as a peripheral device in response to an access request from the CPU 24. That is, FIG.
Areas 0 to 7 are formed by dividing the address space supported by the CPU 24 as shown in FIG.
RAM1, SRAM2, DRAM1, DRAM2, SD
RAM1, SDRAM2, PCMCIA (IC card)
Are assigned, and the bus cycle of the peripheral device corresponding to the access request from the CPU 24 is activated. This allows access to peripheral devices without external glue logic.

Incidentally, FIG. 3 shows the CPU 2 by the address division.
4 shows a memory device that can be arranged in the address space managed by 4, and in the system to which this microcomputer 31 is applied, it does not exactly match the device that is actually combined.

The access status flag register 13 has a function as a holding means for holding the access status to the peripheral device, and has a 7-bit structure corresponding to the address division. That is, access status flag register 1
Bits 1 to 7 of 3 are ROM, SRAM1, SRAM2, and DRA as memory interfaces, respectively.
M1, DRAM2, SDRAM1, SDRAM2, PC
It supports MCIA. When each peripheral device is accessed, the bus control circuit 15 sets the flag "1" in the corresponding bit. Bits corresponding to peripheral devices that are not accessed are flag "0".
It is said.

The control logic 12 has a function of forming low power consumption mode instruction signals PD1 to PD7 for the peripheral device based on the contents held in the access state flag register 13 when there is a peripheral device which is not accessed for a predetermined period. Although it is not particularly limited, it has two-input AND gates G1 to G7 and inverters G8 to G1.
4 and 7 inputs AND gate G15 is connected. Each bit of the access status flag register 13
The output logic of 1 to bit 7 is AND gates G1 to G14.
To the corresponding inverters G8 to G1
It is input to one of the input terminals of the AND gates G1 to G7 in the subsequent stage via the input terminal 4. The overflow signal of the counter 14 is input to the other input terminal of the AND gates G1 to G7. Each bit bi of the access state flag register 13 is controlled by the AND gate G15.
The logical product of t1 to bit7 is obtained, and the counter 14 is reset by the logical product. In other words, ROM as memory interface, SRAM1, SRAM2, D
RAM1, DRAM2, SDRAM1, SDRAM2,
All of the PCMCIA are access status flag registers 13
The counter 14 is reset when all the bits bit1 to bit7 of the above are logical "1". Counter 14
Is a 10-bit counter, and is counted up each time the bus cycle is started by the bus control circuit 15. If any of the bits bit1 to bit7 of the access status flag register 13 is a logical "0", that is, if there is an area where the CPU 24 does not access, the AND gate G15.
Has an output logic of "0", the counter 14 continues to count up, and eventually reaches an overflow state. Since the logic of the overflow signal becomes "1" due to the overflow of the counter 14, the AND gates G1 to G7
Of these, the logical "0" of the access status flag register 13
The output logic of the AND gate corresponding to is "1". For example, in the state where access to area 0 has not occurred,
When the logic of bit 1 becomes "0" and the counter 14 reaches an overflow state in that state, the low power consumption mode instruction signal PD1 which is the logic output of the AND gate G1.
Is asserted high. As such, CPU2
If there is an area where access by 4 does not occur,
By asserting the low power consumption mode instruction signals PD1 to PD7 for the peripheral devices corresponding to the area, the corresponding peripheral devices are instructed to shift to the low power consumption mode.

In the system shown in FIG. 4, the SDR
AM and SRAM have one system each, and PCM
CIA (IC card) is not connected. When there is an unconnected device in this way, the corresponding bit in the access state flag register 13 is forced to be a logic "1" and is not subject to the low power consumption control.

In this embodiment, the low power consumption mode instruction signals PD1 to PD7 are input to the interrupt controller 23 shown in FIG. By asserting the low power consumption mode instruction signals PD1 to PD7, interrupt processing for shifting the corresponding peripheral device to the low power consumption mode is performed. That is, an interrupt to the CPU 24 is generated by the interrupt controller 23 due to the assertion of any of the low power consumption mode instruction signals PD1 to PD7, and when the interrupt is accepted by the CPU 24, transition to the interrupt handler is made, In the interrupt handler, transition control to low power consumption mode is performed by software. For example, this transfer control is a process of setting control data for cutting off the power supply of the main internal circuit of the corresponding memory device via the system bus BUS in a register or the like in each device. . Further, the clock synchronous memory is processed such as invalidating the input clock.

FIG. 5 shows a configuration example of the SDRAM 32.

The SDRAM 32 is not particularly limited,
It is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The memory cell array 50 has a plurality of memory mats formed by arranging dynamic memory cells in an array. An address is transmitted from the outside to the row address decoder 52 via the row address buffer 51 and is decoded there, whereby the memory cell array 5
A signal for selectively driving the 0 word line is generated. Further, a part of the address fetched from the outside is input to the column address counter 54 via the column address buffer 53. The column address counter 54 uses the input address as an initial address to generate subsequent column addresses by a step operation. The generated column address is transmitted to the column address decoder 54. This column address decoder 5
4 decodes the input address to generate an operation signal of the column selection system in the sense amplifier and column selection circuit 56. The sense amplifier and column selection circuit 56 includes a sense amplifier for amplifying a weak potential difference (memory cell data) of a data line coupled to a memory cell of the memory cell array 50, and a common I / O line (I / O).
The column address decoder 5 is also referred to as a bus).
A column selection system or the like for selectively coupling to the data line based on the control signal from 5 is included.

The memory cell data amplified by the sense amplifier is externally output via the input / output buffer 57. Further, write data from the outside is transmitted to the common I / O line via the input / output buffer 57, and written to the corresponding memory cell via the data line selected based on the column address as described above. Be done.

The controller 58 uses the basic clock CL
K, clock enable CLE, chip select signal C
S * (* means low active or signal inversion),
Row address strobe signal RAS *, column address strobe signal CAS *, write enable signal WE *
SDR based on various signals input from outside
The operation control signal of each part in AM32 is produced | generated. In particular, the operation modes of the SDRAM 32 are chip select signal CS *, row address strobe signal RAS *,
It is determined by the combination of the logical states of the write enable signal WE *. Here, when the clock enable CKE is asserted, the acquisition of the clock CLK is validated, and when the acquisition of the clock CLK is validated, each unit is operated in synchronization with the clock CLK. Therefore,
With clock enable CKE negated,
Since the clock CLK is not valid, the synchronous operation is not performed. That is, the low power consumption mode is set. In this embodiment, the clock enable CLK is negated by the interrupt processing in the low power consumption mode in the CPU 24, whereby the SDRAM 32 is shifted to the low power consumption mode.

FIG. 6 shows a configuration example of the SRAM 33.

Although not particularly limited, the SRAM 33 shown in FIG. 6 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

Reference numeral 61 is a memory cell array in which a plurality of static memory cells are arranged in a matrix, and the data line of the memory cell array 61 includes a column switch circuit 6 including a plurality of switches connected to each other in a one-to-one relationship.
It is commonly connected to the common data line through the line 4.

The high-order several bits of the address signal input from the outside are transmitted to the row address decoder 62 via the row address buffer 63 arranged corresponding thereto, and the low-order few bits are arranged correspondingly. The column address buffer 66 is transmitted to the column address decoder 65. Based on the decoded output of the row address decoder 62, the word line corresponding to the input address signal is driven to the selection level.

When a predetermined word line is driven, the memory cell connected to this word line is selected. Further, the column address decoder 65 turns on the column selection switch corresponding to the address signal supplied thereto,
It conducts to the selected complementary common data line. At this time, the potential of the complementary common data line is the data input / output circuit 67.
It is amplified by the sense amplifier included in and can be output to the outside through the output buffer. When write data is externally applied to the input buffer included in the data input / output circuit 67, the complementary common data line is driven according to the write data, whereby a predetermined memory is provided via the complementary data line selected by the address signal. Charge information corresponding to the data is stored in the cell.

Then, a chip select signal CS * and a write enable signal W as control signals given from the outside are provided.
E * and output enable signal OE * are control circuits 6
8 and the control circuit 68 generates operation control signals for each part. When the chip select signal CS * is asserted to the low level, the operation is selectively enabled. Further, in such a selected state, when the write enable signal WE * is set to the high level, the data write state to the memory cell is set, and when the write enable signal WE * is set to the low level, the memory is set. The cell data is read. The output enable signal OE * is asserted to the low level to enable the external output of the memory cell data.

Here, in order to reduce the power consumption, the sense amplifier or the like does not operate when the chip select signal CS * is negated to the high level. In this embodiment, in order to further reduce the power consumption compared to the state in which the chip select signal CS * is negated to the high level, the main components such as the row address buffer 63, the column address buffer 66, and the data input / output circuit 67 are provided. The supply of power supply voltage to the circuit is stopped. That is, the row address buffer 63 and the column address buffer 6
6, and an appropriate switch circuit is provided in the power supply voltage supply system to the data input / output circuit 67 and the like, and the operation of this switch circuit is controlled based on the control data provided from the microcomputer 31 to reduce the consumption of the SRAM 32. The power mode can be entered.

In the case of the ROM 33, the SRAM 3 is also used.
Similar to the case of 3, the power supply of the main circuit is cut off under the control of the CPU 24, whereby the low power consumption mode can be entered.

According to the above embodiment, the following operational effects can be obtained.

(1) An access state flag register 13 capable of holding an access state to a memory and a signal for instructing a low power consumption mode to a memory which is not accessed for a predetermined period are formed based on the contents held in the access state flag register 13. Since the control logic 12 is included, a signal for instructing the low power consumption mode to the memory that is not accessed for a predetermined period is obtained, so that the shift of the peripheral device to the low power consumption mode can be optimized.

(2) By including the CPU 24 that shifts the corresponding peripheral device to the low power consumption mode by executing software based on the signal for instructing the low power consumption mode, Since the corresponding peripheral device can be shifted to the low power consumption mode based on the signal, the power consumption of the computer system can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, when the interrupt controller 23 generates an interrupt to the CPU 24 due to the assertion of one of the low power consumption mode instruction signals PD1 to PD7, and the CPU 24 accepts the interrupt. The transition to the interrupt handler is performed and the shift control to the low power consumption mode is performed by software, but the shift control to the low power consumption mode can be performed by another method. For example, in FIG. 2, as indicated by P1 to P7, low power consumption mode instruction signals PD1 to P1
Seven external output terminals corresponding to D7 are provided, and the low power consumption mode instruction signal P is provided through the external output terminals P1 to P7.
If D1 to PD7 are output to the outside, the device can be shifted to the low power consumption mode by an external circuit of the microcomputer 31.

The low power consumption mode instruction signals PD1 to PD1
Based on the PD 7, a jump request to a specific address of the built-in ROM 26 may be issued, and the CPU 24 may execute the software of the jump destination to perform the transition processing of the corresponding device to the low power consumption mode. .

Further, the low power consumption mode instruction signal PD1
When the assertion of ~ PD7 is set in a built-in register that can be read by the CPU 24, and the assertion of the low power consumption mode instruction signals PD1 to PD7 is confirmed by the CPU 24 by periodically reading the storage content of this register. In addition, the process of shifting the corresponding device to the low power consumption mode may be performed by software.

In the above embodiment, the semiconductor memory is set to the low power consumption mode under the predetermined conditions, but the invention is not limited to the semiconductor memory, and various devices are set to the low power consumption mode under the predetermined conditions. be able to.

Instead of the counter 14 in the above embodiment, a plurality of counters corresponding to the bit configuration of the access status flag register 13 are provided, and the plurality of counters measure the period in which no access occurs in each of the areas 0-7. You may do it.

In the above description, the case where the invention made by the present inventor is mainly applied to a computer system which is the background of the application has been described. However, the present invention is not limited to this, and various data processing may be performed. Applicable to the device.

The present invention can be applied on the condition that at least peripheral devices are included.

[0051]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by forming a signal for instructing a low power consumption mode for a peripheral device which is not accessed for a predetermined period based on the content held by the holding means, the shift of the peripheral device to the low power consumption mode is optimized. Therefore, a microcomputer suitable for reducing the power consumption of the data processing device can be obtained.

Further, in the data processing device including the microcomputer, the microcomputer controls the shift of the peripheral device to the low power consumption mode, so that the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a configuration example of a bus controller included in a microcomputer in a computer system that is an embodiment of the present invention.

FIG. 2 is a block diagram of a configuration example of the microcomputer.

FIG. 3 is an explanatory diagram of a relationship between an area formed by address division and a memory interface corresponding to the area.

FIG. 4 is a block diagram of a configuration example of the computer system.

FIG. 5: SDRA included in the above computer system
It is a block diagram of a configuration of M.

FIG. 6 is an SRAM included in the computer system.
It is a block diagram of a structure of.

[Explanation of symbols]

 12 Control Logic 13 Access State Flag Register 14 Counter 15 Bus Control Circuit 21 Bus Controller 22 Internal Bus 23 Interrupt Controller 24 CPU 25 Timer 26 Internal ROM 27 Internal RAM 28 A / D Converter 31 Microcomputer 32 SDRAM 33 SRAM 34 ROM 35 Peripheral Device control unit 36 Display control unit 38 External storage device 39 Keyboard 40 CRT display 50, 61 Memory cell array 51, 63 Row address buffer 52, 62 Row address decoder 53, 66 Column address buffer 54 Column address counter 55 Column address decoder 56 Sense amplifier And column selection circuit 57 input / output buffer 58 controller 64 column switch circuit 65 column address decoder 67 Over data input and output circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuyoshi Yamamoto 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Shigezumi Matsui Josuimotocho, Kodaira-shi, Tokyo 5-20-1 Incorporated Hitachi, Ltd. Semiconductor Division (72) Inventor Susumu Kaneko 5-20-1 Kamisuihonmachi, Kodaira-shi, Tokyo Incorporated Hitachi Ltd Semiconductor Division

Claims (5)

[Claims] 1. In a microcomputer capable of accessing a peripheral device, holding means capable of holding an access status to the peripheral device, and holding a signal for instructing a low power consumption mode to the peripheral device which has not been accessed for a predetermined period of time is held by the holding means. A microcomputer including control logic formed based on contents. 2. In a microcomputer capable of accessing a peripheral device, holding means capable of holding an access status to the peripheral device, and holding means for holding a signal for instructing a low power consumption mode to a peripheral device which is not accessed for a predetermined period. A micro controller comprising: a control logic formed based on contents; and a central processing unit that shifts a corresponding peripheral device to a low power consumption mode by executing software based on the signal for instructing the low power consumption mode. Computer. 3. In a microcomputer capable of accessing a peripheral device, holding means capable of holding an access status to the peripheral device, and holding a signal for instructing a low power consumption mode to a peripheral device which has not been accessed for a predetermined period of time is held by the holding means. A microcomputer comprising: a control logic formed based on contents; and a terminal capable of outputting a detection result of the detection means to an external device. 4. The microcomputer according to claim 1, further comprising a counter that determines the predetermined period by counting the number of bus accesses. 5. A data processing apparatus comprising the microcomputer according to claim 1 and a semiconductor memory device as a peripheral device accessible by the microcomputer.