JP4586645B2 - Control circuit, information processing apparatus, and control method - Google Patents

Description

  The present invention relates to a control circuit for controlling an access target apparatus accessible by a central processing unit, an information processing apparatus including the control circuit, and a control method.

  Currently, techniques for suppressing power consumption are widespread in information processing apparatuses such as personal computers (see, for example, Patent Document 1 and Patent Document 2).

  According to the technique of Patent Document 1, a CPU having a stop clock signal for reducing the power consumption of the CPU by stopping the internal clock of the CPU is provided, and the stop clock signal is asserted at regular intervals. The apparent operating speed of the CPU is reduced and the current consumption of the CPU is reduced.

Further, according to the technique of Patent Document 2, the power consumption is reduced by lowering the clock frequency to a bus with low access frequency.
Japanese Patent Laid-Open No. 8-328684 JP 2000-66654 A

  In the information processing apparatus, the boot code stored in the startup disk is read at the time of booting and the OS is loaded into the memory. The device storing this boot code is accessed after being accessed by the CPU at the time of booting. Despite not being accessed, power supply continues. Although the power consumption can be reduced by the above-described conventional technology, the power supply to the device without access by the CPU is continuously executed. Therefore, the CPU is simply supplied with power to the information processing apparatus main body. There is a problem that power is consumed even when the process according to the above is not executed.

  SUMMARY An advantage of some aspects of the invention is that it provides a control circuit, an information processing apparatus, and a control method capable of reducing power consumption.

The control circuit according to claim 1 includes a measuring unit that measures a time elapsed since a previous access signal was output from a central processing unit that performs various data processing to an access target device accessible by the central processing unit, and the measurement Stop control means for controlling the power supply means to stop the power supply to the access target apparatus by the power supply means for supplying power to the access target apparatus when a predetermined time is measured by the means Detecting means for detecting that a chip select signal indicating that the access target device is an access target is output from the central processing unit to the access target device whose power supply is stopped; When the chip select signal is detected by the detecting means, the central processing unit is connected to the access target from the central processing unit. The power supply means is controlled to start power supply to the access target device after the standby state for waiting for access to the device, and the central processing is performed after power supply to the access target device is started. Start control means for releasing the standby state of the apparatus .

  The measuring means of the control circuit according to claim 1 has elapsed since the last access signal was output from a central processing unit such as a CPU that performs various data processing to an access target device such as a peripheral device accessible by the central processing unit. Time. The stop control means sends the access target device to stop the power supply to the access target device when a predetermined time is measured as a time elapsed since the last access signal was output by the measuring means. The power supply means for supplying power is controlled.

  In this way, the power supply means for supplying power to the access target device can be controlled so that the power supply from the central processing unit to the access target device that has not been accessed for a predetermined time can be controlled. Power to be reduced.

Further , when a chip select signal is output from the central processing unit to the access target device, power supply to the access target device is started, and when there is no output of the access signal from the central processing unit to the access target device, Since the power supply to the access target device can be stopped, the power consumed by the access target device can be effectively reduced.

The control circuit according to claim 2 is the control circuit according to claim 1 , wherein when the predetermined time is measured by the measurement unit, the start control unit is configured to execute the central processing unit and the access target device. The switching means for switching between the state in which the signal cannot be exchanged or the state in which the signal can be exchanged is controlled so that the signal cannot be exchanged, and when the chip select signal is detected by the detection means, After setting the central processing unit to the standby state, the power supply unit is controlled to start power supply to the access target device and the switching unit is controlled to be in a state where the signal can be exchanged, After the power supply to the access target device is started and the central processing unit and the access target device are switched to a state in which signals can be exchanged, the center Releasing the waiting state of the management device.
For this reason, it is possible to prevent a signal from being input to the access target device when power supply to the access target device is stopped.

Further, it is possible when the power supply to the access target device is started, to control the central processing unit so as to allow access to the access target device.

As shown in claim 3 , the control circuit according to claim 1 or 2 is provided in an information processing apparatus including a central processing unit, an access target device, and power supply means. Thus, it is possible to provide an information processing apparatus that can efficiently reduce power consumption.

Note that the power consumed by the access target device can be reduced by the following control method. Specifically, the control method according to claim 4 is a measuring step of measuring a time elapsed since the last access signal was output from a central processing unit that performs various data processing to an access target device accessible by the central processing unit. And a stop control step of controlling the power supply means to stop the power supply to the access target device by the power supply means for supplying power to the access target device when a predetermined time is measured. And a detection step of detecting that a chip select signal indicating that the access target device is an access target is output from the central processing unit to the access target device whose power supply has been stopped, and When a chip select signal is detected, the central processing unit waits for access from the central processing unit to the access target device. Then, the power supply means is controlled to start power supply to the access target device, and after the power supply to the access target device is started, start to release the standby state of the central processing unit And a control step .

  The control circuit, the information processing apparatus, and the control method according to the present invention include a power supply unit that supplies power to the access target apparatus so as to stop power supply from the central processing unit to the access target apparatus that has not been accessed for a predetermined time. Since it can be controlled, the power consumed by the access target device can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  As illustrated in FIG. 1, the information processing apparatus 10 includes a CPU 12 as a central processing unit for controlling the entire information processing apparatus 10, a bus controller 14, a device 18, and a power supply circuit 26 for supplying power to the device 18. , A power detection circuit 28 for detecting that power is supplied from the power supply circuit 26 to the various devices 18, and a power control circuit 30 for controlling power supply from the power supply circuit 26 to the device 18 and power supply stoppage. And a control circuit 24 for controlling the device 18.

  An example of the device 18 includes various devices such as a nonvolatile memory and a volatile memory. The device 18 includes a plurality of types of devices. In the present embodiment, the device 18 includes a plurality of types of devices. It will be described as including.

  The CPU 12 is connected so as to be able to exchange data and commands with the bus controller 14 via a bus 16 such as a data bus or an address bus. The bus controller 14 is connected to the device 18 via the bus 20 via the bus release buffer 22 so as to be able to exchange data and commands. The control circuit 24 is connected to the bus controller 14, the bus release buffer 22, the device 18, the power supply detection circuit 28, and the power supply control circuit 30 so as to be able to exchange data and commands. The power supply circuit 26 is connected so as to be able to supply power to the device 18, and is connected to the control circuit 24 through the power supply control circuit 30 and the power supply detection circuit 28 so as to be able to exchange data and commands.

  The bus controller 14 exchanges data and commands with the device 18 via the bus 20 based on the access signal input from the CPU 12, and the control circuit 24 based on the access signal input from the CPU 12. Send and receive data and commands.

  The control circuit 24 mainly controls the bus controller 14, the bus release buffer 22, the power supply control circuit 30, and the device 18 based on an access signal input from the CPU 12 via the bus controller 14 (details will be described later).

  The power supply circuit 26 supplies power to the device 18, and power supply to the device 18 or power supply stoppage is controlled by the control of the power supply control circuit 30 by the control circuit 24.

  The power detection circuit 28 detects that power is supplied from the power supply circuit 26 to the device 18, and outputs a reset signal indicating the start of power supply to the control circuit 24 when power supply to the device 18 is detected. .

  The bus release buffer 22 switches the bus 20 to either the High-Z state or the drive state under the control of the control circuit 24. Specifically, the bus release buffer 22 sets the bus 20 in a High-Z state or a drive based on an output enable (/ OE) signal (hereinafter referred to as an / OE signal) input from the control circuit 24. Switch to one of the states. Specifically, when the / OE signal is at a low level (when the / OE signal is asserted), the bus 20 is in a drive state, and the bus controller 14 and the device 18 are connected to be able to exchange data and signals. State (drive state). On the other hand, when the / OE signal is at a high level (when the / OE signal is negated), the bus 20 is in a High-Z state, and the bus controller 14 and the device 18 are in a state in which data and signals cannot be exchanged. Become.

  Next, processing executed by the control circuit 24 will be described.

  The control circuit 24 measures the time that has elapsed since the last access signal was output from the CPU 12 to the device 18, and repeats negative determination until the measurement time exceeds a predetermined time. Based on the determination in step 100, it is possible to determine whether or not the CPU 12 has not accessed the device 18 for a predetermined time.

  The predetermined time may be stored in the control circuit 24 in advance. The predetermined time may be changed by an operation by a user of a user interface (not shown) connected to the bus 16 so as to be able to exchange data. Moreover, you may make it change by the change instruction | indication by CPU12.

  Note that the time elapsed since the last access signal was output from the CPU 12 to the device 18 may be measured by using a timer for measuring time in the control circuit 24. Alternatively, measurement may be performed using a timer built in the CPU 12 or a soft program timer. If a timer built in the CPU 12 is used, the control circuit 24 can be downsized.

  In step 102, it is determined whether power supply to the device 18 can be stopped. In step 102, information indicating that the power supply to the device 18 can be stopped is stored in the control circuit 24 in advance, and it is determined whether or not this information is stored. Judgment is possible. Information indicating that the power supply to the device 18 can be stopped may be changed by an operation instruction by a user of a user interface (not shown) or by control of the CPU 12. Information indicating that the power supply to the device 18 can be stopped may be set by a dip switch (not shown) provided in the information processing apparatus 10 main body. In this case, the determination in step 102 can be made by determining the state of the dip switch.

  In the next step 104, the / OE signal is asserted to the bus release buffer 22. By the processing in step 104, the bus 20 is in a High-Z state, and the bus controller 14 and the device 18 are unable to exchange data or signals.

  In the next step 106, the power supply control circuit 30 is controlled so as to stop the power supply to the device 18, and then this routine is terminated. Under the control of the power supply control circuit 30, the power supply from the power supply circuit 26 to the device 18 is stopped.

  By executing the processing from step 100 to step 106, the power supply to the device 18 that has not been accessed by the CPU 12 for a predetermined time or more is stopped, and the bus controller 14 and the device 18 exchange data and signals. It becomes impossible.

  Next, when the power supply to the device 18 that has not been accessed by the CPU 12 for a predetermined time or more is stopped by executing the processing from the step 100 to the step 106, the processing routine shown in FIG. The process proceeds to step 200.

  In step 200, the negative determination is repeated until the CPU 12 is accessed to the device 18 whose power supply has been stopped. The determination in step 200 can be made by determining whether an access signal is input from the CPU 12 to the bus controller 14 and a signal based on the access signal is input from the bus controller 14. The signal based on the access signal input from the bus controller 14 includes a chip select signal (hereinafter referred to as a / CS signal) indicating a device to be accessed by the CPU 12, and a signal for instructing reading or writing of the device (hereinafter referred to as a “device”) / RW signal) and (/ OE signal).

  In step 202, the Wait signal is asserted to the bus controller 14. Since the Wait signal is asserted to the bus controller 14 by the process of step 202, the access to the device 18 by the CPU 12 is in a standby state.

  In the next step 204, an instruction signal for starting power supply to the device 18 whose power supply has been stopped is output to the power supply control circuit 30. When an instruction signal for starting power supply to the device 18 is input, the power supply control circuit 30 controls the power supply circuit 26 to start power supply to the device 18. By the processing in step 204, power supply to the device 18 is started.

  In the next step 206, negative determination is repeated until a reset signal indicating that power supply from the power supply circuit 26 to the device 18 has been started is input from the power supply detection circuit 28.

  In step 208, the bus release buffer 22 (bus 20) is transitioned from the High-Z state to the drive state by asserting the / OE signal to the bus release buffer 22.

  In the next step 210, the / CS signal input in step 200 is asserted to the device 18.

  By executing the processing of step 208 and step 210 described above, the bus 20 that has been changed to the High-Z state is changed to the drive state, and the / CS signal is driven from the control circuit 24 to the device 18. . For this reason, the signal excluding the address signal and the / CS signal among the access signals input from the CPU 12 to the bus controller 14 in the processing of step 200 via the bus 20 from the bus controller 14 to the device 18 is sent to the device 18. Asserted.

  In the next step 212, a negative determination is repeated until a predetermined access time of the device 18 elapses.

  The predetermined access time is a time required for access such as reading or writing in the device 18, and is measured and set in advance.

In the next step 214, the wait state of the CPU 12 is canceled by negating the Wait signal to the bus controller 14.

  In the next step 216, after the / CS signal to the device 18 is negated at the timing when the bus controller 14 negates the / CS signal, this routine is finished.

  As described above, according to the information processing apparatus 10 of the present invention, the power supply to the device 18 is stopped when there is no access from the CPU 12 to the device 18 for a predetermined time or more, so that power consumption can be reduced. it can.

  Further, when the CPU 12 has not accessed the device 18 for a predetermined time or longer, the bus 20 that connects the bus controller 14 and the device 18 so as to be able to exchange data and signals can be switched from the drive state to the High-Z state. The device 18 can be prevented from being broken.

  If access from the CPU 12 to the device 18 occurs when power supply to the device 18 is stopped, the control circuit 24 sets the CPU 12 in a standby state and starts supplying power to the device 18. Since the standby state of the CPU 12 is released after switching from the Z state to the drive state and the access time of the device 18 elapses, the device 18 is prevented from being destroyed, and only when the access by the CPU 12 occurs. The power supply can be started to enable access by the CPU 12.

  Note that the information processing apparatus according to the present invention is not limited to the above-described configuration of the information processing apparatus as long as it has a configuration for realizing the present invention.

It is a block diagram which shows the structure of the information processing apparatus which concerns on embodiment of this invention. 4 is a flowchart illustrating processing executed by a control circuit 24 when power supply to a device is stopped. 6 is a flowchart illustrating processing executed by a control circuit when an access to a device occurs from a CPU after stopping power supply to the device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Information processing apparatus 14 Bus controller 24 Control circuit 26 Power supply circuit 28 Power supply detection circuit 30 Power supply control circuit

Claims (4)

Measuring means for measuring the time elapsed since the last access signal was output from the central processing unit performing various data processing to the access target device accessible by the central processing unit;
A stop for controlling the power supply means to stop the power supply to the access target device by the power supply means for supplying power to the access target device when a predetermined time is measured by the measurement means. Control means;
Detecting means for detecting that a chip select signal indicating that the access target device is an access target is output from the central processing unit to the access target device whose power supply is stopped;
When the chip selection signal is detected by the detection means, the central processing unit is placed in a standby state for waiting for access from the central processing unit to the access target device, and then the power supply to the access target device is performed. Start control means for controlling the power supply means to start, and releasing the standby state of the central processing unit after power supply to the access target device is started;
Control circuit with. The start control means includes
Switching means for switching between the central processing unit and the access target device to a state in which a signal cannot be exchanged or a state in which a signal can be exchanged when the predetermined time is measured by the measurement means; Control it to be impossible,
When the detection unit detects the chip select signal, the power supply unit is controlled to start the power supply to the access target device after the central processing unit is set to the standby state, and the signal After controlling the switching means so as to be in a state where it can be transmitted and received, after power supply to the access target device is started and switching between the central processing unit and the access target device into a state where signals can be transmitted and received , Canceling the standby state of the central processing unit,
The control circuit according to claim 1 . The control circuit according to claim 1 or 2 ,
The central processing unit;
The access target device;
The power supply means;
An information processing apparatus comprising: A measurement process for measuring the time elapsed since the last access signal was output from the central processing unit that performs various data processing to the access target device accessible by the central processing unit,
A stop control step of controlling the power supply means to stop the power supply to the access target device by the power supply means for supplying power to the access target device when a predetermined time is measured;
A detection step of detecting that a chip select signal indicating that the access target device is an access target is output from the central processing unit to the access target device whose power supply is stopped;
When the chip select signal is detected, the central processing unit is placed in a standby state for waiting for access from the central processing unit to the access target device, and then power supply to the access target device is started. A start control step of controlling the power supply means and releasing the standby state of the central processing unit after power supply to the access target device is started;
Control method.