JP5244759B2 - Information processing apparatus and image forming apparatus - Google Patents

Description

  The present invention relates to an information processing apparatus and an image forming apparatus.

  In an electronic device, a technique for saving power by stopping clock supply to a circuit module that does not need to operate has been proposed (for example, see Patent Documents 1 and 2).

  In particular, in the technique described in Patent Document 1, when data to be processed is received, clock supply to the circuit module is resumed. Thus, by stopping only the clock supply without shutting off the power to the circuit module, when data to be processed is generated, the processing of the data can be started in a relatively short time.

JP 2006-276979 A JP 2005-050030 A

  However, in the above-described technology, even if the clock supply is stopped, the power supply of the circuit module is not shut off, so that power consumption still occurs in the circuit module. Further, in the above-described technology, if a circuit module that does not need to be operated is turned off, a certain period is required until it becomes operable after the power is restored. Therefore, it becomes difficult to start processing the data in a relatively short time, and an operation delay occurs in the circuit module.

  The present invention has been made in view of the above problems, and an object thereof is to obtain an information processing apparatus and an image forming apparatus that can further reduce power consumption in a circuit module while avoiding occurrence of operation delay. To do.

  In order to solve the above problems, the present invention is configured as follows.

An information processing apparatus according to the present invention includes a plurality of modules each having a data processing circuit, a bus, an arbitrator that gives a right to use the bus to any one of the plurality of modules, and an arbitration among the plurality of modules. And a power management unit that shuts off the power supply of the module that is not given the right to use. Then, on the arbitration schedule of the arbiter, the power management unit restores the power of the module more than a predetermined time before the time when the right to use is given to the module that has cut off the power. This predetermined time is the time required for the module to become operable after the power of the module is restored.

Thereby, since the power supply of the module which does not operate immediately after the use right is not given by the arbiter, the power consumption in the circuit module can be further reduced while avoiding the occurrence of the operation delay. In addition, since the power is restored according to the start time of the operation of the module, it is possible to reliably avoid the occurrence of the operation delay of the module.

The information processing apparatus according to the present invention, in addition to the above information processing equipment, may be as follows. In this case, the information processing apparatus includes a processor that issues operation commands for a plurality of modules. Then, when the module to which the operation command is issued from the processor is a module whose power is cut off, the power management unit supplies the operation command to the module after returning the power of the module.

  Thereby, it can be avoided that the operation command is lost without being normally received by the module.

  An information processing apparatus according to the present invention may be as follows in addition to any of the information processing apparatuses described above. In this case, if the module for which the operation command is issued from the processor is a module whose power is cut off, the power management unit operates on the module after a predetermined time has elapsed since the power of the module was restored. Supply directives. This predetermined time is the time required for the module to become operable after the power of the module is restored.

  As a result, the module does not start to operate in an excessive state after the power is restored, and thus the module operates normally.

  An information processing apparatus according to the present invention may be as follows in addition to any of the information processing apparatuses described above. In this case, the information processing apparatus includes a processor that issues operation commands for a plurality of modules. Then, the power management unit determines that a module that is not currently in operation and for which an operation command has not been issued from the processor is a module that is not given the right to use by the arbitrator, and shuts off the power of the module.

  An image forming apparatus according to the present invention includes any one of the information processing apparatuses described above, and each of the plurality of modules executes image processing.

  According to the present invention, in the information processing apparatus and the image forming apparatus, it is possible to further reduce power consumption in the circuit module while avoiding occurrence of operation delay.

FIG. 1 is a block diagram showing the configuration of the information processing apparatus according to the embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a bandwidth of a bus used by a module when the priority of bus use of a plurality of modules is the same in the first embodiment and one module cannot occupy the bus. FIG. 3 is a diagram illustrating an example of a bandwidth of a bus used by a module when the priority of bus use of a plurality of modules is the same in the second embodiment and one module cannot occupy the bus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.

  FIG. 1 is a block diagram showing the configuration of the information processing apparatus according to the embodiment of the present invention. For example, the information processing apparatus is built in an image forming apparatus such as a printer, a copier, or a multifunction peripheral. This device is configured as an integrated circuit, for example.

  In FIG. 1, the plurality of modules 1-1 to 1-3 each have a data processing circuit. For example, the modules 1-1 to 1-3 access the memory controller 8 via the bus 3 and read / write data from / to the memory 9 when the arbitrator 2 is given the right to use the bus 3. . When the information processing apparatus is built in the image forming apparatus, the module 1-i has a data processing circuit that performs image processing. In this embodiment, three modules 1-1 to 1-3 are provided, but the number of modules is not limited to three.

  The arbiter (arbiter) 2 is a circuit that gives the right to use the bus 3 to one or a plurality of modules 1-1 to 1-3.

  The switches 4-1 to 4-3 are provided between the modules 1-1 to 1-3 and the power supply 5, and according to the power control signal from the power management unit 6, the modules 1-1 to 1-3 are arranged. The power supply 5 is connected to each.

  The power management unit 6 opens and closes the switches 4-1 to 4-3 to control connection and disconnection of the power sources of the modules 1-1 to 1-3, and sets the startup timing of the modules 1-1 to 1-3. It is a circuit that controls independently.

  The power management unit 6 shuts off the power of the module 1-i (i = 1, 2, 3) to which the right of use is not given by the arbiter 2. In this embodiment, the power management unit 6 controls the switch 4-i with the power control signal before the module 1-i whose power has been cut off is given the right to use by the arbiter 2, and the module 1-i. Restore the power of i. In this embodiment, the power management unit 6 monitors the arbitration schedule of the arbiter 2 (that is, the schedule that gives the right to use the bus 3 to the modules 1-1 to 1-3). When it is determined that the right to use is given to the module 1-i that has cut off the power, the power of the module 1-i is restored.

  Further, the power management unit 6 activates the modules 1-1 to 1-3 with the activation control signal. Each module 1-i is not supplied with a clock signal in a state in which a power supply is connected but not activated, and is in an operation stop state. When activated by an activation control signal, each module 1-i is supplied with a clock signal, Start operation.

  A CPU (Central Processing Unit) 7 is a processor that operates according to a control program (not shown) and issues operation commands for the modules 1-1 to 1-3. This operation command is a command for starting the modules 1-1 to 1-3 and executing predetermined data processing. Further, this operation command is first supplied to the power management unit 6, and at the timing determined by the power management unit 6, the activation control signal is sent to the module 1-j (j = 1, 2, 3) designated by the CPU 7. As supplied from the power management unit 6.

  The memory controller 8 is a circuit that is connected to the bus 3 and reads / writes data from / to the memory 9 in accordance with data and commands supplied via the bus 3. The modules 1-1 to 1-3 can perform data reading / writing on the memory 9 only during a period when the right to use the bus 3 is given by the arbiter 2.

  Next, the operation of the above apparatus will be described.

  Based on the arbitration schedule of the arbiter 2, the power management unit 6 has a higher priority for the module to which the current bus use right is given, and is assigned to another module (that is, the module to which the current bus use right is not given). When it is determined that the right to use the bus is not given, the power supply of the module is cut off at the time of the determination. The arbitration schedule includes information such as the presence / absence of bus usage rights of modules 1-1 to 1-3, the priority of bus usage, the amount of data to be transmitted / received, and the period (timing and time length) during which usage rights are given.

  Thereafter, the power management unit 6 monitors the arbitration schedule of the arbiter 2, and when it is determined on the arbitration schedule that the right to use is given to the module 1-i that has shut off the power, the module 1-i. Restore the power supply.

  Next, a specific example of shutting down and restoring the power supply of the module will be described.

(A) When the priority of bus use of module 1-1 is high and module 1-1 can occupy bus 3

  When the priority of the bus usage of the module 1-1 is high and the module 1-1 can occupy the bus 3, the arbiter 2 gives the bus usage right to the module 1-1. In the initial state, none of the modules 1-1 to 1-3 is activated. When the power management unit 6 receives an operation command for the module 1-1 from the CPU 7, the power management unit 6 activates the module 1-1 and shuts off the power of the modules 1-2 and 1-3.

  Thereafter, when the CPU 7 issues an operation command for the module 1-3, the power management unit 6 holds the operation command without starting the module 1-3 at that time, monitors the arbitration schedule of the arbiter 2, When the time required for completing the data transmission / reception processing of the module 1-1 is the same as the time required for the module 1-3 to be operable (startable) from the time of power connection, the module 1- 3 is connected, the processing of the module 1-1 is completed, and the module 1-3 is activated when the bus use right is given to the module 1-3. Therefore, the module 1-3 starts its operation immediately when the bus use right is given.

  Note that the time point when the power supply of the module 1-3 is connected is the time when the amount of data to be transmitted / received by the module 1-1 falls below a predetermined amount, that is, the remaining amount of data to be transmitted / received by the module 1-1 The time required for this is the time when the module 1-3 is substantially the same as the time required for the module 1-3 to be operable (startable) from the time of power connection. Alternatively, when the power supply of the module 1-3 is connected, the time until the end time of the bus use period assigned to the module 1-1 is operable (startable) from the power supply connection time of the module 1-3. It is assumed that it is almost the same as the time required to become.

  When the processing of the module 1-1 is completed, the power management unit 6 stops the supply of the clock signal to the module 1-1 with the activation control signal.

(B) When the bus usage priority of modules 1-1 to 1-3 is the same and one module cannot occupy the bus 3

  When the bus usage priority of the modules 1-1 to 1-3 is the same, and the right to use the bus is given in order by the round robin method or the like, and one module cannot occupy the bus 3, the power management unit 6 In the idle state, the power supply of the modules 1-1 to 1-3 is set to the connected state, and the supply of the clock signal is stopped without starting the modules 1-1 to 1-3 without the operation command from the CPU 7. And

  When the power management unit 6 receives the operation command for the module 1-1 from the CPU 7 and immediately receives the operation command for the module 1-3, the power management unit 6 first activates the module 1-1 and operates the module 1-3. It is possible to hold the command, determine whether the module 1-3 can be operated in parallel with the module 1-1, and operate the module 1-3 in parallel with the module 1-1. In such a case, the module 1-3 is activated, and when the module 1-3 cannot be operated in parallel with the module 1-1, the power supply of the module 1-3 is cut off.

  FIG. 2 shows the modules 1-1 to 1-1 in the case where the priorities of bus use of the plurality of modules 1-1 to 1-3 are the same in the first embodiment and one module cannot occupy the bus 3. 3 is a diagram illustrating an example of a bandwidth of a bus 3 used by 3. FIG. As shown in FIG. 2, according to the arbitration schedule in this case, the amount of data that the module 1-1 should complete transmission / reception by time T is the product of the entire bandwidth (transmission speed) of the bus 3 and time T. If the data amount that the module 1-3 should complete transmission / reception by the time 2T is 60% of the product of the entire bandwidth (transmission speed) of the bus 3 and the time T, the module 1-1 If 80% of the bandwidth of the bus 3 is used, the data transmission / reception processing can be completed by the time T, so that the remaining bandwidth of 20 percent can be allocated to the module 1-3. Therefore, in this case, the power management unit 6 determines that the module 1-3 can be operated in parallel with the module 1-1, and activates the module 1-3.

  As described above, the information processing apparatus according to the first embodiment includes a plurality of modules 1-1 to 1-3 each having a data processing circuit, a bus 3, and a plurality of modules 1-1 to 1-3. An arbiter 2 that gives the right to use the bus to one or more of them, and a power management unit 6 that cuts off the power of the module 1 -i that is not given the right to use by the arbiter 2.

  As a result, the power supply of the module 1-i that does not operate immediately after the use right is not given by the arbiter 2 is cut off, so that it is possible to further reduce the power consumption in the circuit module while avoiding the occurrence of an operation delay. it can.

Embodiment 2. FIG.

  The information processing apparatus according to the second embodiment has a configuration similar to that of the information processing apparatus according to the first embodiment (FIG. 1), and the power management unit 6 includes (B) modules 1-1 to 1-3. When the priority of bus use is the same and one module cannot occupy the bus 3, the operation is as follows.

  In the second embodiment, similarly, in this case, the power management unit 6 is in a state in which the power sources of the modules 1-1 to 1-3 are connected in the idle state, and there is no operation command from the CPU 7. The supply of the clock signal is stopped without starting 1 to 3.

  When the power management unit 6 receives the operation command for the module 1-1 from the CPU 7 and immediately receives the operation command for the module 1-3, the power management unit 6 first activates the module 1-1 and operates the module 1-3. If it is determined that the data transmission / reception process of the module 1-3 is completed by the designated time even if the module 1-3 is started after the data transmission / reception process of the module 1-1 is ended after the instruction is suspended, the module 1- Even if 3 can be operated in parallel with the module 1-1, the power supply of the module 1-3 is immediately cut off. Thereafter, the power supply management unit 6 connects the power supply of the module 1-3 at the appropriate timing described above so that the module 1-3 can be started immediately after the data transmission / reception processing of the module 1-1 is completed. When the data transmission / reception process 1 is completed, the module 1-3 is activated immediately.

  FIG. 3 shows the modules 1-1 to 1-1 in the case where the priorities of bus use of the plurality of modules 1-1 to 1-3 are the same in the second embodiment and one module cannot occupy the bus 3. 3 is a diagram illustrating an example of a bandwidth of a bus 3 used by 3. FIG. As shown in FIG. 3, according to the arbitration schedule in this case, the amount of data that the module 1-1 should complete transmission / reception by time T is the product of the total bandwidth (transmission speed) of the bus 3 and time T. If the data amount that the module 1-3 should complete transmission / reception by the time 2T is 60% of the product of the entire bandwidth (transmission speed) of the bus 3 and the time T, the module 1-1 The data transmission / reception processing is completed by time T, and the module 1-3 can execute transmission / reception processing of the data amount in the period from time T to time 2T. For this reason, in this case, when the power management unit 6 receives the operation command of the module 1-3 from the CPU 7, the power supply of the module 1-3 is cut off, and then the activation of the module 1-3 at time T is in time. Thus, the power supply of the module 1-3 is restored.

  As described above, according to the second embodiment, the frequency with which the power supply of the module is cut off is higher than that in the first embodiment. Therefore, the power consumption in the circuit module is further reduced while avoiding the occurrence of operation delay. can do.

  Each embodiment described above is a preferred example of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. It is.

  For example, in each of the above embodiments, the power management unit 6 determines that a module that is not currently in operation and for which an operation command has not been issued from the CPU 7 is a module for which the right of use is not given by the arbiter 2, You may make it cut off the power supply of the module.

  The present invention can be applied to, for example, reducing power consumption of circuit modules in an image forming apparatus such as a printer, a copier, and a multifunction peripheral.

1-1 to 1-3 Multiple modules 2 Arbiter 3 Bus 6 Power management unit 7 CPU (an example of processor)

Claims (5)

A plurality of modules each having a data processing circuit;
With bus,
An arbiter that gives the right to use the bus to any of the plurality of modules;
Among the plurality of modules, a power management unit that shuts off the power of the module that is not given a usage right by the arbiter,
Equipped with a,
The power management unit, on the arbitration schedule of the arbiter, restores the power of the module more than a predetermined time before the time when the right to use is given to the module that has cut off the power,
The predetermined time is a time required for the module to be in an operable state from the time when the power of the module is restored;
An information processing apparatus characterized by the above. A processor for issuing operation commands for the plurality of modules;
The power management unit is configured to supply the operation command to the module after the power of the module is restored when the module to which the operation command is issued from the processor is a module in which the power is cut off;
The information processing apparatus according to claim 1 . When the module to which the operation command is issued from the processor is a module that cuts off the power, the power management unit is configured to operate the module after a predetermined time has elapsed since the power of the module was restored. Supply
The predetermined time is a time required for the module to be in an operable state from the time when the power of the module is restored;
The information processing apparatus according to claim 2 . A processor for issuing operation commands for the plurality of modules;
The power management unit determines that a module that is not currently in operation and for which an operation command has not been issued from the processor is a module that is not given a right to use by the arbitrator, and shuts off the power of the module. ,
The information processing apparatus according to claim 1. An information processing apparatus according to any one of claims 1 to 4 , comprising:
Each of the plurality of modules executes image processing;
An image forming apparatus.

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