JP2008097093A - Processor system and communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor system and a communication device that enable a master processor to obtain the status of a slave processor. <P>SOLUTION: The communication device comprises, a so-called master/slave configuration including a slave processor 11, an integration circuit 12 and a master processor 13. The slave processor 11 sends a task start status signal to the integration circuit 12. The integration circuit 12 converts the received task start status signal by integration, and sends the integration result signal to the master processor 13. The master processor 13 receives the integration result signal to determine the task start status. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a processor system and a communication device, and more particularly to a processor system and a communication device having a processor load state monitoring function.

  Generally, in a communication apparatus equipped with a processor system having a master processor and a slave processor, the master processor operates the slave processor by communication. In program control using a multitasking operating system (hereinafter abbreviated as multitasking OS), for example, tasks are divided into functions such as communication control tasks and power control tasks, and programs are controlled with priorities assigned to them. There are many cases. In this case, when a plurality of tasks operate collectively, the tasks are executed in order from the task with the highest priority, and the load on the CPU increases. Therefore, when a task having a higher priority than the communication control task is activated, communication control cannot be performed in response to a request from the master processor (response cannot be returned to the master processor). In order to solve this problem, a means to notify the status from the slave processor to the master processor is required. However, in the conventional method, the master processor and the slave processor having terminals indicating the communicable status are connected. By realizing the connection, the master processor often knows the status of the slave processor.

  Hereinafter, the prior art of Patent Document 1 will be described with reference to FIGS. 8, 9, 10, and 11.

  Initially, the structure of the communication apparatus concerning the said prior art is demonstrated using FIG.

  The master processor 81, the slave processor 82, and the slave processor 83 are connected to each other by a master ready line 84b and a slave ready line 84c provided in the common bus 84. The master processor 81 is connected to the master ready line 84b by its own. Gives the operating state (master operating state). On the other hand, the slave processor 82 and the slave processor 83 give their own operation state (slave operation state) to the slave ready line. The master processor 81 knows the operation state of the slave processor by monitoring the slave ready line 84c, and the slave processor 82 and the slave processor 83 monitor the master ready line 84b and the slave ready line 84c, thereby Know the operating status of other slave processors.

  Next, processing in the communication apparatus according to the related art will be described.

  When the power is turned on, the microprocessor (MPU) 81a on the master processor 81 resets the master flip-flop (MF / F) 81b with an initialization signal. By this reset, a master inactive signal is transmitted from the master flip-flop 81b, and the driver 81c drives the master ready line 84b inactive.

  Similarly, in the slave processor 82 and the slave processor 83, when the power is turned on, the microprocessor 82a and the microprocessor 83a reset the slave flip-flop (SF / F) 82b and the slave flip-flop (SF / F) 83b, respectively. By this reset, the first and second slave inactive signals are transmitted from the slave flip-flop 82b and the slave flip-flop 83b, respectively, and the driver 82c and the driver 83c drive the slave ready line 84c inactive.

  The slave processor 82 and the slave processor 83 recognize that the master ready line 84c is inactive by the receiver 82d and the receiver 83d, respectively. After the power is turned on, the microprocessor 82a and the microprocessor 83a have the master ready line 84c active. Waiting to become. That is, it is in a standby state.

  On the other hand, in the master processor 81, the microprocessor 81a sets the master flip-flop 81b. As a result, the master flip-flop 81b transmits a master active signal, and the driver 81c actively drives the master ready line 84b.

  In the slave processor 82, when the microprocessor 82a recognizes that the master ready line 84b is active via the receiver 82d, the slave processor 82 starts processing. Similarly, the slave processor 83 notifies the microprocessor 83a through the receiver 83d that the master ready line 84b is active, and starts processing.

  When the processing of the slave processor 82 and the slave processor 83 is completed, the microprocessor 82a and the microprocessor 83a set the slave flip-flop 82b and the slave flip-flop 83b to the set state. As a result, the slave flip-flops 82b and 83b transmit an active signal, and the drivers 82c and 83c drive the slave ready line 84c actively. However, when either one is processing, the driver 82c or driver 83c that is processing is driving the slave ready line 84c inactive. Therefore, the slave ready line 84c remains in an inactive state until all slave processors have completed processing, and in the master processor 81, the microprocessor 81a recognizes that the slave ready line 84c is inactive by the receiver 81d. The slave processor 82 does not access other processors.

  When all the slave processors complete the processing, the master processor 81 recognizes that the slave ready line 84c is activated by the receiver 81d. Similarly, in the slave processor 82 and the slave processor 83, it is recognized by the receiver 82e and the receiver 83e that the slave ready line 84c is activated, and access to other processors becomes possible.

  During operation, for example, when a failure occurs in the slave processor, the microprocessor 82a and the microprocessor 83a reset the slave flip-flop 82b and the slave flip-flop 83b. As a result, the slave flip-flops 82b and 83b transmit an inactive signal, and the driver 82c and the driver 83c drive the slave ready line 84c inactive. As a result, the master processor 81 recognizes by the receiver 81d that the microprocessor 81a has inactivated the slave ready line 84c. That is, it is recognized that a failure has occurred in the slave processor 82 or the slave processor 83.

  Next, problems of the communication apparatus according to the related art will be described.

  As described above, the master processor controls the slave processor according to the slave ready signal. When the slave processor uses a multitask OS, the slave flip-flop (hereinafter abbreviated as SF / F) output. The timing at which the master processor is controlled may be different from the timing at which the original control is performed, and it becomes difficult for the master processor to know the state of the slave processor only by the slave ready line.

  Hereinafter, a mechanism for causing the problems of the related art will be described with reference to FIGS. 9, 10, and 11.

  9 is a configuration diagram using a multitask OS, FIG. 10 is a flowchart showing processing of a slave flip-flop control task, and FIG. 11 shows that tasks other than the SF / F control task are executed in between. FIG.

  As shown in FIG. 9, there are a plurality of tasks in the configuration using the multitask OS, and the priority order is determined for each. Here, for the sake of explanation, there are task A, task B, and SF / F control task, and the priority order is higher in the order of task A, task B, and SF / F control task.

  When an event for executing task A occurs, the multitask OS executes task A. At this time, if another task B or SF / F control task is being executed, the processing of the task being executed is interrupted, and task A is executed (hereinafter, the right to execute this operation is transferred). .

  The execution right is transferred only to a task having a low priority to a high task.

  As shown in FIG. 10, when the SF / F control task processing is divided into SF / F output pre-processing, SF / F output, and SF / F post-processing, priority is given to the SF / F control task. When a high task is activated, processing is executed as shown in FIG.

  Here, a case where task A and task B are executed during execution of SF / F control pre-processing of the SF / F control task will be described.

  When the SF / F control task is executed at 1101 in FIG. 11 and an activation event of task A or task B occurs during the execution of the SF / F control pre-process, the multitasking OS determines the SF of the SF / F control task. / F control pre-processing is interrupted, and the execution right is first transferred to task A having a higher priority (S301). Task A processing is executed in task A to which the execution right has been transferred. After the task A process is completed, the multitask OS transfers the execution right to the task B (S302). The task B process is executed in the same manner as the task A, and after the completion, the execution right is transferred to the SF / F control task in which the multitask OS is suspended (S303).

Therefore, as shown in FIG. 10, task processing that executes processing in the order of SF / F control pre-processing, SF / F output, and post-SF / F control processing is interleaved with tasks A and B. As a result, the processing time differs. That is, there is a problem that the active / inactive switching timing of the slave ready signal is not originally controlled, and the master processor cannot be controlled by the slave ready signal.
JP-A-4-305758

  In the conventional method for realizing the connection between the master processor and the slave processor having the terminal indicating the communication enable state as described above, the slave ready signal is controlled, but the slave ready signal is not processed until the processing of the task having the higher priority is completed. Therefore, it is difficult for the master processor to know the state of the slave processor by the slave ready signal. In addition, the slave ready signal can be delayed by any number of situations as described above. In such a case, the master processor takes a long time to control the slave processor, or the process falls into an infinite loop or the like even though the slave processor is operating normally (such as A special process such as an abnormal process may be executed assuming that the state is also called a “deadlock state”.

  A processor system according to the present invention includes a slave processor that outputs a task activation state signal indicating a task activation state, an integration circuit that integrates a task activation state signal input from the slave processor and outputs an integration result signal, and the slave And a master processor connected to the processor and the integration circuit for determining a task activation state based on the integration result signal. With such a configuration, the master processor can know the task activation status of the slave processor.

  ADVANTAGE OF THE INVENTION According to this invention, the processor system and communication apparatus which a master processor can know the state of a slave processor can be provided.

Embodiment 1 of the Invention
First, the configuration of the communication apparatus according to the first embodiment of the present invention will be described with reference to FIG. 1, FIG. 3, and FIG.

  This communication apparatus includes a slave processor 11, an integration circuit 12, a master processor 13, a communication line 14, a communication line 15, and a communication line 16.

  The slave processor 11 includes a port (PORT) terminal 11a, the integrating circuit 12 includes an input (IN) terminal 12a and an output (OUT) terminal 12b, and the master processor 13 includes an A / D terminal 13a. The slave processor 11 is connected to the integrating circuit 12 via a communication line 14 and to the master processor 13 via a communication line 16. The integrating circuit 12 is connected to the master processor 13 by a communication line 15.

  The slave processor 11 can use a multitasking OS as shown in FIG. In this example, the slave processor 11 can execute the task A31, the task B32, and the communication control task 33, and the priority order is higher in the order of task A, task B, and communication control task. The slave processor 11 has a PORT terminal 11a shown in FIG. 1, and a port output signal indicating a task activation status of the slave processor 11 which is a feature of the present invention is output from the PORT terminal 11a. As the port output signal, a value based on the determination as to whether or not the task activated by the slave processor 11 is a PORT output task is output. Details of the PORT output task will be described later.

  FIG. 7 is a configuration diagram of the CPU of the slave processor 11. The CPU of the slave processor 11 includes a RAM 71, a PORT I / O 72, a CPU core 74, a bus bridge 75, an internal bus 73, and a communication line 16. The RAM 71, the PORT I / O 72, the CPU core 74, and the bus bridge 75 are connected to each other by a communication line 73.

  The RAM 71 functions as a storage unit that temporarily stores data. The PORT I / O 72 transmits / receives a signal such as a task activation state signal to / from an external device such as the integration circuit 12. The internal bus 73 is a transmission path for transmitting and receiving data of the RAM 71, the PORT I / O 72, the CPU core 74, and the bus bridge 75. The CPU core 74 has a central calculation part in the internal circuit of the central processing unit, and executes calculation processing based on application programs developed in the RAM 71 and the like, temporarily stored data, and the like. The bus bridge 75 transmits and receives signals between the communication line 16 and the internal bus 73. The communication line 16 is a transmission path for transmitting and receiving signals between the bus bridge 75 and the master processor 13.

  Next, processing in the communication apparatus according to the first exemplary embodiment of the present invention will be described.

  As shown in FIG. 1, in the schedule process of the slave processor 11, the port output signal output from the PORT terminal 11 a is input to the IN terminal 12 a of the integrating circuit 12 through the communication line 14. An example of the signal waveform of the port output signal is shown in the upper part of FIG. As shown in the figure, since the port output signal 21 is a digital signal, it includes a plurality of rectangular waves.

  The basic operation of the PORT output task and the CPU core 74 and the PORT I / O 72 of the slave processor 11 will be described with reference to FIGS. 4 and 5. The PORT output task is preferably set for a task having a low priority among tasks processed by the slave processor 11. An example is the IDLE task. The IDLE task is a task that is activated when no task is activated in the schedule process executed by the CPU core 74. The schedule process is the same as that described in the prior art. Needless to say, the IDLE task is a low-priority task. When another task is activated in a state where the IDLE task is activated, the slave processor moves to processing of another task by schedule processing. Further, the PORT output task is not limited to the IDLE task, and an arbitrary task can be set. In this example, as an example, the communication control task is a PORT output task.

  When the slave processor 11 starts a task, the schedule process is started. This schedule processing is activated when the priority of the task determined by the multitask OS is higher than the priority of the currently activated task. The CPU core 74 first executes a task activation pre-processing (S101) to determine which task to activate. Next, it is determined whether or not the activated task is a PORT output task (S102), and based on the result, the PORT I / O 72 is instructed to output a port output signal. Specifically, when the activated task is a PORT output task, a low level value is output, and when it is not a PORT output task, a high level value is output. FIG. 5 illustrates an example of the operation. In the CPU core 74, an IDLE task → task A → IDLE task → PORT output task (communication control task) → task A → task B → PORT output task (communication control task). The port output signal output to the PORT terminal 11a when the tasks are activated one after another. It can be seen that a low level value is output when the IDLE task and communication control task, which are PORT output tasks, are activated, and a high level value is output when task A and task B, which are not PORT output tasks, are activated.

  The port output signal input to the IN terminal 12a of the integrating circuit 12 is integrated in the integrating circuit 12, and output as an integration result signal from the OUT terminal 12b of the integrating circuit 12. 2 shows an example of the integration result signal 22 obtained by integrating the port output signal 21 shown in the upper stage. As shown in the figure, when the period during which the port output signal is at a high level becomes longer, the output level of the integration result signal 22 becomes higher.

  The integration result signal output from the OUT terminal 12 b of the integration circuit 12 is input to the A / D terminal 13 a of the master processor 13 through the communication line 15.

  As described below, the master processor 13 can know the task activation state of the slave processor 11 from the value input to the A / D terminal 13 a of the master processor 13.

  In the schedule processing of the slave processor 11, when a task higher than the priority of the communication control task is activated, the value output from the PORT terminal 11 a of the slave processor 11 becomes high level, and the A / D terminal of the master processor 13 The value input in 13a is also close to the upper limit. In this case, the master processor 13 knows that the slave processor 11 is busy with task processing other than the communication control task. Further, the master processor 13 may determine that the slave processor 11 is in a deadlock state and perform an abnormality processing if the integration result signal is equal to or greater than a predetermined value for a predetermined time.

  On the other hand, when the communication control task is activated, the value output from the PORT terminal 11a of the slave processor 11 is low level, and the value input to the A / D terminal 13a of the master processor 13 is close to the lower limit. Become. In this case, the master processor 13 knows that the slave processor 11 is not busy with task processing other than the communication control task.

  As described above, in the communication device according to the first embodiment of the present invention, the master processor can know the task activation state of the slave processor from the value input to the A / D terminal of the master processor.

Embodiment 2 of the Invention
Next, the configuration of the communication apparatus according to the second embodiment of the present invention and the processing in the communication apparatus according to the second embodiment of the present invention will be described with reference to FIG.

  Initially, the structure of the communication apparatus concerning Embodiment 2 of this invention is demonstrated.

  The communication apparatus includes a slave processor 11, an integration circuit 12, a comparator 61, a master processor 13, a communication line 14, a communication line 15, a communication line 16, and a communication line 62.

  The slave processor 11 includes a PORT terminal 11a, the integration circuit 12 includes an IN terminal 12a and an OUT terminal 12b, and the master processor 13 includes an INT terminal 13b. The slave processor 11 is connected to the integrating circuit 12 via a communication line 14 and to the master processor 13 via a communication line 16. The integrating circuit 12 is connected to the comparator 61 by the communication line 15. The comparator 61 is connected to the master processor 13 by a communication line 62.

  Next, processing in the communication apparatus according to the second exemplary embodiment of the present invention will be described. Note that the steps up to the embodiment in which a value is output to the OUT terminal 12b of the integrating circuit 12 are the same as those in the first embodiment, and thus description thereof is omitted.

  If the threshold voltage is set with respect to the value output to the OUT terminal 12b of the integrating circuit 12 and becomes higher than the threshold voltage, the output of the comparator 61 changes. The master processor 13 can know the state of the slave processor 11 as an external interrupt from the change in the output of the comparator 61.

  As described above, also in the communication apparatus according to the second embodiment of the present invention, the master processor can know the task activation state of the slave processor as in the communication apparatus according to the first embodiment of the present invention.

It is a block diagram of the communication apparatus concerning Embodiment 1 of this invention. It is the figure which showed the value input into the IN terminal in the integration circuit concerning this invention, and the value output to the OUT terminal by integration in the waveform. It is a task block diagram of the slave processor concerning this invention. It is a flowchart which shows the schedule process of the slave processor concerning this invention. It is the figure which showed the transition of the output waveform of the PORT terminal concerning this invention, the output waveform of an integration circuit, and a task starting state. It is a block diagram of the communication apparatus concerning Embodiment 2 of this invention. It is a CPU block diagram of the slave processor concerning this invention. It is a block diagram of the communication apparatus concerning a prior art. It is a task block diagram concerning a prior art. It is a flowchart which shows the process of SF / F control task. It is a sequence diagram explaining that tasks other than the SF / F control task are executed in between.

Explanation of symbols

11 Slave processor 12 Integration circuit 13 Master processor 14 Communication line 15 Communication line 61 Comparator 62 Communication line

Claims (8)

A slave processor that outputs a task start state signal indicating a task start state;
An integration circuit that integrates the task activation state signal input from the slave processor and outputs an integration result signal;
A processor system comprising: a master processor connected to the slave processor and the integration circuit, and determining a task activation status based on the integration result signal. The processor system further includes a comparator that performs a comparison process on the integration result signal output from the integration circuit and outputs a comparison result signal.
The processor system according to claim 1, wherein the master processor determines a task activation status based on the comparison result signal.   The processor system according to claim 1, wherein the slave processor executes a multitask operating system.   4. The processor system according to claim 1, wherein the slave processor outputs the task activation state signal as a port.   2. The processor system according to claim 1, wherein the master processor comprises means for converting the integration result signal into a digital signal.   A communication apparatus comprising the processor system according to claim 1.   A processor that executes a multitasking operating system, based on a startup state of a first task that is executed by the multitasking operating system and a second task that has a lower execution priority than the first task. A processor characterized by outputting an activation state signal.   The task activation state signal has a first potential when the first task is activated, and has a second potential when the second task is activated. 7. The processor according to 7.

Images