JP2020112918A - Method of measuring execution load factor of software in control device - Google Patents

Method of measuring execution load factor of software in control device Download PDF

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JP2020112918A
JP2020112918A JP2019001833A JP2019001833A JP2020112918A JP 2020112918 A JP2020112918 A JP 2020112918A JP 2019001833 A JP2019001833 A JP 2019001833A JP 2019001833 A JP2019001833 A JP 2019001833A JP 2020112918 A JP2020112918 A JP 2020112918A
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interrupt process
load factor
software
level voltage
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JP7230511B2 (en
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孝雄 澤田
Takao Sawada
孝雄 澤田
小高 章弘
Akihiro Odaka
章弘 小高
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Fuji Electric Co Ltd
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Abstract

To provide a method of easily measuring an execution load factor of software with a small error while suppressing a required time to 100 ns or less by limiting processing for measuring the execution load factor into necessary minimum.SOLUTION: In executing software comprising a plurality of pieces of interruption processing 401 to 404 and idling processing 405, a high-level voltage is output to a digital terminal when interruption processing being a measurement object is started, and a low-level voltage is output when the interruption processing is terminated. The low-level voltage is output when interruption processing not being the measurement object is started, and the high-level voltage is output when the interruption processing being the measurement object occurs and interruption processing having a priority level higher than that of the interruption processing being the measurement object does not occur when the interruption processing not being the measurement object is terminated. While the idling processing is executed, the low-level voltage is output (406 and 407), and an execution load factor of the software is calculated from an average voltage at the digital terminal in a prescribed period.SELECTED DRAWING: Figure 5

Description

本発明は、電動車両のモータ駆動装置のように高速定周期でソフトウェアを動作させる制御装置においてソフトウェアの実行負荷率を測定する技術に関する。 The present invention relates to a technique for measuring an execution load factor of software in a control device that operates software at a high-speed fixed cycle such as a motor drive device of an electric vehicle.

ソフトウェアの実行時間や単位時間当たりの実行時間である実行負荷率を測定する方法として、対象とするソフトウェアに属するタスクや割込み処理の実行開始時および終了時にCPU内蔵タイマのカウンタ値を記録し、開始時と終了時の差分から実行時間と実行負荷率を算出する技術が知られている。 As a method to measure the execution time rate of software execution time or execution time per unit time, the counter value of the CPU built-in timer is recorded and started at the start and end of the execution of tasks and interrupt processing belonging to the target software. There is known a technique of calculating an execution time and an execution load factor from a difference between time and end time.

この技術において、対象とするソフトウェアに属するタスクや割込み処理の実行中、当該ソフトウェアに属さないタスクや割込み処理が優先的に実行される場合はそれらの実行時間を差し引く必要がある。 In this technique, during execution of a task or interrupt process belonging to target software, if a task or interrupt process not belonging to the software is preferentially executed, it is necessary to subtract the execution time thereof.

特許文献1に記載された制御装置におけるタスク等の実行時間測定方法では、測定対象より優先順位の高いタスクや割込み処理が多重に実行される場合、スタックを操作することでそれらの実行時間を差し引いている。 In the execution time measuring method for tasks and the like in the control device described in Patent Document 1, when tasks or interrupts having a higher priority than the measurement target are executed in multiple, the execution time is subtracted by operating the stack. ing.

具体的には、制御装置がオペレーティングシステム用に備えたフリーランカウンタを利用し、タスクや割込み処理の開始時点でフリーランカウンタの時刻値を読み出してプッシュ操作によりスタックデータとして記憶しておき、終了時点のフリーランカウンタの時刻値とプル操作で呼び戻したスタックデータから各タスクや割込み処理の実行時間を算出している。 Specifically, the control device uses the free-run counter provided for the operating system, reads the time value of the free-run counter at the start of the task or interrupt processing, stores it as stack data by a push operation, and ends. The execution time of each task and interrupt process is calculated from the time value of the free-run counter at that time and the stack data recalled by the pull operation.

特開2003−288237号公報JP, 2003-288237, A

しかしながら特許文献1の方法には以下のような課題がある。 However, the method of Patent Document 1 has the following problems.

まず、各タスクや割込み処理の実行時間を算出する処理、および測定対象より高い優先順位で実行されたタスクや割込み処理の実行時間を差し引く処理自体に時間を要する。また、割込み処理の実行や実行時間の算出に伴う割込みマスクや符号付き演算といったスタック操作にさらに時間を要する。このため性能が低いCPUでは、ソフトウェアの実行と実行時間の測定に要する時間が、制御対象や制御内容で決まる許容時間を超過するおそれがある。 First, it takes time for the process of calculating the execution time of each task and interrupt process, and the process itself for subtracting the execution time of the task and interrupt process executed with a higher priority than the measurement target. Further, stack operations such as interrupt masks and signed operations accompanying execution of interrupt processing and calculation of execution time require more time. Therefore, in a CPU with low performance, the time required for executing the software and measuring the execution time may exceed the allowable time determined by the control target and the control content.

次に、この方法では実行時間に測定時間が含まれることになる。電動車両のモータ駆動装置のように数百μs以下の高速定周期でソフトウェアを動作させる制御装置ではこれが無視できない誤差となり、実行時間から算出する実行負荷率にも大きな誤差が生じる。 Then, in this method, the execution time includes the measurement time. This is a non-negligible error in a control device that operates software at a high-speed fixed cycle of several hundreds of μs or less, such as a motor drive device of an electric vehicle, and a large error occurs in the execution load factor calculated from the execution time.

本発明は上記の課題を解決するためのものであり、実行負荷率測定用の処理を必要最小限にして所要時間を100ns以下程度に抑え、容易にかつ小さい誤差でソフトウェアの実行負荷率を測定する方法を提供する。 The present invention is for solving the above-mentioned problems, and it is possible to measure the execution load factor of software easily and with a small error by minimizing the processing for measuring the execution load factor to a required time of about 100 ns or less. Provide a way to do.

Highレベル電圧もしくはLowレベル電圧が出力されるディジタル端子を有する制御装置において、優先順位の異なる複数の割込み処理と、いずれの割込み処理も実行されていないときに実行されるアイドリング処理と、から成るソフトウェアを実行したときに、各割込み処理の実行中にはディジタル端子にHighレベル電圧を、アイドリング処理の実行中にはLowレベル電圧を出力する。 In a control device having a digital terminal that outputs a high level voltage or a low level voltage, software including a plurality of interrupt processes with different priorities and an idling process executed when none of the interrupt processes is executed When executing, the high level voltage is output to the digital terminal during execution of each interrupt process, and the low level voltage is output during execution of the idling process.

このディジタル端子の電圧をオシロスコープやメモリハイコーダ等の機器で測定し、所定の期間における平均電圧とHighレベル電圧との比率、もしくは所定の期間においてHighレベル電圧が出力されていた期間の割合を算出することで、ソフトウェアの実行負荷率を求めることができる。 The voltage of this digital terminal is measured with equipment such as an oscilloscope or memory high coder, and the ratio of the average voltage to the high level voltage in a predetermined period or the ratio of the period in which the high level voltage was output in the predetermined period is calculated. By doing so, the execution load factor of the software can be obtained.

割込み処理単位での実行負荷率を測定する場合には、測定対象の割込み処理開始時にディジタル端子にHighレベル電圧を、終了時にLowレベル電圧を出力するとともに、測定対象外の割込み処理開始時にLowレベル電圧を、終了時に測定対象の割込み処理が発生中かつ測定対象の割込み処理より優先順位の高い割込み処理が発生中でない場合にHighレベル電圧を出力し、上記と同様にディジタル端子の電圧を測定することで、対象とした割込み処理の実行負荷率を求めることができる。 When measuring the execution load factor in interrupt processing units, a high level voltage is output to the digital terminal at the start of interrupt processing of the measurement target, a low level voltage is output at the end, and a low level voltage is output at the start of interrupt processing other than the measurement target. At the end of the voltage measurement, when the interrupt process of the measurement target is occurring and the interrupt process of higher priority than the interrupt process of the measurement target is not occurring, the High level voltage is output and the voltage of the digital terminal is measured in the same manner as above. As a result, the execution load ratio of the target interrupt process can be obtained.

また、ソフトウェアにグローバル変数を設け、上記のディジタル端子,Highレベル電圧,Lowレベル電圧をそれぞれグローバル変数,“1”,“0”に置き換えた処理を実行してグローバル変数の状態をRAMモニタ等の機器で計測することでもソフトウェアや割込み処理の実行負荷率を求めることができる。 Further, a global variable is provided in the software, and the processing of replacing the digital terminal, the high level voltage and the low level voltage with the global variable, “1” and “0”, respectively, is executed, and the state of the global variable is monitored by a RAM monitor or the like. The execution load factor of software and interrupt processing can also be obtained by measuring with equipment.

本発明によれば、優先順位の異なる複数の割込み処理から成るソフトウェアを高速定周期で動作させる制御装置において、ソフトウェアやこれを構成する割込み処理の実行負荷率測定処理を必要最小限とすることができ、測定に要する時間が短く、誤差の小さい実行負荷率測定が可能となる。 According to the present invention, in a control device that operates software consisting of a plurality of interrupt processes having different priorities at a high-speed fixed cycle, it is possible to minimize the execution load factor measurement process of the software and the interrupt processes constituting the software. Therefore, the time required for the measurement is short, and the execution load factor can be measured with a small error.

本発明の方法でソフトウェアの実行負荷率を測定するシステムの構成図。The block diagram of the system which measures the execution load factor of software by the method of this invention. 本発明が測定の対象とするソフトウェアの構成図。The block diagram of the software used as the object of measurement by the present invention. 本発明の第1実施形態を表すタイミングチャート。The timing chart showing 1st Embodiment of this invention. 図3におけるディジタル端子出力信号の数値例。Numerical example of the digital terminal output signal in FIG. 本発明の第2実施形態を表すタイミングチャート。The timing chart showing 2nd Embodiment of this invention. 図5に対応する割込み処理実行状態変数とディジタル端子出力状態の推移。Transition of interrupt process execution status variables and digital terminal output status corresponding to Fig. 5.

以下、図を参照して発明の実施形態について説明する。
[システムおよびソフトウェア構成]
図1は本発明の方法でソフトウェアの実行時間および実行負荷率を測定するシステムの構成例である。試験装置10,駆動装置20,モータ30,測定器40から成る。
Embodiments of the invention will be described below with reference to the drawings.
[System and software configuration]
FIG. 1 shows an example of the configuration of a system for measuring the execution time and execution load factor of software by the method of the present invention. It is composed of a test device 10, a drive device 20, a motor 30, and a measuring device 40.

試験装置10はツイストペア等の通信用のケーブルで駆動装置20と接続され、駆動装置20に指令を与える。駆動装置20は試験装置10からの指令に応じてモータ30を制御する制御装置であって、モータ30に指令を与えるとともに、試験装置10に指令の実行結果や自身およびモータ30の状態等を応答として返す。モータ30に駆動力を供給する電源や電力変換装置、モータ30の電流や回転状態を検出する機器は図示を省略している。測定器40は駆動装置20が有するディジタル端子やメモリの状態を駆動装置20のI/Oポートを通じて計測するもので、具体的にはオシロスコープ,メモリハイコーダ,RAMモニタ等を使用する。 The test device 10 is connected to the drive device 20 with a cable for communication such as twisted pair, and gives a command to the drive device 20. The drive device 20 is a control device that controls the motor 30 in response to a command from the test device 10. The drive device 20 gives a command to the motor 30 and responds to the test device 10 with the execution result of the command and the state of itself and the motor 30. To return as. A power source for supplying a driving force to the motor 30, a power converter, and a device for detecting the current and the rotation state of the motor 30 are not shown. The measuring device 40 measures the state of the digital terminals and the memory of the driving device 20 through the I/O port of the driving device 20, and specifically uses an oscilloscope, a memory hi-coder, a RAM monitor or the like.

図2は駆動装置20で動作するソフトウェア(以下、制御プログラムと呼ぶ)の構成例である。制御プログラムは割込み処理A(201),割込み処理B(202),割込み処理C(203),アイドリング処理204から成る。 FIG. 2 is a configuration example of software (hereinafter, referred to as a control program) that operates in the drive device 20. The control program includes an interrupt process A (201), an interrupt process B (202), an interrupt process C (203), and an idling process 204.

割込み処理の優先順位は割込み処理A(201)>割込み処理B(202)>割込み処理C(203)で、いずれの割込み処理も実行されていない時はアイドリング処理204が実行される。各処理の機能は本発明の実行負荷率測定とは関係ないため説明を省略する。 The priority order of the interrupt processing is interrupt processing A (201)>interrupt processing B (202)>interrupt processing C (203). When no interrupt processing is executed, idling processing 204 is executed. Since the function of each process is not related to the execution load factor measurement of the present invention, the description thereof will be omitted.

図1のシステム構成および図2の制御プログラム構成において、実行負荷率測定用の処理として駆動装置20は割込み処理A(201),割込み処理B(202),割込み処理C(203),アイドリング処理204の実行状態に応じてディジタル端子にHighレベル電圧もしくはLowレベル電圧を出力する。 In the system configuration of FIG. 1 and the control program configuration of FIG. 2, as a process for measuring the execution load factor, the drive unit 20 uses the interrupt process A (201), the interrupt process B (202), the interrupt process C (203), and the idling process 204. The high level voltage or the low level voltage is output to the digital terminal according to the execution state of.

出力された電圧は逆レベルの電圧(Highレベル電圧に対するLowレベル電圧、Lowレベル電圧に対するHighレベル電圧)が出力されるまで保持される。このような機構はフリップフロップ回路やこれを内蔵したロジックICにより容易にかつ安価で実現することができる。 The output voltage is held until a reverse level voltage (Low level voltage for High level voltage, High level voltage for Low level voltage) is output. Such a mechanism can be easily and inexpensively realized by a flip-flop circuit or a logic IC incorporating the flip-flop circuit.

なお、以下ではHighレベル電圧およびLowレベル電圧をそれぞれ単にHighおよびLowとも書き、ディジタル端子出力電圧をディジタル端子出力信号もしくはディジタル端子出力状態とも呼ぶ。
[第1実施形態]
第1実施形態では図2に示した制御プログラム全体を測定対象とする。
In the following, the High level voltage and the Low level voltage are simply written as High and Low, respectively, and the digital terminal output voltage is also called a digital terminal output signal or a digital terminal output state.
[First Embodiment]
In the first embodiment, the entire control program shown in FIG. 2 is the measurement target.

実行負荷率測定用の処理として、割込み処理A(201),割込み処理B(202),割込み処理C(203)それぞれの開始時にディジタル端子にHighレベル電圧を、アイドリング処理204の開始時にLowレベル電圧を出力する。 As the processing for measuring the execution load factor, a high level voltage is applied to the digital terminal at the start of each of the interrupt process A (201), the interrupt process B (202), and the interrupt process C (203), and the low level voltage is started at the start of the idling process 204. Is output.

図3は制御プログラムの動作例と、これに第1実施形態を適用したときのディジタル端子出力信号のタイミングチャートである。以下、図中の丸囲み数字を括弧つき数字で表す。 FIG. 3 is an operation example of the control program and a timing chart of the digital terminal output signal when the first embodiment is applied thereto. In the following, the circled numbers in the figures are represented by numbers in parentheses.

割込み処理A(301)が開始された(1)の時点でディジタル端子出力信号305をLowからHighにする。続いて割込み処理B(302),割込み処理C(303),割込み処理A(301),割込み処理C(303)が順に実行される。 At the time of (1) when the interrupt processing A (301) is started, the digital terminal output signal 305 is changed from Low to High. Subsequently, the interrupt process B (302), the interrupt process C (303), the interrupt process A (301), and the interrupt process C (303) are sequentially executed.

割込み処理C(303)が終了した(2)の時点でいずれの割込み処理も実行されておらずアイドリング処理304が開始されるので、ディジタル端子出力信号305をHighからLowにする。(1)−(2)の期間をT1とする。 At the time of (2) when the interrupt process C (303) is completed, no interrupt process is executed and the idling process 304 is started, so that the digital terminal output signal 305 is changed from High to Low. The period of (1)-(2) is T1.

同様に、いずれかの割込み処理が実行されている(3)−(4),(5)−(6),(7)−(8)の期間をそれぞれT2,T3,T4とする。(1)−(9)の期間を測定期間とし、その長さを全体時間Tallとする。 Similarly, the periods of (3)-(4), (5)-(6), and (7)-(8) in which any of the interrupt processes are executed are T2, T3, and T4, respectively. The period of (1)-(9) is set as the measurement period, and its length is set as the total time Tall.

測定期間(1)−(9)における制御プログラムの実行負荷率は、割込み処理時間の合計をTsum=T1+T2+T3+T4とするとTsum÷Tall×100%である。 The execution load factor of the control program in the measurement period (1)-(9) is Tsum÷Tall×100% when the total interrupt processing time is Tsum=T1+T2+T3+T4.

このときディジタル端子の平均電圧VAは、Highレベル電圧をVH、Lowレベル電圧をVLとするとVA=(VH−VL)×Tsum÷Tallであるから、オシロスコープ等の測定器でこれを測定すればVA÷(VH−VL)×100%により実行負荷率を算出することができる。 At this time, the average voltage VA of the digital terminal is VA=(VH−VL)×Tsum÷Tall, where VH is the high level voltage and VL is the low level voltage. The execution load factor can be calculated by ÷(VH−VL)×100%.

例えば図4のようなディジタル端子出力信号でHighレベル電圧が5.0V、Lowレベル電圧が0.0Vの場合、平均電圧を測定すると3.75Vとなる。この平均電圧から制御プログラムの実行負荷率を算出すると3.75V÷(5.0V−0.0V)×100%=75%となる。
[第2実施形態]
第2実施形態では制御プログラムを構成する処理のうち特定の割込み処理を測定対象とする。
For example, when the high level voltage is 5.0 V and the low level voltage is 0.0 V in the digital terminal output signal as shown in FIG. 4, the average voltage is 3.75 V when measured. When the execution load factor of the control program is calculated from this average voltage, it becomes 3.75V÷(5.0V-0.0V)×100%=75%.
[Second Embodiment]
In the second embodiment, a specific interrupt process among the processes forming the control program is a measurement target.

実行負荷率測定用の処理として、測定対象の割込み処理開始時にディジタル端子にHighレベル電圧を、終了時にLowレベル電圧を出力するとともに、測定対象外の割込み処理開始時にLowレベル電圧を、終了時に測定対象の割込み処理が発生中(開始後かつ終了前)かつ測定対象の割込み処理より優先順位の高い割込み処理が発生中でない場合Highレベル電圧を出力する。アイドリング処理開始時にはディジタル端子にLowレベル電圧を出力する。 As a process for measuring the execution load factor, a high-level voltage is output to the digital terminal at the start of interrupt processing of the measurement target, and a low-level voltage is output at the end, and the low-level voltage is measured at the start of interrupt processing outside the measurement target and measured at the end. When the target interrupt process is occurring (after starting and before ending) and the interrupt process having a higher priority than the measurement target interrupt process is not occurring, the high level voltage is output. At the start of the idling process, a low level voltage is output to the digital terminal.

図5は、図2に示した制御プログラムに割込み処理D(404)を追加した制御プログラムの動作例と、これに第2実施形態を適用したときのディジタル端子出力信号のタイミングチャートである。 FIG. 5 is an operation example of a control program in which an interrupt process D (404) is added to the control program shown in FIG. 2 and a timing chart of a digital terminal output signal when the second embodiment is applied thereto.

割込み処理の優先順位は割込み処理A(401)>割込み処理B(402)>割込み処理C(403)>割込み処理D(404)で、いずれの割込み処理も実行されていない時はアイドリング処理204が実行される。
[第2実施形態:割込み処理Bを測定対象とした場合]
割込み処理B(402)を測定対象とした場合、割込み処理B(402)が開始された(3),(10),(15)の時点でディジタル端子出力信号406をHighに、終了した(4),(11),(18)の時点でLowにするとともに、測定対象外の割込み処理A(401),C(403),D(404)が開始された(1),(2),(4),(5),(9),(11),(12),(16)の時点でディジタル端子出力信号406をLowに、終了した(3),(6),(7),(8),(10),(13),(14),(17)の時点で割込み処理B(402)が発生中の場合ディジタル端子出力信号406をHighにする。
The priority of the interrupt processing is interrupt processing A (401)>interrupt processing B (402)>interrupt processing C (403)>interrupt processing D (404). When no interrupt processing is executed, the idling processing 204 is To be executed.
[Second Embodiment: When Interrupt Process B is Measured]
When the interrupt process B (402) is set as the measurement target, the digital terminal output signal 406 is set to High and ended (4) at the time points (3), (10), and (15) when the interrupt process B (402) is started. ), (11) and (18), the interrupt process A (401), C (403) and D (404) which is not the measurement target is started while it is set to Low (1), (2), ( At the time of 4), (5), (9), (11), (12), and (16), the digital terminal output signal 406 is set to Low and ended (3), (6), (7), (8 ), (10), (13), (14), and (17), when the interrupt process B (402) is occurring, the digital terminal output signal 406 is set to High.

(3)−(4)および(10)−(11)の期間には割込み処理B(402)の実行中にこれより優先順位の高い割込み処理が発生していない。このため当該期間がそのままディジタル端子出力信号406がHighの期間となる。 During the period of (3)-(4) and (10)-(11), the interrupt process having a higher priority than the interrupt process B (402) is not executed during execution. Therefore, the period is directly the period when the digital terminal output signal 406 is High.

(15)−(18)の期間には割込み処理B(402)より優先順位の高い割込み処理A(401)が発生している。そこで、割込み処理A(401)が開始された(16)の時点でディジタル端子出力信号406をLowにし、終了した(17)の時点では割込み処理Bが発生中のためディジタル端子出力信号406をHighにする。すると(15)−(18)の期間のうち(15)−(16)および(17)−(18)の期間でディジタル端子出力信号406がHighになる。 During the period (15)-(18), the interrupt process A (401) having a higher priority than the interrupt process B (402) is generated. Therefore, the digital terminal output signal 406 is set to Low at the time (16) when the interrupt processing A (401) is started, and the digital terminal output signal 406 is set to High at the time (17) when the interrupt processing B is being generated. To Then, the digital terminal output signal 406 becomes High in the periods (15)-(16) and (17)-(18) of the period (15)-(18).

ここで(3)−(4),(10)−(11),(15)−(16),(17)−(18)の期間をそれぞれTb1,Tb2,Tb3,Tb4とする。(1)−(19)の期間を測定期間とし、その長さを全体時間Tallとする。 Here, the periods (3)-(4), (10)-(11), (15)-(16), and (17)-(18) are referred to as Tb1, Tb2, Tb3, and Tb4, respectively. The period (1)-(19) is set as the measurement period, and its length is set as the total time Tall.

測定期間(1)−(19)における割込み処理B(402)の実行負荷率は、割込み処理時間の合計をTsum=Tb1+Tb2+Tb3+Tb4とするとTsum÷Tall×100%であり、これは第1実施形態と同様にディジタル端子の平均電圧の測定値から算出することができる。
[第2実施形態:割込み処理Dを測定対象とした場合]
割込み処理D(404)を測定対象とした場合、割込み処理D(404)が開始された(1)の時点でディジタル端子出力信号407をHighに、終了した(8)の時点でLowにするとともに、測定対象外の割込み処理A(401),B(402),C(403)が開始された(2),(3),(4),(5),(9),(10),(11),(12),(15),(16)の時点でディジタル端子出力信号407をLowに、終了した(3),(4),(6),(7),(10),(11),(13),(14),(17),(18)の時点で割込み処理D(404)が発生中かつこれより優先順位の高い割込み処理が発生中でない場合ディジタル端子出力信号407をHighにする。
The execution load ratio of the interrupt processing B (402) in the measurement period (1)-(19) is Tsum÷Tall×100% when the total interrupt processing time is Tsum=Tb1+Tb2+Tb3+Tb4, which is the same as in the first embodiment. Can be calculated from the measured value of the average voltage of the digital terminal.
[Second Embodiment: When the interrupt processing D is the measurement target]
When the interrupt process D (404) is set as a measurement target, the digital terminal output signal 407 is set to High at the time point (1) when the interrupt process D (404) is started, and at the time point when the interrupt process D (404) is ended (8). , Interrupt processing A(401), B(402), C(403) outside the measurement target was started (2), (3), (4), (5), (9), (10), ( At the time of 11), (12), (15), and (16), the digital terminal output signal 407 is set to Low and ended (3), (4), (6), (7), (10), (11). ), (13), (14), (17), and (18), when the interrupt process D (404) is occurring and the interrupt process with a higher priority is not occurring, the digital terminal output signal 407 is set to High. To

(1)−(8)の期間には割込み処理D(404)より優先順位の高い割込み処理A(401),B(402),C(403)が発生している。 During the period (1)-(8), the interrupt processes A (401), B (402), and C (403) having a higher priority than the interrupt process D (404) are generated.

そこでまず、割込み処理A(401)が開始された(2)の時点でディジタル端子出力信号407をHighからLowにする。割込み処理A(401)が終了した(3)の時点では測定対象である割込み処理D(404)が実行中であるが、割込み処理A(401)の実行中に順番待ちとなった割込み処理B(402)が続けて開始されるためディジタル端子出力信号407はLowのままとなる。割込み処理B(402)が終了して割込み処理C(403)が開始される(4)の時点も同様で、(2)−(4)の期間においてディジタル端子出力信号407はLowに保たれることになる。 Therefore, first, at the time point (2) when the interrupt processing A (401) is started, the digital terminal output signal 407 is changed from High to Low. At the time of (3) when the interrupt process A (401) is completed, the interrupt process D (404) that is the measurement target is being executed, but the interrupt process B that has been waiting for a turn while the interrupt process A (401) is being executed. Since (402) is continuously started, the digital terminal output signal 407 remains Low. The same applies at the time point (4) when the interrupt process B (402) is ended and the interrupt process C (403) is started, and the digital terminal output signal 407 is kept low during the period (2)-(4). It will be.

続いて、再び割込み処理A(401)が開始された(5)の時点でもディジタル端子出力信号407はLowのままとなる。割込み処理A(401)が終了した(6)の時点では依然として測定対象の割込み処理D(404)が実行中であるが、これより優先順位の高い割込み処理C(403)が実行中のためディジタル端子出力信号407はLowのままとなる。割込み処理C(403)が終了した(7)の時点では測定対象の割込み処理D(404)が実行中かつこれより優先順位の高い割込み処理は実行中でないためディジタル端子出力信号407をLowからHighにする。 Then, the digital terminal output signal 407 remains Low even at the time of (5) when the interrupt processing A (401) is started again. At the time of (6) when the interrupt process A (401) is completed, the interrupt process D (404) to be measured is still being executed, but since the interrupt process C (403) having a higher priority is being executed, it is digital. The terminal output signal 407 remains Low. At the time of (7) when the interrupt process C (403) is completed, the interrupt process D (404) to be measured is being executed, and the interrupt process having a higher priority than this is not being executed. Therefore, the digital terminal output signal 407 is changed from Low to High. To

その後、割込み処理D(404)が再開され、終了した(8)の時点でディジタル端子出力信号をHighからLowにする。これ以降は割込み処理D(404)が実行されないためディジタル端子出力信号はLowに保たれる。 After that, the interrupt processing D (404) is restarted, and the digital terminal output signal is changed from High to Low at the time of the completion (8). Since the interrupt process D (404) is not executed thereafter, the digital terminal output signal is kept low.

従って(1)−(19)の期間のうち(1)−(2)および(7)−(8)の期間でディジタル端子出力信号407がHighになる。 Therefore, the digital terminal output signal 407 becomes High in the periods (1)-(2) and (7)-(8) of the period (1)-(19).

ここで(1)−(2)および(7)−(8)の期間をそれぞれTd1およびTd2とする。(1)−(19)の期間を測定期間とし、その長さを全体時間Tallとする。 Here, the periods (1)-(2) and (7)-(8) are referred to as Td1 and Td2, respectively. The period (1)-(19) is set as the measurement period, and its length is set as the total time Tall.

測定期間(1)−(19)における割込み処理D(404)の実行負荷率は、割込み処理時間の合計をTsum=Td1+Td2とするとTsum÷Tall×100%であり、これも第1実施形態と同様にディジタル端子の平均電圧の測定値から算出することができる。 The execution load ratio of the interrupt processing D (404) in the measurement period (1)-(19) is Tsum÷Tall×100% when the total interrupt processing time is Tsum=Td1+Td2, which is also the same as in the first embodiment. Can be calculated from the measured value of the average voltage of the digital terminal.

上記のように各割込み処理の実行状態に応じてディジタル端子への出力を変える処理は、制御プログラムに割込み処理実行状態変数を設けることで実現することができる。 The process of changing the output to the digital terminal according to the execution state of each interrupt process as described above can be realized by providing an interrupt process execution state variable in the control program.

各割込み処理ごとに実行状態を示す割込み処理実行状態変数を設け、割込み処理開始時に割込み処理実行状態変数をON(実行中)にし、終了時にOFF(実行中でない)にする。割込み処理実行状態=ONは実行再開待ち状態を含み、割込み処理を開始してから終了するまでの期間とする。 An interrupt process execution state variable indicating the execution state is provided for each interrupt process, and the interrupt process execution state variable is turned ON (running) at the start of the interrupt process and turned OFF (not being executed) at the end. The interrupt processing execution state=ON includes the execution restart waiting state, and is the period from the start of the interrupt processing to the end thereof.

図6は図5における各割込み処理の割込み処理実行状態変数およびディジタル端子出力状態の推移を示したものである。 FIG. 6 shows transitions of interrupt processing execution state variables and digital terminal output states of each interrupt processing in FIG.

例えば第2実施形態で割込み処理D(404)を測定対象とした場合の(4)から(7)の期間では、割込み処理B(402)が終了した(4)の時点で他の割込み処理の実行状態変数を参照すると測定対象である割込み処理D(404)の実行状態変数はONであるがこれより優先順位の高い割込み処理C(403)の実行状態変数がONのためディジタル端子への出力はLowとなり、割込み処理A(401)が終了した(6)の時点では依然として測定対象の割込み処理D(404)の実行状態変数はONであるがこれより優先順位の高い割込み処理C(403)の実行状態変数がONのためディジタル端子への出力はやはりLowとなる。割込み処理C(403)が終了した(7)の時点で測定対象の割込み処理D(404)の実行状態変数がONかつこれより優先順位の高い割込み処理A(401),B(402),C(403)の実行状態変数がいずれもONでないためディジタル端子への出力はHighとなる。 For example, in the period from (4) to (7) when the interrupt process D (404) is the measurement target in the second embodiment, another interrupt process is interrupted at the time (4) when the interrupt process B (402) is completed. When the execution state variable is referred to, the execution state variable of the interrupt process D (404) that is the measurement target is ON, but the execution state variable of the interrupt process C (403) having a higher priority is ON, so the output to the digital terminal is made. Becomes Low, and the execution state variable of the interrupt process D (404) to be measured is still ON at the time of (6) when the interrupt process A (401) is completed, but the interrupt process C (403) having a higher priority than this. Since the execution state variable of is ON, the output to the digital terminal is also Low. At the time of (7) when the interrupt processing C (403) is completed, the execution state variable of the interrupt processing D (404) to be measured is ON and the interrupt processing A (401), B (402), C having a higher priority than this. Since none of the execution state variables of (403) are ON, the output to the digital terminal becomes High.

このような処理はデータの比較と出力のみから成っており課題で挙げたような複雑な演算を必要としないため、所要時間を100ns以下程度に抑えることができる。
[第1実施形態および第2実施形態の応用]
第1実施形態および第2実施形態において、測定モードを記憶する変数を制御プログラムに設けることで、第1実施形態のように制御プログラム全体の実行負荷率を測定するモードと第2実施形態のように割込み処理単位での実行負荷率を測定するモードを試験装置10から指定できるようにしてもよい。
Since such a process consists only of data comparison and output and does not require the complicated calculation as mentioned in the problem, the required time can be suppressed to about 100 ns or less.
[Application of the first and second embodiments]
In the first and second embodiments, by providing the control program with a variable for storing the measurement mode, a mode for measuring the execution load factor of the entire control program as in the first embodiment and a mode as in the second embodiment. In addition, the test apparatus 10 may be allowed to specify the mode for measuring the execution load rate in units of interrupt processing.

また第2実施形態において、各割込み処理を区別する識別子を定義しておき、測定対象とする割込み処理の識別子を記憶する変数を制御プログラムに設けることで、測定対象とする割込み処理を試験装置10から指定できるようにしてもよい。 Further, in the second embodiment, an identifier for distinguishing each interrupt process is defined, and a variable for storing the identifier of the interrupt process to be measured is provided in the control program, so that the interrupt process to be measured is tested by the test apparatus 10. It may be possible to specify from.

このほか第1実施形態および/もしくは第2実施形態において、ディジタル端子を複数設けておき、制御プログラム全体を測定対象とした処理および割込み処理のいずれかを測定対象とした処理のうち複数の処理を各割込み処理の開始時および終了時に実施して、各処理の出力を複数のディジタル端子に割り付けるようにしてもよい。
[第3実施形態]
第3実施形態ではディジタル端子に代えて制御プログラムに設けたグローバル変数を用いる。
In addition, in the first embodiment and/or the second embodiment, a plurality of digital terminals are provided, and a plurality of processes out of the processes targeted for measurement of either the entire control program or the interrupt process are performed. The output of each process may be assigned to a plurality of digital terminals by performing the process at the start and end of each interrupt process.
[Third Embodiment]
In the third embodiment, a global variable provided in the control program is used instead of the digital terminal.

制御プログラムにグローバル変数を設け、第1実施形態および第2実施形態のディジタル端子,Highレベル電圧,Lowレベル電圧をそれぞれグローバル変数,“1”,“0”に置き換えた処理を実行する。 A global variable is provided in the control program, and the processing in which the digital terminals, the high level voltage, and the low level voltage of the first and second embodiments are replaced with the global variables, "1" and "0", respectively, is executed.

このグローバル変数の状態をRAMモニタ等の機器を用いて定周期でサンプリングすると、グローバル変数が“1”であった回数から測定対象の割込み処理時間がわかり、これより実行負荷率を算出することができる。 If the state of this global variable is sampled at regular intervals using a device such as a RAM monitor, the interrupt processing time of the measurement target can be known from the number of times the global variable was "1", and the execution load factor can be calculated from this. it can.

例えば第1実施形態でディジタル端子出力信号が図4のようになる制御プログラムを実行した場合、本実施形態ではTsum=T1+T2+T3+T4+T5=15msとTall=20msがわかり、これより実行負荷率は15ms÷20ms×100%=75%と算出される。 For example, when the control program in which the digital terminal output signal is as shown in FIG. 4 is executed in the first embodiment, Tsum=T1+T2+T3+T4+T5=15 ms and Tall=20 ms are found in this embodiment, and the execution load factor is 15 ms÷20 ms× It is calculated as 100%=75%.

この方法を第1実施形態や第2実施形態と併用して算出結果を突き合わせることで実行負荷率測定の精度を上げることができる。また、この方法を単独で用いればディジタル端子やディジタル端子への電圧出力手段が無くても実行負荷率を測定することができる。 The accuracy of the execution load factor measurement can be improved by using this method in combination with the first embodiment and the second embodiment and matching the calculation results. Further, if this method is used alone, the execution load factor can be measured without a digital terminal or a voltage output means to the digital terminal.

10 試験装置
20 駆動装置
30 モータ
40 測定器
201,301 割込み処理A
202,302 割込み処理B
203,303 割込み処理C
204,304 アイドリング処理
401 割込み処理A
402 割込み処理B
403 割込み処理C
404 割込み処理D
405 アイドリング処理
305,406,407 ディジタル端子出力信号
10 Test device 20 Drive device 30 Motor 40 Measuring device 201, 301 Interrupt processing A
202, 302 Interrupt processing B
203, 303 Interrupt processing C
204, 304 Idling processing 401 Interrupt processing A
402 Interrupt processing B
403 Interrupt processing C
404 Interrupt processing D
405 Idling process 305, 406, 407 Digital terminal output signal

Claims (6)

Highレベル電圧もしくはLowレベル電圧が出力されるディジタル端子を有する制御装置において、
優先順位の異なる複数の割込み処理と、いずれの前記割込み処理も実行されていないときに実行されるアイドリング処理と、から成るソフトウェアを実行したときに、
前記各割込み処理の実行状態に応じて前記ディジタル端子にHighレベル電圧もしくはLowレベル電圧を出力するとともに、
前記アイドリング処理の実行状態に応じて前記ディジタル端子にHighレベル電圧もしくはLowレベル電圧を出力し、
前記ディジタル端子の電圧測定値から前記ソフトウェアもしくは前記各割込み処理の実行負荷率を算出する、
ソフトウェアの実行負荷率測定方法。
In a control device having a digital terminal for outputting a high level voltage or a low level voltage,
When a software consisting of a plurality of interrupt processes with different priorities and an idling process executed when none of the interrupt processes is executed is executed,
A High level voltage or a Low level voltage is output to the digital terminal according to the execution state of each interrupt process, and
A High level voltage or a Low level voltage is output to the digital terminal according to the execution state of the idling process,
Calculating the execution load factor of the software or the interrupt processing from the voltage measurement value of the digital terminal,
Software execution load factor measurement method.
請求項1に記載されたソフトウェアの実行負荷率測定方法であって、
前記各割込み処理の実行中には前記ディジタル端子にHighレベル電圧を出力し、
前記アイドリング処理の実行中には前記ディジタル端子にLowレベル電圧を出力し、
所定の期間における前記ディジタル端子の平均電圧、もしくは所定の期間において前記ディジタル端子にHighレベル電圧が出力されていた期間の長さから前記ソフトウェアの実行負荷率を算出する、
ソフトウェアの実行負荷率測定方法。
A method for measuring an execution load factor of software according to claim 1, comprising:
A high level voltage is output to the digital terminal during execution of each interrupt process,
During execution of the idling process, a Low level voltage is output to the digital terminal,
An execution load factor of the software is calculated from an average voltage of the digital terminal in a predetermined period, or a length of a period in which a high level voltage is output to the digital terminal in the predetermined period.
Software execution load factor measurement method.
請求項1に記載されたソフトウェアの実行負荷率測定方法であって、
前記複数の割込み処理のうち一つの割込み処理を測定対象とし、
測定対象の割込み処理開始時に前記ディジタル端子にHighレベル電圧を出力してこれを保持し、終了時に前記ディジタル端子にLowレベル電圧を出力するとともに、
測定対象外の割込み処理開始時に前記ディジタル端子にLowレベル電圧を出力してこれを保持し、終了時に前記測定対象の割込み処理が発生中かつ前記測定対象の割込み処理より優先順位の高い割込み処理が発生中でない場合に前記ディジタル端子にHighレベル電圧を出力して、
所定の期間における前記ディジタル出力端子の平均電圧、もしくは所定の期間において前記ディジタル端子にHighレベル電圧が出力されていた期間の長さから前記測定対象の割込み処理の実行負荷率を算出する、
ソフトウェアの実行負荷率測定方法。
A method for measuring an execution load factor of software according to claim 1, comprising:
One of the plurality of interrupt processes is the measurement target,
A high level voltage is output to the digital terminal at the start of the interrupt processing of the measurement target and held, and a low level voltage is output to the digital terminal at the end.
When a non-measurement target interrupt process is started, a low-level voltage is output to the digital terminal and held, and at the end of the measurement target interrupt process, an interrupt process having a higher priority than the measurement target interrupt process is in progress. When not being generated, output a high level voltage to the digital terminal,
An execution load factor of the interrupt process of the measurement target is calculated from an average voltage of the digital output terminal in a predetermined period or a length of a period in which a high level voltage is output to the digital terminal in a predetermined period,
Software execution load factor measurement method.
請求項1に記載されたソフトウェアの実行負荷率測定方法であって、
前記ソフトウェアにグローバル変数を設け、
前記各割込み処理の実行状態に応じて前記グローバル変数に“1”もしくは“0”を出力するとともに、
前記アイドリング処理の実行状態に応じて前記グローバル変数に“1”もしくは“0”を出力し、
前記グローバル変数を定周期でサンプリングすることにより前記ソフトウェアもしくは前記各割込み処理の実行負荷率を算出する、
ソフトウェアの実行負荷率測定方法。
A method for measuring an execution load factor of software according to claim 1, comprising:
We have global variables in the software,
In addition to outputting "1" or "0" to the global variable according to the execution state of each interrupt process,
“1” or “0” is output to the global variable according to the execution state of the idling process,
The execution load factor of the software or each interrupt process is calculated by sampling the global variable at regular intervals,
Software execution load factor measurement method.
請求項4に記載されたソフトウェアの実行負荷率測定方法であって、
前記各割込み処理の実行中には前記グローバル変数に“1”を出力し、
前記アイドリング処理の実行中には前記グローバル変数に“0”を出力し、
所定の期間において前記グローバル変数に“1”が出力されていた期間の長さから前記ソフトウェアの実行負荷率を算出する、
ソフトウェアの実行負荷率測定方法。
A method for measuring an execution load factor of software according to claim 4,
"1" is output to the global variable during execution of each interrupt process,
"0" is output to the global variable during execution of the idling process,
The execution load factor of the software is calculated from the length of the period in which "1" is output to the global variable in a predetermined period,
Software execution load factor measurement method.
請求項4に記載されたソフトウェアの実行負荷率測定方法であって、
前記複数の割込み処理のうち一つの割込み処理を測定対象とし、
測定対象の割込み処理開始時に前記グローバル変数に“1”を出力してこれを保持し、終了時に前記グローバル変数に“0”を出力するとともに、
測定対象外の割込み処理開始時に前記グローバル変数に“0”を出力してこれを保持し、終了時に前記測定対象の割込み処理が発生中かつ前記測定対象の割込み処理より優先順位の高い割込み処理が発生中でない場合に前記グローバル変数に“1”を出力して、
所定の期間において前記グローバル変数に“1”が出力されていた期間の長さから前記測定対象の割込み処理の実行負荷率を算出する、
ソフトウェアの実行負荷率測定方法。
A method for measuring an execution load factor of software according to claim 4,
One of the plurality of interrupt processes is the measurement target,
At the start of the interrupt process of the measurement target, "1" is output to the global variable and held, and at the end, "0" is output to the global variable.
When the non-measurement target interrupt process starts, "0" is output to the global variable and is held, and at the end, the measurement target interrupt process is occurring and an interrupt process with a higher priority than the measurement target interrupt process is executed. If not, output "1" to the global variable,
Calculating the execution load factor of the interrupt process of the measurement object from the length of the period in which "1" was output to the global variable in a predetermined period;
Software execution load factor measurement method.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59116864A (en) * 1982-12-22 1984-07-05 Fujitsu Ltd Measurement system for use rate of central processing unit
JP2008097093A (en) * 2006-10-06 2008-04-24 Nec Electronics Corp Processor system and communication device
JP2010244376A (en) * 2009-04-08 2010-10-28 Fujitsu Ten Ltd Software development device, and debugging method using the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59116864A (en) * 1982-12-22 1984-07-05 Fujitsu Ltd Measurement system for use rate of central processing unit
JP2008097093A (en) * 2006-10-06 2008-04-24 Nec Electronics Corp Processor system and communication device
JP2010244376A (en) * 2009-04-08 2010-10-28 Fujitsu Ten Ltd Software development device, and debugging method using the same

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