JP2010244376A - Software development device, and debugging method using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a software development device for properly evaluating the execution timing and execution environment of an arbitrary task or function without performing any processing to add a program for debugging to a source program. <P>SOLUTION: The software development device includes: a memory for storing a control program; a simulation CPU for executing a control program stored in the memory; a simulation microcomputer with a simulation peripheral circuit for simulating a peripheral circuit; and a host computer for managing this, and configured to, when a prescribed task included in the control program or the leading address of a prescribed function included in the task is matched with the value of the program counter of the simulation CPU, to generate interruption, and to monitor the execution state of the control program by the simulation CPU, and to display the results with a graphic. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a software development apparatus for developing and evaluating software incorporated in a microcomputer for controlling a device, and a debugging method using the software development apparatus.

  In an electronic control device including a microcomputer that controls an electronic device, for example, an electronic control device such as an electronic control unit (ECU) that controls an engine of a vehicle, the performance of the control target device such as the engine is improved and the functionality is increased. In line with technological trends, the performance of microcomputers used is also evolving year by year, and new software, that is, control logic, is assumed for microcomputers that have evolved beyond the performance of microcomputers used in current electronic control devices. Has been developed.

  Usually, there is no next-generation microcomputer with improved performance at the time of development, and if there is no electronic control unit that incorporates the next microcomputer with improved performance over the current microcomputer, the current microcomputer The development of control logic must be done based on this.

  However, when prior development of control logic is performed using an electronic control device incorporating a current microcomputer, the CPU mounted on the current microcomputer lacks processing capacity, memory capacity, peripheral resources As a result, the development of the next microcomputer and its application program was delayed, which hindered the development of new products.

  In the microcomputer incorporated in the current electronic device, in order to keep the cost of the electronic device low, the CPU performance and peripheral functions are selected with specifications that are optimal for the current system, and the CPU and CPU peripheral resources are one. Since it is incorporated into one package, it is impossible to change the functions of each package without changing the microcomputer.

  Therefore, Patent Document 1 discloses a central block having an application processing function and a communication function, a pseudo microcomputer peripheral device that performs pseudo I / O processing by realizing a microcomputer peripheral device in a pseudo manner, an arithmetic function, and Proposed software development device with communication function, peripheral block connected to central block by PCI bus, and interface circuit block that has circuit equivalent to hardware of electronic control unit and connected to peripheral block Has been.

  In this software development device, a bus controller is provided for the computation function between the communication function of the central block and the peripheral device of the pseudo microcomputer, and the communication function of the central block is connected to this bus controller via a PCI bus. The bus controller and the pseudo microcomputer peripheral device are connected by an internal bus, and data is directly transmitted and received between the communication function and the pseudo microcomputer peripheral device via the PCI bus, the bus controller, and the internal bus. Is configured to be performed.

  Further, Patent Document 2 includes a first block including a first central processing unit and a RAM and having a function corresponding to a microcomputer core, and a function corresponding to a microcomputer resource including a second central processing unit. A microcomputer logic development device having a second block having a bus and a bus connecting the first and second blocks, and having a shared memory and connected to the first block and the RAM measurement device The RAM measurement block is provided, the process of monitoring the RAM of the first block by the RAM measurement apparatus, the process of writing the contents of the RAM into the shared memory, and the contents of the shared memory are transmitted to the RAM measurement apparatus Microcomputer logic development that separates each processing timing Location has been proposed.

  According to the technique described in Patent Document 2, an existing RAM measuring device can be connected to a logic development device of a microcomputer to realize a high-speed sampling RAM monitor.

JP 2004-234530 A JP 2005-25601 A

  When evaluating previously developed software, the software development apparatus described above may be used in the following procedure.

  First, in order to determine whether or not a predetermined function included in the software to be evaluated is executed by the software development apparatus, a variable operation program in which a flag is set before and after the execution of the predetermined function, For example, after being added to a source program generated in C language, an execution program is generated by compiling.

  Next, the execution program is ported to the software development apparatus and executed, and the flag area on the RAM is monitored to confirm that the predetermined function has been executed.

  Alternatively, a debug statement that displays the fact on the display device at the start or end of execution of a predetermined function is added to the source program, and then compiled to generate an execution program.

  In the former case, it can be confirmed that the predetermined function has been executed by a change in the flag of the monitored RAM. In the latter case, the predetermined function has been executed based on the debug statement displayed on the display device. Can be confirmed.

  However, if variable operation programs and debug statements are added individually corresponding to all functions included in the source program, the computation load increases and the processing time becomes longer, so that each function is within the expected execution time. It becomes impossible to execute.

  Therefore, if the variable manipulation program or debug statement to be added to the source program is restricted, editing processing for adding the variable manipulation program or debug statement to the source program individually is required corresponding to the function to be evaluated. A very complicated process of compiling and generating an execution program and porting it to a software development device is required.

  Further, although the result of whether or not the function is executed can be determined by the variable operation program, there is a problem that it is impossible to determine in what situation the task to which the function is assigned is executed.

  For example, when a task is set to be activated by interrupt processing, it is possible to evaluate in which phase of multiple prioritized interrupt processing is executed and whether the processing time at that time is appropriate. It cannot be done.

  In addition, when a debug statement is inserted into the source program, it is only possible to confirm that the predetermined function has been executed based on the debug statement displayed on the display device, and that the variable on the RAM has changed due to the processing. Even if the RAM monitor recognizes, there is a problem that the display timing of the debug sentence and the change of the variable cannot be measured in synchronization.

  In view of the above-described problems, the present invention provides a software development apparatus that can appropriately evaluate the execution timing and execution environment of an arbitrary task or function without performing a complicated process of adding a debugging program to the source program, And it is in the point which provides the debugging method using a software development apparatus.

  In order to achieve the above object, the characteristic configuration of the software development apparatus according to the present invention includes a CPU that executes a control program and a microcomputer in which peripheral circuits are incorporated, and a memory that stores the control program; Software in which a simulation CPU that executes a control program stored in the memory, a simulation microcomputer that includes a simulation peripheral circuit that simulates the peripheral circuit, and a host computer that manages the simulation microcomputer are connected to a network An address setting unit for setting a predetermined task included in the control program or a start address of a predetermined function included in the task to the simulated microcomputer via the host computer; The setting in the setting section And a monitor processing unit that monitors the execution state of the control program executed by the simulated CPU, and transmits data monitored by the monitor processing unit to a host computer. And a monitor data transmission unit.

  According to the above configuration, when the address set by the address setting unit and the value of the program counter of the simulated CPU match, the monitor processing unit monitors the execution state of the simulated CPU, and the monitor data transmitting unit monitors the monitor data. Sent to the computer.

  Therefore, the execution state of the simulated CPU can be changed by simply setting the start address of the task or function whose operation is to be verified through the address setting unit without performing complicated processing such as adding a variable operation program to the source program. Monitored so that task and function execution timing can be properly evaluated.

  As described above, according to the present invention, a software development apparatus or the like that can appropriately evaluate the execution timing and execution environment of an arbitrary task or function without performing a complicated process of adding a debugging program to the source program Can now be provided.

Block configuration diagram comparing the configuration of a simulated microcomputer and a real microcomputer constituting a software development apparatus according to the present invention Functional block diagram of a simulated microcomputer and a host computer based on a program executed by a software development apparatus according to the present invention Explanatory drawing of the transition state of tasks included in the control program executed by the CPU of the motherboard Flowchart explaining the main part of the debugging procedure of the control program Illustration of the debug screen displayed in real time while the control program is running Explanatory drawing of the debug screen displayed after the control program is stopped

  Hereinafter, embodiments of the software development apparatus according to the present invention will be described.

  A software development device is a device that simulates an electronic control unit (hereinafter referred to as “ECU”) on which a microcomputer that controls a controlled part is mounted. For example, the software development device is replaced with an ECU that controls an engine mounted on a vehicle. Connected to the engine or a simulator simulating the engine.

  As shown in FIG. 1, the ECU 100 includes a microcomputer 101, an input / output circuit 106 connected to the input / output port of the microcomputer 101, and a harness that connects the input / output circuit 106 and sensors and actuators arranged in the engine. The connector 107 is provided, and these are mounted on a printed circuit board.

  As shown on the left side of FIG. 1, the microcomputer 101 includes a CPU 102, a memory 103 having a ROM storing an engine control program executed by the CPU 102 and a RAM used as a working area of the CPU 102, A peripheral resource 105 connected to the CPU 102 via an internal bus is housed in one package.

  Peripheral resources include input resources and output resources. Input resources include an input port that handles digital signals, a latch port, an A / D conversion port that handles analog inputs, an input capture port that handles pulse inputs, and the like. Output system resources include an output port that outputs a digital signal, a PWM port that outputs a pulse signal, a compare port, and the like.

  In the microcomputer 101, in addition to these peripheral resources, an internal timer and an interrupt controller are provided.

  When signals from the sensors and switches representing the driving state of the vehicle are captured via the input port, the CPU 102 determines the engine state according to the engine control program, and necessary signals are output from the output port to various actuators. The engine is controlled to an appropriate state.

  As shown on the right side of FIG. 1, the software development apparatus 1 includes a motherboard 10 accommodated in a rack, a single or plural I / O boards 20, and an interface board 30 (hereinafter referred to as “IF board”). It is described.)

  The operation of the CPU 102 of the microcomputer 101 is simulated by the CPU 11 of the motherboard 10, and the peripheral resource 105 of the microcomputer 101 is simulated by the I / O board 20. That is, the microcomputer 101 is simulated by the mother board 10 and the I / O board 20.

  The IF board 30 is connected to a harness that simulates the input / output circuit 106 of the ECU 100 and is connected to the engine via the connector 31 or a simulator that simulates the engine.

  The IF board 30 includes an input / output circuit including a port assignment conversion board and a plurality of standard circuit boards and function boards inserted into the connector of the port assignment conversion board, and the standard circuit board and functions inserted into the port assignment conversion board. Any number of input / output circuits can be realized by combining the boards.

  The standard circuit board consists of a digital signal circuit with a driver circuit and buffer circuit that inputs and outputs a warning lamp lighting signal and a serial signal such as a CAN bus. The function board is a power train output circuit, an analog signal input / output circuit, and an engine. The input / output processing circuit includes a low-function microcomputer for signal processing for inputting / outputting an injection signal, an ignition signal, an electronic throttle control signal, and the like.

  The software development apparatus 1 according to the present invention simulates a new microcomputer (hereinafter referred to as “virtual microcomputer”) that is a target to be mounted on the ECU 100 described above, and provides a new or improved engine control program. Functions as an emulator to verify operation.

  The motherboard 10 includes a CPU 11, a memory 12 having a ROM and a RAM, an interrupt processing unit 13, an internal timer 14, a PCI bus IF 15, a LAN IF 16, and the like, which are connected by an internal bus including a chip set.

  The memory 12 stores an operating system (hereinafter referred to as “OS”), a PCI bus driver for the PCI bus IF 15, and a LAN communication driver for the LANIF 16. Further, an engine control program, an I / O driver, an evaluation monitor program, and the like to be evaluated are transmitted from the host computer 50 connected via the LANIF 16 and stored in the memory 12.

  In order to simulate a microcomputer mounted on the next generation EUC, the motherboard 10 needs to have sufficient computing performance, processing speed, and memory capacity commensurate with it. Therefore, as the CPU 11, for example, a high-performance CPU of several GHz used for a general-purpose personal computer such as a Pentium processor (Pentium is a registered trademark of Intel Corporation) is used.

  The IO board 20 includes a CPU 23, a memory 22 having a ROM and a RAM, a PCI bus IF 23, microcomputers 24 and 25 that simulate peripheral resources for input / output of the virtual microcomputer, and the like. Connected via controller.

  A program functioning as a peripheral resource is stored in a ROM built in the microcomputers 24 and 25, and the program is executed by the CPU of the microcomputers 24 and 25, whereby the above-described input port, latch port, A / D conversion are performed. Functions such as ports, input capture ports, output ports, PWM ports, and compare ports are simulated. Therefore, various peripheral resources can be configured flexibly by changing the program.

  The motherboard 10 and the I / O board 20 are connected by a PCI bus, and exchange of data, that is, variables via the PCI bus is performed between the I / O driver stored in the memory 12 of the motherboard 10 and the I / O board 20. It is executed by the I / O driver stored in the memory 22.

  Variable data output from the CPU of the motherboard 10 is written to the shared memory via the I / O driver, and is output as a control signal from the output ports of the microcomputers 24 and 25 which are peripheral resources to the IF board 30. Further, signals taken from the input ports of the microcomputers 24 and 25, which are peripheral resources, are converted into variable data, written to the shared memory, and transmitted to the motherboard 10 via the I / O driver. Note that data transfer between the PCI bus, shared memory 22, and microcomputers 24 and 25 is performed at high speed by the bus controller.

  The internal bus that connects the CPU of the virtual microcomputer and peripheral resources for input / output is simulated by the I / O drivers of the motherboard 10 and the IO board 20 and the shared memory.

  Signals from sensors and the like input to the input ports of the microcomputers 24 and 25, which are peripheral resources, are written to the shared memory via the I / O driver, and are written to the memory 12 of the motherboard 10 via the PCI bus. Processed by.

  That is, the I / O drivers provided in the mother board 10 and the I / O board 20 respectively synchronize the boards via the PCI bus and exchange input / output data.

  The CPU 21 of the IO board 20 only needs to have a processing capability sufficient to execute PCI bus PCI communication processing and the like. For example, the operating frequency may be about 16 MHz and a 32-bit CPU.

  That is, the mother board 10 and the I / O board 20 simulate a microcomputer in which a CPU for executing a control program and its peripheral circuits are incorporated, a memory 12 for storing the control program, and a control stored in the memory 12. A simulation microcomputer including a simulation CPU 11 that executes a program and simulation peripheral circuits 24 and 25 that simulate peripheral circuits is configured.

  The host computer 50 that manages the simulation microcomputer is connected to an input device such as a keyboard and a mouse, a display device, and a hard disk. The hard disk includes an engine control program, an I / O driver, an evaluation monitor program, and A management program for operating the simulation microcomputer on which the engine control program is executed and displaying the execution state is stored.

  When power is supplied to the software development apparatus described above, an engine control program, an IO driver, and a part of an evaluation monitor program are loaded from the host computer 50 into the memory 12 of the motherboard 10 by the operation of the operator. Then, the management program and the monitor program are started.

  More specifically, as shown in FIG. 2, the host computer 50 is installed with programs such as a management program, a monitor program, a LAN communication driver, and an input / output driver, and each program is executed by the CPU of the host computer 50 under the management of the OS. Is executed.

  The motherboard 10 is installed with an engine control program, an IO driver, a PCI bus driver, a LAN communication driver, a monitor program, and the like, and each program is executed by the CPU 11 under the management of the OS.

  The engine control program executed by the CPU 11 of the motherboard 10 is composed of a collection of a plurality of tasks, and a plurality of functions for executing predetermined data processing are incorporated in each task.

  For example, a task that incorporates a function for determining the engine speed and crank angle based on a crank pulse signal input from the engine, a task that incorporates a function for determining a cylinder based on a crank signal and a cam signal, and each cylinder For example, a task in which a function for obtaining an injection timing and an ignition timing is incorporated, a task in which a function for obtaining a vehicle speed based on a vehicle speed pulse signal is incorporated, and the like.

  Each task includes a time synchronization task executed by a timer interrupt and a non-time synchronization task executed by an input / output interrupt. Timer interrupts, input capture interrupts, output compare interrupts, A / D conversion interrupts, and the like are included.

  The engine control program incorporates a real-time OS including a scheduler that manages each interrupt process based on a preset priority order, and the interrupt hand is activated by the scheduler according to the priority order.

  When the interrupt handler is activated, the task is activated after the values of the program counter and various registers are saved in the stack area partitioned in the memory 12, and when the task is completed, the saved program counter and various register values are displayed. It is restored and the interrupt process is completed.

  The scheduler manages the interrupt handler of the engine control program, reads the timer value managed by the internal timer 14, manages the start time and end time of each interrupt handler, and the task activated by each interrupt handler. The transition information of the interrupt handler, such as the execution state, that is, the suspended state in which the task processing is suspended by another interrupt handler having a higher priority, or the active state in which the task is processed, is managed and partitioned into the memory 12 The management information is stored in the interrupt processing management area.

  FIG. 3 shows that task D having a higher priority is activated while task E having a lower priority is executed, task C having a higher priority is activated while task D is being executed, and task D is terminated after task C is completed. It is shown that the task E is resumed and the task E is resumed after the completion.

  As shown in FIG. 3, the scheduler performs task name, priority, task start time, task end time, task processing time, task suspend time, task active for each task during interrupt handler start processing or end processing. Transition information such as time and the number of active tasks is stored in the interrupt processing management area.

  In response to an input / output interrupt generated by the microcomputers 24 and 25, which are peripheral resources provided in the IO board 20, an interrupt flag is set in the shared memory by the CPU 21 of the IO board 20, and the interrupt flag is set on the PCI bus. To the memory 12 of the motherboard 10.

  In the motherboard 10, when the interrupt processing unit 13 detects the occurrence of a PCI interrupt, the CPU 11 is interrupted, a PCI interrupt interrupt handler provided separately from the engine control program is activated, and the interrupt written in the memory 12 is started. In response to the flag, an interrupt request is issued to the scheduler of the engine control program. The scheduler activates an interrupt handler corresponding to the interrupt flag written in the memory 12.

  The evaluation monitor program is executed by the host computer 50 and the motherboard 10 and functions as a RAM monitor unit, a monitor condition setting unit, a monitor processing unit, a monitor data transmission unit, and a display processing unit.

  The RAM monitor unit monitors data exchanged with the shared memory provided on the I / O board 20 via the PCI bus, that is, variables, and displays the data in a shared memory monitor area partitioned by the memory 12 of the motherboard 10. When the monitor condition that is stored and set by the monitor condition setting unit is satisfied, the corresponding data is output from the shared memory monitor area to the host computer 50.

  The monitor condition setting unit includes an address setting unit that sets a predetermined task included in the engine control program or a start address of a predetermined function included in the task in the simulated microcomputer via the host computer 50; It includes a monitor data setting section for setting information for specifying data to be checked among data stored in the partitioned shared memory monitor area and setting monitor data to be compared with the data.

  The monitor processing unit matches the address set by the address setting unit with the value of the program counter of the simulated CPU, or the monitor data set by the monitor data setting unit matches the data in the shared memory monitor area. The execution state of the engine control program that is sometimes started and executed by the simulated CPU 11 is monitored and stored in a debug information management area partitioned in the memory 12.

  The monitor data transmission unit is monitored by the monitor processing unit and transmits the data stored in the monitor data area to the host computer.

  The display processing unit displays the monitor data transmitted by the monitor data transmission unit on the display device of the host computer 50.

  Among the monitor programs described above, the RAM monitor unit, a part of the monitor condition setting unit, the monitor processing unit, and the program that functions as the monitor data transmission unit are installed in the memory 12 of the motherboard 10 and a part of the monitor condition setting unit The display processing unit is installed in the host computer 50.

  A GUI operation screen for setting the execution conditions of the engine control program, the execution conditions of the monitor program for evaluation, and the like is displayed on the display device by the management program of the host computer 50, and the execution conditions set by the operator via the input device are displayed. The data is transmitted from the host computer 50 to the simulated microcomputer.

  Further, when the operator performs a start operation of the engine control program via the GUI operation screen, a start command is transmitted to the simulation microcomputer and the engine control program is started.

  The engine control program execution conditions include input / output data definition information exchanged between the motherboard 10 and the I / O board 20 via the shared memory, and allocation information of the start address of the input / output data to the shared memory. Among the data monitored by the RAM monitor unit, initial setting conditions such as information for specifying data to be transmitted to the host computer 50, operation commands for controlling start and stop of the engine control program, and the like are included.

  The execution conditions of the monitor program for evaluation are stored in the program address information of the task or function to be debugged among the tasks included in the engine control program, and the shared memory monitor area set as necessary. Among the variable data, the monitor data information for specifying the variable data that needs to be checked and the contrast data for comparing with the value of the variable data specified by the monitor data information are included. In addition, a plurality of variable data can be set in association with each other so that the variable data related to the variable data can be monitored simultaneously.

  The address setting unit writes the program address included in the execution condition of the monitor program transmitted from the host computer 50 in the PC interrupt register provided in the interrupt processing unit 13. A plurality of PC interrupt registers (five in this embodiment) are provided, and five program addresses can be set simultaneously.

  The monitor data setting unit stores the monitor data information and the comparison data in a debug information management area partitioned in the memory 12.

  The interrupt processing unit 13 includes a comparator that compares the program address written in the PC interrupt register with the program address of the engine control program executed by the CPU 11, and is configured to interrupt the CPU 11 when the two addresses match. ing.

  When the interrupt processing unit 13 interrupts the CPU 11, the OS determines the type of interrupt and activates an application corresponding to the interrupt type. If the interrupt is related to the engine control program, first, the scheduler of the engine control program is started, and the corresponding interrupt handler is started under the management of the scheduler.

  That is, when a task or function incorporated in the engine control program is executed by the CPU 11, the value of the program counter of the CPU 11 is set to the start address of the task or function, and the instruction at the address set in the program counter is set. The code is fetched, but an interrupt occurs at that time.

  As shown in FIG. 4, the monitor processing unit is activated by the interrupt, and reads the execution state of the engine control program, that is, the transition information of the interrupt handler stored in the interrupt processing management area by the scheduler over a predetermined time (SA1). And stored in the debug information management area (SA2). As a result, the state of the interrupt handler that activates the corresponding task or function and the other interrupt handlers nested at that time are captured.

  Further, when the monitor data information stored in the debug information management area is set (SA3), the monitor processing unit activates the RAM monitor unit (SA4), and the comparison data corresponding to the monitor data information And the variable data in the shared memory monitor area monitored by the RAM monitor unit (SA5), and when the two data match, the value of the data and related data are stored in the debug information management area for a predetermined time. (SA6).

  That is, the RAM monitor unit is configured to execute a normal process for storing data in the shared memory in the shared memory monitor area and a variable data comparison process activated by the monitor process unit.

  The transition information of the interrupt handler stored in the debug information management area and the variable data monitored by the comparison process are transmitted to the host computer 50 by the monitor data transmission unit (SA7), and displayed graphically on the display device by the display processing unit. (SA8).

  In other words, the monitor processing unit is configured to monitor the transition information of the interrupt handler including the interrupt handler that started the task or function and the variables on the memory operated by the task or function.

  Furthermore, the display processing unit is configured to display a task or function in which the variable is updated in association with the variable when the variable is updated.

  While the engine control program is being executed, it is monitored by the RAM monitor unit, and the data set in the initial setting conditions is transmitted to the host computer 50 at a predetermined interval together with the time data of the internal timer, and the display processing unit displays the data. Is displayed graphically as a trend graph.

Below, the example of a screen displayed by the display process part is demonstrated.
FIG. 5 shows a state in which the task execution state is displayed in a bar graph in real time by the display processing unit based on the transition information of the interrupt handler transmitted from the monitor data transmission unit.

  The vertical axis indicates the priority of the task, and the higher the task is, the higher the priority is. The horizontal axis shows time. Nested interrupts occur, and the period during which a task with a lower priority is suspended is hatched. In addition, the task in the active state is filled with a color corresponding to the priority order to improve visibility.

  In this example, the start address of a predetermined function incorporated in the task E is set in the interrupt register, and the monitor processing unit is activated when the CPU 11 equals the value of the program counter. Thereafter, the task is executed for a predetermined time. The state is monitored.

  The bar graph shows that the execution of the function is marked with an asterisk and that the specified specific function is called. Also, right-clicking the star marking position pops up the function name, call task name, and variable data measurement conditions (comparison data).

  When right-clicking on any bar graph displayed, the task name, priority, number of active tasks, and task status are displayed in a hop-up manner.

  When the operator performs a stop operation of the engine control program via the GUI operation screen, a stop command is transmitted to the simulation microcomputer, and the engine control program is stopped.

  6 shows that the task execution state is displayed by the display processing unit after the engine control program is stopped based on the transition information of the interrupt handler transmitted from the monitor data transmission unit under the same condition setting as FIG. Indicates the state displayed in a graph.

  When right-clicking the marking position of the star, the function name, calling task name, variable data measurement conditions (comparison data), and associated variable data are popped up. Also, right-clicking on any displayed bar graph displays the task name, priority, task processing time, task suspend time, and task actual operation time as a hop-up display.

  The operator operates or visually checks such a display screen to confirm the execution state of the task or function to be evaluated.

  As described above, in the software development apparatus according to the present invention, the corresponding task can be executed by simply changing and setting the start address of the task or function corresponding to the task to be debugged without editing the source program. Whether or not the value of the variable at that time changes in this way.

  Hereinafter, embodiments will be described. In the above-described embodiment, the case where the control program executed and verified by the simulation microcomputer is the engine control program has been described. However, the control program to which the present invention is applied is not limited to this and is installed in the vehicle. Another ECU control program may be used.

  The control program is not limited to the one installed in the vehicle, but can be widely applied to the development of embedded software such as an OA device provided with a control microcomputer.

  The specific configuration of the above-described software development apparatus is merely an example, and the specific configuration of each part such as a mother board and an I / O board should be appropriately constructed using a known technique as long as the effects of the present invention are achieved. Needless to say, you can.

1: Software development device 10: Motherboard 11: CPU (simulated CPU)
12: Memory 20: I / O board 24, 25: Simulated peripheral circuit (microcomputer)
50: Host computer

Claims (5)

A CPU that executes a control program and a microcomputer in which its peripheral circuit is incorporated is simulated, a memory that stores the control program, a simulation CPU that executes a control program stored in the memory, and the peripheral circuit A simulation microcomputer having a simulation peripheral circuit to be simulated;
A host computer for managing the simulated microcomputer;
Is a software development device connected to the network,
An address setting unit that sets a predetermined task included in the control program or a start address of a predetermined function included in the task to the simulated microcomputer via the host computer;
A monitor processing unit that is activated when the address set by the address setting unit matches the value of the program counter of the simulated CPU and that monitors the execution state of the control program by the simulated CPU, and is monitored by the monitor processing unit A monitor data transmitter for transmitting the received data to the host computer;
A software development device comprising:   The monitor processing unit monitors transition information of an interrupt handler including an interrupt handler that has started the task or function, and a variable on a memory operated by the task or function. Software development equipment.   The host computer includes a display processing unit that graphically displays an execution state of the task or function or a variable update state based on monitor information transmitted from the monitor data transmission unit. Item 3. The software development device according to item 1 or 2.   The software development apparatus according to claim 3, wherein when the variable is updated, the display processing unit displays the task or function that updated the variable in association with each other. A CPU that executes a control program and a microcomputer in which its peripheral circuit is incorporated is simulated, a memory that stores the control program, a simulation CPU that executes a control program stored in the memory, and the peripheral circuit A simulation microcomputer having a simulation peripheral circuit to be simulated;
A host computer for managing the simulated microcomputer;
Is a debugging method using a software development device connected to a network,
An address setting step of setting a predetermined task included in the control program or a start address of a predetermined function included in the task in the simulated microcomputer via the host computer;
A monitoring step that starts when the address set in the address setting step and the value of the program counter of the simulated CPU match, monitors the execution state of the control program by the simulated CPU, and transmits to the host computer; ,
A display processing step for graphically displaying an execution state of the task or function or an update state of a variable operated by the task or function based on the monitor data transmitted in the monitoring step;
A debugging method characterized by executing