JPS59116864A - Measurement system for use rate of central processing unit - Google Patents

Abstract

PURPOSE:To measure the use rate of a CPU by setting an FF corresponding clock level processing and base level processing only while they are carried out, and measuring externally the time ratio of its set state. CONSTITUTION:When a clock interruption signal is generated, an FF 1 is set to generate (1) as its Q output. This state is held until a reset signal is applied to the FF 1 under programmed control after the base level processing is completed. A pulse generating circuit 3 which generates pulses of specific frequency is connected to an AND gate 2. Therefore, the output of the FF 1 is inputted to a counter circuit 4 through a gate 2 and counted. The circuit 4 is reset at specific intervals of time, so the number of pulses received within the specific time is sent to a display device 6 through a decoder circuit 5 and displayed. The display uses decimal representation.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an electronic switching system having a central processing unit, in which the central processing unit executes clock level processing, pace level processing, etc. Related to the central processing unit usage rate measurement method that measures what percentage of the total time including time It scans for calls, detects which lines have been disconnected, and performs other processes as well. Of these, the former periodic processing, such as line status scanning and relay drive for sending dial signals to other stations, is called clock level processing, and the other processing is called pace level processing. This clock level processing is performed periodically and is executed with priority over pace level processing. Therefore, pace level processing is performed following this clock level processing, and once pace level processing is completed, the next The central processing unit remains in an unused state (idle state) until the clock level processing cycle comes.

In an electronic switching system, it is necessary to measure the usage rate of the central processing unit in order to manage the equipment, and the usage rate is calculated at regular intervals and its operating status is monitored. There is. Here, the usage rate U can be obtained by the following equation, assuming that the clock level processing time is T11, the pace level processing time is T3, and the unused state is T3.

Conventionally, in order to measure the usage rate of the central processing unit in an electronic switching system, an execution management program runs a separately prepared timer while the central processing unit is idle, and based on that value, the execution management program The usage rate of the processing device was determined by calculation. For example, when the central processing unit operates as shown in FIG.
Next, pace level processing is performed. When the base rail processing is finished, the execution management program operates a timer to measure the idle time T3 until the next clock level processing starts, and based on the sum of the T3 values, the central processing was calculating the usage rate.

Therefore, in order to measure and calculate the usage rate of the central processing unit, it is necessary to run another processing routine, which has the disadvantage that the processing capacity of the system is reduced, albeit slightly. The purpose of the invention is to improve such drawbacks by making it possible to easily and accurately measure the usage rate of a central processing unit from the outside without performing calculations that affect exchange processing. An object of the present invention is to provide a central processing unit usage rate measurement method that does not require internal processing for usage rate measurement.

Structure of the Invention In order to achieve this object, the central processing unit usage rate measurement method of the present invention uses clock level processing for periodically executed processing, pace level processing for other processing, and In an electronic switching system that has a central processing unit in which clock level processing is activated by a clock interrupt that occurs periodically, the central processing unit is used to indicate when the central processing unit is in use and can be read from the outside at the same time as a clock interrupt occurs. By setting the flip-flop of , and resetting the flip-flop at the same time as the pace level processing is completed, the flip-flop is set only while the clock level processing and pace level processing are being executed, and the flip-flop is set. The present invention is characterized in that the usage rate of the central processing unit is measured by externally measuring the percentage of time in the set state.

Examples of the invention An embodiment of the present invention will be described with reference to FIGS. 1 and 2.

Figure 1 (a) is an explanatory diagram of the use state of the central processing unit in the electronic switching system, (b) is an explanatory diagram of the output state of the flip-flop circuit in Figure 2, and (c) is an explanatory diagram of the output state of the flip-flop circuit in Figure 2. FIG. 2 is a configuration diagram of an embodiment of the present invention.

In the figure, 1 is a flip-flop circuit (hereinafter referred to as FF);
2 is an AND f-), 3 is a t4 pulse generation circuit, 4 is a counter circuit, 5 is a decoder circuit, and 6 is a display device.

FFI has a period T for the central processing unit to perform clock level processing. It is reset by a clock interrupt signal that is generated every time, and is reset by a base level processing end signal that is generated when the software finishes pace level processing. By the way, in an electronic switching system, the exchange processing of the central processing unit includes a clock level process that is periodically activated in response to a clock interrupt, and a pace level process that is executed after the completion of the process, as shown in Figure 1 (a). There is processing. Therefore, when a clock interrupt signal occurs, the FF
I is in the set state and the Q output is "1", and this state continues until a reset signal is applied to the FFI under the control of the program after the pace level processing is completed. By repeating this operation, the output of fiFFl is as shown in Figure 1 (b).
It will be as shown below.

Further, a pulse generating circuit 3 is connected to the AND gate 2, and this pulse generating circuit 3 generates, for example, a pulse of 1. Therefore, as shown in Figure 1 (b), F
Since the output of F1 is applied to the AND gate 2, the AND gate 2 outputs a signal as shown in FIG. 4 Rus number is counted. By the way, the counter circuit 4 is reset by a reset signal applied at fixed time intervals, for example, every second, so the number of pulses received within a fixed time is sent to the display device 6 via the decoder circuit 5. Display. Therefore, in this embodiment, the pulse generation circuit 3 generates a pulse of 1 (Z (1,000,000/ygC)), and the counter circuit 4 is reset at a cycle of 1 second, so the display device 6 displays the data in decimal notation. By displaying only the top 3 digits out of 7 digits, it is possible to display the usage rate of the central processing unit at 1 second intervals.Therefore, by simply adding an external measurement circuit as shown in Fig. The utilization rate can be determined without any loss in the processing capacity of the device.

Another embodiment of the invention will be described with reference to FIG.

In FIG. 3, an integrating circuit 7 is connected to the Q terminal of the FF 1, and the integrated value of the integrating circuit 7 is displayed on a display device 8.

In this case, the output signal of the FFI shown in FIG.
The duty value of the output signal of the FFI is determined by the integrating circuit 7.
will be output from. Therefore, the duty value can be displayed on the display device 8, and since this duty value is proportional to the usage efficiency of the central processing unit, the usage rate can be read directly from the display device 8, which is also a meter. .

Effects of the Invention According to the present invention, the FF is set by the clock interrupt signal of the central processing unit, reset when it becomes an empty state, and the OFF state is read from the outside. It becomes possible to measure the usage rate effectively and very easily without any loss of processing capacity.

[Brief explanation of the drawing]

Figure 1 (a) is an explanatory diagram of the usage state of the central processing unit in the electronic switching system, (b) is an explanatory diagram of the output state of the flip-flop circuit in Figure 2, and (c) is an illustration of the output status of the flip-flop circuit in Figure 2. 2 is a diagram illustrating the configuration of one embodiment of the present invention, and FIG. 3 is a diagram illustrating the configuration of another embodiment of the present invention. In the figure, 1 is a frizzo flop circuit, 2 is an AND dart, 3 is a pulse generation circuit, 4 is a counter circuit, 5 is a decoder circuit, 6 is a display device, 7 is an integration circuit, and 8 is a display device. Patent applicant Fujitsu Limited

Claims (3)

[Claims] (1) Clock level processing for periodically executed processing;
In an electronic switching system having a central processing unit in which other processing is called pace level processing, and clock level processing is given execution priority and clock level processing is activated by a clock interrupt that occurs periodically, clock interrupts occur. At the same time, by setting an externally readable flip-flop to indicate that the central processing unit is in use, and resetting the flip-flop at the same time as the pace level processing is completed, the clock level processing and pace level processing are executed. A central processing unit characterized in that the usage rate of the central processing unit is measured by setting the flip-flop in a set state and externally measuring the percentage of time that the flip-flop is in the set state. Utilization measurement method. (2) A pass counter is connected to the flip-flop, and the noggle counter is operated when the flip-flop is in a set state. Central processing unit utilization measurement method described. (3) The central processing unit according to claim 1, characterized in that an integrating circuit and a display device are connected to the flip-flop so that an integrating operation is performed when the flip-flop is in a set state. Utilization measurement method.