JPH09320258A - Sdram, memory module and data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique which reduces the cost of a memory module provided with a parity function. SOLUTION: In accordance with plural data mask signal terminals DQM 0-DQM3, installed in correspondence with data input/output terminals I/O 0-I/O 3 and the logic of the signals given to individual data mask terminals from outside, a SDRAM(Synchronous Dynamic Random Access Memory) is formed, including input control circuits 700-703 and output control circuits 800-803 which allow to control the data input/output from the corresponding data input/output terminals. Such a SDRAM is used as the one exclusively for parity and other inexpensive SDRAMs having no parity function are applied in plural numbers, thereby reducing the cost of memory modules.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous dynamic random sync which can operate in synchronization with an external clock.
The present invention relates to an access memory (abbreviated as SDRAM) and a technique effectively applied to a main memory of a data processing device such as a computer system.

[0002]

2. Description of the Related Art DRAM as an example of a semiconductor memory device
Is an address buffer, a decoder, as described in "LSI Handbook (Page 486-)" issued by Ohmsha, Ltd. on November 30, 1984.
A peripheral circuit such as a sense amplifier uses a dynamic circuit that operates in synchronization with a clock to reduce power consumption. The DRAM requires external clocks of one to three phases, and an internal circuit clock is generated based on these clocks to control or drive the peripheral circuits. In such a DRAM,
Random access is mainly performed, and a memory cell is selected by sequentially reading a row address and a column address for each access. Each part of the peripheral circuit is controlled by an internal clock so as to follow the procedure of row selection, detection of memory cell information, and column selection in order to prevent information destruction of memory cells. In a normal DRAM mounted on a system, a read / write operation is performed asynchronously with a system clock, while an SDRAM is a semiconductor memory device operated in synchronization with the system clock. This SDRAM has data in synchronization with a clock,
Since the address and control signals can be input / output, a large-capacity memory similar to DRAM can be operated at high speed comparable to SRAM, and some data can be accessed to one selected word line. By designating this by the burst length, a plurality of data can be continuously read or written by sequentially switching the selected states of the column system by the built-in column address counter.

[0003]

Since the SDRAM can read and write data at high speed, it is very effective to use it for the main memory of the computer system. In that case, the parity function is considered to be essential in order to increase the reliability of the data handled in the main memory. As a main memory of a computer system, it is cost effective to apply it as a memory module formed by mounting a plurality of SDRAMs on a single board.

For example, SDRA with parity bit
M is × 9 bits (meaning that data input / output can be performed in 9-bit units), and such SDRAM has 4
By combining them individually, a memory module corresponding to the 36-bit bus can be formed. In this case, the parity bit is 1 bit for each SDRAM,
Of the 36-bit bus, 4 bits are used for parity bits.

However, S with a parity bit
Since a DRAM is more expensive than one that does not have it, forming a memory module by combining four such expensive SDRAMs impedes the cost reduction of the memory module.

An object of the present invention is to provide a technique for reducing the cost of a memory module with a parity function.

It is an object of the present invention to provide a data processing device having a memory module whose cost is reduced by such a technique as a main memory.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the data input / output terminals (I / O0-
Data mask signal terminals (DQM0 to DQM3) provided corresponding to I / O3) and data from corresponding data input / output terminals according to the logic of signals externally applied to the individual data mask terminals. An SDRAM is configured by including control circuits (700 to 703, 800 to 803) capable of individually controlling input and output. According to this, in the case of forming a memory module by combining a plurality of SDRAMs, by using one dedicated for parity, an inexpensive one having no parity function can be applied as another SDRAM. This achieves a cost reduction of the memory module with parity function.

Of the plurality of data mask terminals, a signal from a specific terminal (DQM0) is replaced with a signal from other data mask terminals (DQM1 to DQM3), and the control corresponding to the other data mask terminals is performed. A switching circuit (101, 103) that can be supplied to the circuit can be provided.
According to it, in the same SDRAM, a normal SD
Selective switching between the first mode as the RAM and the second mode as the SDRAM for parity is achieved. A memory module is configured to include such SDRAM, and a data processing device is formed by using such a memory module as a main memory.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 7 shows a computer system which is an example of a data processing device according to the present invention.

This computer system includes a CPU (Central Processing Unit) 310, R via a system bus BUS.
AM (random access memory) 320, ROM
(Read-only memory) 340, peripheral device control unit 3
The display controller 360 and the display controller 360 are connected to each other so that signals can be exchanged therebetween, and are configured as a computer system that performs predetermined data processing in accordance with a predetermined program. The CPU 310 is a logical core of this system, and mainly addresses, reads and writes information, operates data, sequences instructions, accepts interrupts, activates information exchange between a storage device and an input / output device, etc. It has the function of, and is composed of an arithmetic control unit, a bus control unit, a memory access control unit, and the like. RAM320 or ROM
340 is positioned as an internal storage device. RA
The M320 stores programs and data required for calculation and control by the CPU 310, and is also called a main memory. The external storage device 380 is controlled by the peripheral device control unit 350.
And the information input control from the keyboard 390 and the like. Further, by the display control unit 360,
Information display control on the CRT display 370 is performed.

The RAM 320 includes a synchronous dynamic random memory capable of operating in synchronization with an external clock.
A memory module in which a plurality of access memories (SDRAM) are combined is applied. The memory module is not particularly limited, but as shown in FIG.
SDRAMs 11 to 14, and parity SDRAM 1
5 and 5 are combined into a single board. SDRAM1
1 to 14 are x8-bit configurations, SD for parity
The RAM 15 has a x4 bit configuration. Since the SDRAM 15 dedicated to the parity bit is provided, SD
The RAMs 11 to 14 are inexpensive S that do not have a parity function.
DRAM is applied. Such SDRAMs 11-1
4 and the SDRAM 15 for parity are combined to make the input / output bit configuration 36 bits. Of these, 32 bits are for data and the remaining 4 bits are for parity bits. Bus BUS shown in FIG.
Has a 36-bit configuration, and the memory module shown in FIG. 1 is coupled to the bus BUS through a group of terminals formed on the edge of the module.

FIG. 6 shows an example of the structure of the SDRAM 15 for parity.

The SDRAM for parity 15 shown in FIG.
Is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique, and the memory array 200A forming the memory bank A and the memory array 20 forming the memory bank B are formed.
With 0B. Each memory array 200A, 20
0B includes dynamic type memory cells arranged in a matrix. According to the drawing, the selection terminals of the memory cells arranged in the same column are connected to word lines (not shown) for each column and arranged in the same row. The data input / output terminals of the stored memory cells are coupled to complementary data lines (not shown) row by row.

One word line (not shown) of the memory array 200A is driven to the selection level according to the decoding result of the row address signal by the row decoder 201A. The complementary data line (not shown) of the memory array 200A is coupled to the sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplification circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column switch circuit in that is a switch circuit for individually selecting complementary data lines and conducting to the complementary common data lines. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A. Similarly, on the memory array 200B side, the row decoder 201B,
A sense amplifier and column selection circuit 202B and a column decoder 203B are provided. The complementary common data line 20
4 is a data input / output terminal I / O via the input / output unit 210
0 to I / O3 are connected. In addition, the input / output unit 210
Is provided with data mask signal terminals DQM0 to DQM3 for receiving a data mask signal from the outside.
The input / output unit 210 will be described later in detail. The data input / output from the corresponding data input / output terminal is controlled according to the logic of the signal externally applied to the data mask signal terminals DQM0 to DQM3. For example, when any of the data mask signal terminals DQM0 to DQM3 is set to the low level, the input / output terminals I / O0 to I / O0
Data input / output is restricted in the corresponding bit of I / O3.

The row address signal and the column address signal supplied from the address input terminals A0 to A11 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. The row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal in the refresh operation mode. The output of the column address buffer 205 is supplied as preset data of the column address counter 207, and the column address counter 207 outputs the column address signal as the preset data or a value obtained by sequentially incrementing the column address signal according to the operation mode. , To the column decoders 203A and 203B.

The controller 212 is not particularly limited, but may be a clock signal CLK and a clock enable signal CK.
E, chip select signal CS * (symbol * means row enable or signal inversion), column address strobe signal CAS *, row address strobe signal RAS
External control signals such as * and the write enable signal WE * and control data from the address input terminals A0 to A11 are supplied, and the operation mode of the SDRAM and the above circuit block are based on the level of these signals and the timing of change. It forms an internal timing signal for controlling the operation of the control circuit, and includes a control logic (not shown) for that purpose and a mode register 300. Various control signals such as the clock signal CLK, the clock enable signal CKE, and the chip select signal CS * are supplied to the CPU 3
1 through the system bus BUS.

The clock signal CLK is SDRA for parity.
It is used as the master clock of M15. The chip select signal CS * indicates the start of a command input cycle by its low level. When the chip select signal CS * is at high level (chip non-selected state), other signal inputs have no meaning. However, the internal operation such as the selected state of the memory bank or the burst operation is not affected by the change to the chip non-selected state. Each signal of RAS *, CAS *, and WE * is a significant signal when defining a command cycle. The clock enable signal CKE is a signal indicating the validity of the next clock signal, and the signal CK
When E is high level, the next rising edge of the clock signal CLK is valid, and when it is low level, it is invalid. The row address signal is the clock signal CLK.
A0 in the row address strobe / bank active command cycle synchronized with the rising edge of
ＡA11.

The input from the terminal A11 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A11 is low level, the memory bank A is selected,
When the level is high, the memory bank B is selected. The selection control of the memory bank is not particularly limited, but only the row decoder on the selected memory bank side is activated, all the column switch circuits on the unselected memory bank side are unselected, and the input / output unit 210 on the selected memory bank side only is controlled. It can be performed by processing such as connection.

The input of the terminal A11 in the precharge command cycle indicates the mode of the precharge operation for the complementary data line or the like, and its high level indicates that the precharge target is both memory banks, and its low level. Indicates that one of the memory banks designated by A11 is to be precharged. The column address signal is defined by the levels of the terminals A0 to A7 in the read or write command cycle synchronized with the rising edge of the clock signal CLK. The column address defined in this way is used as a start address for burst access.

FIG. 2 shows a configuration example of the mode register 300.

The mode register 30 is not particularly limited.
0 includes an operation mode register 300A and a test mode register 300B. When the mode set signal is asserted to a low level, information can be set (held). Although not particularly limited, each of the operation mode register 300A and the test mode register 300B has a 12-bit configuration. The seventh signal A7 is an enable bit, and the setting of the test mode register 300B and the setting of the operation mode register 300A are selected depending on the state of the enable bit. For example, a chip select signal CS *, a row address strobe signal RAS *, a column address strobe signal CAS
When all of *, the write enable signal WE *, and the signal A7 are at the low level, setting to the operation mode register 300A is enabled. At this time, the test mode register 300B is reset. When the chip select signal CS *, the row address strobe signal RAS *, the column address strobe signal CAS *, and the write enable signal WE * are at a low level, and the signal A7 is at a high level, setting to the test mode register 300B is possible. It is said.

In the operation mode register 300A, bits 0 to 6 are used as the operation mode setting area, although not particularly limited thereto. The operation mode information set in the operation mode setting area includes burst length, burst type (BT), and column address strobe signal CAS *.
Includes CAS latency and the like indicating in what cycle the data is output after the assertion of. The maximum burst length is eight types, the maximum burst type is two types, and the CAS latency is maximum eight types. The burst length is set to bits 0 to 2, the burst type is set to bit 3, and the CAS latency is set to bits 4 to 4.
Set to 6. The set operation mode information is transmitted to the control system circuit 85. The control system circuit 85 is a part of the controller 212 shown in FIG. 1 and controls the operation of each part based on the operation mode information set in the operation mode register 300A.

FIG. 2 shows a configuration example of the input / output unit 210.

The input / output unit 210 has a data input / output terminal I /
Data input buffers 200 to 203, data output buffers 300 to 301, corresponding to O0 to I / O3, respectively.
Input gates 400-403, output gates 500-503
Is provided. In addition, the data input / output terminals I / O0 to I /
Data mask terminals DQM0 to DQM3 corresponding to O3
Are provided for the data mask terminals DQM0 to DQM3.
Corresponding to, DQM buffers 600 to 603, input control circuits 700 to 703, and output control circuits 800 to 803 are provided. In FIG. 2, a circuit corresponding to the input / output terminal I / O2 and a circuit corresponding to the data mask terminal DQM2 are omitted.

Circuits corresponding to the data input / output terminals I / O0 to I / O3 and the data mask terminals DQM0 to DQM3.
Since the circuits corresponding to (1) and (2) have the same configuration, the circuit corresponding to the data input / output terminal I / O0 and the circuit corresponding to the data mask terminal DQM0 will be described in detail below.

The data input / output terminal I / O0 has an input terminal of the data input buffer 200 and the data output buffer 30.
The 0 output terminals are tied together. Data input / output terminal I / O0
The data input from is transmitted to the gate 400 via the data input buffer 200. The output data of the gate 500 is input / output terminal I through the data output buffer 300.
Externally output from / O0. The data mask signal is DQ
It is transmitted to the input circuit 700 and the output control circuit 800 via the M buffer 600. Data input buffer 20
0, data output buffer 300, DQM buffer 600
The clock signal CLK is input to the
Data output and data mask signal acquisition are performed in synchronization with the clock signal CLK. Further, the input circuit 700 and the output control circuit 800 have read signals φR and write signals φW from the controller 212.
Is entered.

In the case where the data mask signal applied to the data mask terminal DQM0 is high level, if the read signal φR from the controller 212 is high level, the output signal DOE0 of the output control circuit 800 is set to high level. , The gate 500 is activated. At this time, the sense amplifier and column selection circuit 2 shown in FIG.
Output data Dout0 from 02A or 202B is externally output from the data input / output terminal I / O0 via the gate 500 and the data output buffer 300. However, when the data mask signal applied to the data mask terminal DQM0 is at the low level, the output signal DOE0 from the output control circuit 800 goes to the low level, and the gate 500 is closed. Output data Dout from the column selection circuit 202A or 202B
0 is not output to the outside. The same control is performed when data is fetched from the data input / output terminal I / O0. That is,
When the data mask terminal DQM0 is at the high level and the write signal φW from the controller 212 is at the high level, the output signal WT of the input control circuit 700
E0 is set to the high level and the gate 400 is opened. At this time, the data input from the data input / output terminal I / O0 is transferred to the gate 400 via the data input buffer 200.
The sense amplifier and column selection circuit 202A or 2 shown in FIG.
It is transmitted to 02B.

Similarly, the data input / output terminals I / O1 to I /
A circuit corresponding to O3 and data mask terminals DQM1 to
The circuit corresponding to DQM3 also operates in the same manner as in the above case.

In this way, the data input / output terminals I / O0-
Data mask terminals DQM0 to DQ corresponding to I / O3
M3 is provided and the data mask terminals DQM0 to DQ are provided.
Corresponding to M3, DQM buffers 600 to 603, input control circuits 700 to 703, output control circuits 800 to 803
Is provided, and the output gate 4 is provided based on the output signals of the input control circuits 700 to 703 and the output control circuits 800 to 803.
Since the operations of 00 to 403 and 500 to 503 are controlled, the data mask terminals DQM0 to DQM3 can perform data input / output control in input / output terminal units. Therefore, in the RAM 320 shown in FIG.
For parity bits of M11 to 14, S for parity
When the input and output bits of the DRAM are assigned one by one, the parity bit can be set according to the memory usage in the computer system to which this memory module is applied. For example, when all the SDRAMs 11 to 14 are used by the CPU 310, in the SDRAM 15 for parity, all of the data mask terminals DQM0 to DQM3 are set to the high level and the parity is set to 4 bits. In addition, the CPU 310 causes S
SD for parity when DRAM 11 and 12 are used
In the RAM 15, the data mask terminals DQM0 and DQM0, D
QM1 is set to high level and data mask terminal DQM
The parity is set to 2 bits by setting DQM3 and DQM3 to low level.

As the SDRAMs 11 to 14 shown in FIG. 1, ordinary inexpensive SDRAMs having no parity function are applied.

The SDRAMs 21, 22, 23 and 24 are basically constructed as shown in FIG. 6, similarly to the SDRAM 15 for parity. However, the configuration of the input / output unit 210 is significantly different from that of the SDRAM 15 for parity.
That is, the input / output unit 210 in the SDRAMs 21, 22, 23, 24 is provided with the input / output terminals I / O0 to I / O3 and the circuits corresponding thereto as shown in FIG. 4, but the data mask terminal DQM. Has one terminal, and as a circuit corresponding thereto, the DQM buffer 90
0, an input control circuit 901, and an output control circuit 902 are provided. Output signal WTE of input control circuit 901
Are simultaneously supplied to the output gates 400 to 403, and the output signal DOE of the output control circuit 902 is supplied to the gates 500 to 50.
3 will be supplied at the same time. Therefore, all I / Os are controlled simultaneously by the data mask signal applied to one data mask terminal DQM.

FIG. 3 shows a memory module to be compared with this embodiment.

The memory module 250 shown in FIG.
Are SDRAMs 21, 22, 22 each having a × 9 bit configuration.
By mounting 23 and 24 on a single board,
It is configured as a memory module compatible with a 36-bit bus. Each of the SDRAMs 21 to 24 has a parity bit of 1 bit. As described above, the SDRAM having the parity bit is more expensive than the SDRAM having no parity bit. Therefore, as shown in FIG.
A memory module having 4 mounted therein becomes very expensive, which hinders the cost reduction of a computer system including the memory module. On the other hand, in the memory module shown in FIG. 1, a dedicated memory for parity is provided, and inexpensive SDRAMs having no parity function are applied as the four SDRAMs 11 to 14 for data. It can be provided at a lower cost than the memory module shown in FIG.

FIG. 5 shows another configuration example of the input / output unit 210.

The configuration shown in FIG. 5 is largely different from that shown in FIG. 2 in that a plurality of data mask terminals DQM0 are provided.
-DQM3, a signal from the terminal DQM0 is replaced with a signal from another data mask terminal, and a multiplexer (MPX) 101 that can be supplied to an input control circuit and an output control circuit corresponding to the other data mask terminal, It has a point 103. Although the data mask terminal DQM2 and the circuit corresponding thereto are omitted in FIG. 5,
It should be understood that a multiplexer 102 is provided as a circuit corresponding to the multiplexers 101 and 103 in the circuit corresponding to the data mask terminal DQM2.

For example, the multiplexers 101 to 103 respectively cause the data mask terminals DQM1 to DQM3.
When the output signals of the DQM buffers 601 to 603 corresponding to are selected, the circuit shown in FIG.
Is equivalent to the circuit shown in, and the data mask terminal DQM
Since I / O can be individually controlled by inputting signals from 0 to DQM3, it is suitable as a parity SDRAM when forming the memory module shown in FIG. On the other hand, the multiplexers 101 to 1
03 corresponding to the data mask terminal DQM0
When the output signal of the QM buffer 600 is selected,
All input control circuits 700 to 703 and output control circuit 8
00 to 803 are supplied with the data mask signal from the data mask terminal DQM0, and the data mask terminals DQM1 to DQM1 to
The signal input to DQM3 is invalid. Therefore, the circuit in that case is equivalent to the circuit shown in FIG. 4 in that all the I / Os are controlled simultaneously by the data mask signal applied to one data mask terminal. That is, the SDRA including the input / output circuit 210 shown in FIG.
M can be applied to the SDRAMs 11 to 14 shown in FIG. 1 or can be applied as the parity SDRAM 15. The operations of the multiplexers 101 to 103 are controlled by the control system circuit 85 according to the setting contents of the mode register 300. For example, as shown in FIG. 8, in the operation mode register 300A,
Since bits 8 to 11 are normally reserved bits, it is preferable to write the setting information of the multiplexers 101 to 103 here and generate the operation control signals SEL1 to SEL3 of the multiplexers 101 to 103 according to the information. .

According to the above embodiment, the following operational effects can be obtained.

(1) Data input / output terminals I / O0 to I / O
A plurality of data mask signal terminals DQ provided corresponding to
An input control circuit 70 capable of controlling data input / output from the corresponding data input / output terminals in accordance with M0 to DQM3 and the logic of signals externally applied to individual data mask terminals.
0 to 703 and output control circuits 800 to 803
By forming the DRAM 15, a plurality of SDRAs can be formed.
When a memory module is formed by combining Ms, by using one SDRAM 15 dedicated to parity, a plurality of inexpensive SDRAMs having no parity function can be applied. Considering that an SDRAM having a parity function must be more expensive than a general-purpose product without it, a large number of SDRAMs are required.
In the case of forming a memory module by combining DRAMs, it is very advantageous to use a large number of general-purpose products without a parity function in order to reduce the cost of forming the memory module. Therefore, as mentioned above, SDR
One AM15 is used only for parity, and another SDRA is used.
When a plurality of inexpensive Ms having no parity function are applied as M, for example, as shown in FIG. 3, all SDRAMs forming a memory module (21 to 24) having a parity function are applied. Compared to
The formation cost of the memory module can be reduced, and the memory module having the parity function can be provided at low cost.

(2) A signal from a specific terminal DQM0 among a plurality of data mask terminals is transferred to another data mask terminal D.
Instead of the signals from QM1 to DQM3, by providing multiplexers 101 and 103 that can be supplied to the input control circuits 701 to 703 and the output control circuits 801 to 803 corresponding to the other data mask terminals, a single SDRAM is provided.
In, it is possible to selectively switch between the first mode as a normal SDRAM and the second mode as a parity SDRAM.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

For example, although the memory module corresponding to the 36-bit bus has been described in the above example, each S
Number of input / output bits of DRAM, or SD combined
By adjusting the number of RAMs, it is possible to support a bus of 36 bits or less or a multi-bit bus of more than 36 bits.

In the above description, the case where the invention made by the present inventor is applied mainly to the computer system which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto and various data processings are performed. It can be widely applied to devices.

The present invention can be applied on condition that it has at least a data input / output terminal having a plurality of bits.

[0047]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of data mask signal terminals are provided corresponding to the data input / output terminals, and data from the corresponding data input / output terminals is output according to the logic of signals externally applied to the individual data mask terminals. By configuring an SDRAM including a control circuit capable of individually controlling input / output, in the memory module, such SD
By using one RAM exclusively for the parity, an inexpensive SDRAM having no parity function can be applied as another SDRAM, so that the cost of the memory module with a parity function can be reduced.

A switching circuit capable of replacing a signal from a specific terminal among the plurality of data mask terminals with a signal from another data mask terminal and supplying it to a control circuit corresponding to the other data mask terminal. By providing the above, it is possible to realize selective switching between the first mode as a normal SDRAM and the second mode as a parity SDRAM in the same SDRAM.

It is possible to form a memory module including the SDRAM having the above effect and further form a data processing device using such a memory module as a main memory. Due to the cost reduction of the memory module, it is possible to reduce the cost of the data processing device to which it is applied as the main memory.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a memory module according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration example of an input / output unit included in an SDRAM forming the memory module.

FIG. 3 is a block diagram of a configuration example of a memory module used as a comparison target of the memory module shown in FIG.

FIG. 4 is another SDRA forming the memory module.
FIG. 3 is a block diagram showing a detailed configuration example of an input / output unit included in M.

5 is a block diagram of another configuration example of the input / output unit shown in FIG.

FIG. 6 is a block diagram showing an overall configuration example of the SDRAM.

FIG. 7 is a block diagram of an overall configuration example of a computer system including the memory module.

FIG. 8 is a diagram illustrating a configuration of a mode register in the SDRAM.

[Explanation of symbols]

 11-14 SDRAM 15 SDRAM for parity 101-103 Multiplexer 200-203 Data input buffer 300-303 Data output buffer 400-403 Output gate 500-503 Input gate 600-603 DQM buffer 700-703 Input control circuit 800-803 Output control Circuit 200A, 200B Memory array 201A, 201B Row decoder 203A, 203B Column decoder 205 Column address buffer 206 Row address buffer 207 Column address counter 208 Refresh counter 210 Input / output section 212 Controller 300 Mode register I / O0 to I / O3 Input / output buffer DQM0 to DQM3 Data mask terminal 310 CPU 320 RAM 340 ROM 350 Peripheral device Control unit 360 display control unit 370 CRT display 380 external storage device 390 keyboard

Claims (4)

[Claims] 1. An SDRAM having a data input / output terminal having a plurality of bits, and a data input / output operation from the data input / output terminal is synchronized with a clock, a plurality of which are provided corresponding to the data input / output terminals. Data input / output from the corresponding data input / output terminal is individually performed according to the logic of the data mask signal terminal and the above-mentioned data mask terminal provided externally to each data mask signal terminal. An SDRAM including a control circuit capable of controlling. 2. A switching method in which a signal from a specific terminal of the plurality of data mask terminals is replaced with a signal from another data mask terminal and can be supplied to the control circuit corresponding to the other data mask terminal. The S of claim 1 including a circuit.
DRAM. 3. A memory module comprising a plurality of SDRAMs mounted on a single board, the combination of the plurality of SDRAMs capable of handling data having a bit configuration exceeding the number of data input / output bits of each SDRAM. It includes a storage means dedicated to the parity bit for the parity check of the output data, and as the storage means,
A memory module to which the SDRAM according to claim 1 or 2 is applied. 4. A data processing device including a main memory and a central processing unit capable of accessing the main memory, wherein the memory module according to claim 3 is applied as the main memory.