JPH0877771A - Synchronous semiconductor storage device and semiconductor storage device - Google Patents

Abstract

PURPOSE: To provide a synchronous semiconductor storage device and a semiconductor storage device which can suppress the increase of chip area due to increase of the number of memory banks. CONSTITUTION: Two banks, #1 and #2, share a global IO line bus GIO, a preamplifier group 9, a write buffer group 15, an input buffer 17, and an output buffer 11. This method can halve the number of the above blocks compared with conventional systems where these blocks are provided for each bank.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor memory device and a semiconductor memory device, and more particularly, to a synchronous semiconductor memory device which takes in an external signal including an external control signal and an address signal in synchronization with an external clock signal, and The present invention relates to a semiconductor memory device having a plurality of banks.

[0002]

2. Description of the Related Art Microprocessors (MPUs) have become faster and faster in recent years. On the other hand, although the dynamic random access memory (hereinafter referred to as DRAM) used as a main memory has been speeded up, its operating speed still cannot keep up with the operating speed of the MPU. For this reason, it is often said that the access time and cycle time of the DRAM become a bottleneck and the performance of the entire system deteriorates.

In order to improve system performance, DR
A method of arranging a high-speed memory called a cache memory composed of a high-speed static random access memory (hereinafter referred to as SRAM) between the AM and the MPU is often used. The frequently used data is stored in the cache memory, and when the data required by the MPU is stored in the cache memory, the high speed cache memory is accessed. MP in cache memory
Access the DRAM only when there is no data requested by U. Since frequently used data is stored in the high speed cache memory, the frequency of accessing the DRAM is significantly reduced, thereby eliminating the influence of the access time and cycle time of the DRAM and improving the system performance.

The method using this cache memory is S
Since RAM is more expensive than DRAM, it is not suitable for relatively inexpensive devices such as personal computers. Therefore, it is required to improve the system performance by using an inexpensive DRAM.

As one answer to this, what is called a synchronous DRAM (synchronous DRAM; hereinafter referred to as SDRAM) capable of accessing several consecutive bits (for example, 8 bits) at high speed in synchronization with a clock signal. Is proposed. Hereinafter, the conventional SDRAM will be described in detail.

[Functional Configuration of SDRAM] FIG. 7 is a block diagram functionally showing a configuration of a main part of a conventional SDRAM. FIG. 7 shows a structure of a functional portion related to 1-bit input / output data of a SDRAM having a x8 bit structure. The array portion related to the data input / output terminal DQi includes a memory array 1a forming bank # 1 and a memory array 1b forming bank # 2.

For memory array 1a of bank # 1, an X decoder group 2a including a plurality of row decoders for decoding address signals X0 to Xj to select a corresponding row of memory array 1a, and a column address signal Y3. ~ Yk decoder group 4a including a plurality of column decoders for decoding Yk to generate a column selection signal for selecting a corresponding column of memory array 1a, and data of a memory cell connected to a selected row of memory array 1a A sense amplifier group 6a for detecting and amplifying is included.

X decoder group 2a includes a row decoder provided corresponding to each word line of memory array 1a.
Corresponding row decoders are brought into the selected state according to address signals X0 to Xj, and word lines provided for the selected row decoders are brought into the selected state.

Y decoder group 4a includes a column decoder provided for each column selection line of memory array 1a. One column select line sets eight pairs of bit lines in a selected state, as will be described later. By the X decoder group 2a and the Y decoder group 4a, 8-bit memory cells are simultaneously selected in the memory array 1a. X decoder group 2a and Y decoder group 4a are shown activated by bank designating signal B1.

The bank # 1 is further provided with an internal data transmission line (global IO) for transmitting the data sensed and amplified by the sense amplifier group 6a and transmitting the write data to the selected memory cell of the memory array 1a.
Line) bus GIO is provided. Global IO line bus GIO includes eight pairs of global IO lines for transmitting / receiving data simultaneously with simultaneously selected 8-bit memory cells.

For data reading, preamplifier group 8a for activating and amplifying data on global IO line bus GIO in bank # 1 in response to preamplifier activation signal φPA1, and data amplified by preamplifier group 8a. A read register 10a for storing the data and an output buffer 12a for sequentially outputting the data stored in the read register 10a are provided.

Preamplifier group 8a and read register 10a each have an 8-bit width structure corresponding to eight pairs of global IO lines. Read register 10a
Responds to the register activation signal φRr1 to latch and sequentially output the data output from the preamplifier group 8a.

The output buffer 12a responds to the output enable signal φOE1 to output the 8-bit data sequentially output from the read register 10a to the data input / output terminal DQ.
to i. In FIG. 7, the data input / output terminal DQ
Data input and data output are shown via i. The data input and data output may be performed via separate terminals.

In order to write data, a 1-bit wide input buffer 18a is activated in response to input buffer activation signal φDB1 and generates internal write data from the input data applied to data input / output terminal DQi.
And a write register 16a which is activated in response to the register activation signal φRw1 and sequentially stores the write data transmitted from the input buffer 18a (according to the wrap address), and is activated in response to the write buffer activation signal φWB1. A write buffer group 14a for amplifying data stored in the write register 16a and transmitting the amplified data to the global IO line pair bus GIO is included.

The write buffer group 14a and the write register 16a each have an 8-bit width.

Similarly, bank # 2 also has memory array 1b,
X decoder group 2b, Y decoder group 4b, sense amplifier group 6b activated in response to sense amplifier activation signal φSA2, preamplifier group 8b activated in response to preamplifier activation signal φPA2, register activation signal φRr
2, a read register 10b activated in response to 2, an output buffer 12b activated in response to an output enable signal φOE2, a write buffer group 14b activated in response to a buffer activation signal φWB2, a register activation It includes a write register 16b activated in response to activation signal φRw2, and an input buffer 18b activated in response to buffer activation signal φDB2.

The structure of bank # 1 and the structure of bank # 2 are the same. By providing read registers 10a and 10b and write registers 16a and 16b, it becomes possible to input / output data to / from one data input / output terminal DQi in synchronization with a high-speed clock signal.

Regarding the control signals for banks # 1 and # 2, only the control signal for one of the banks is generated in accordance with bank designating signals B1 and B2.

The functional block 200 shown in FIG. 7 is provided for each data input / output terminal. SD of × 8 bit configuration
In the case of RAM, eight functional blocks 200 are included.

Banks # 1 and # 2 can be operated almost completely independently of each other by making bank # 1 and bank # 2 substantially the same structure and activating only one of them by bank designating signals B1 and B2. It will be possible.

Data read registers 10a and 1
0b and data write registers 16a and 16b are separately provided and provided for banks # 1 and # 2 respectively, so that data collision does not occur at the time of data read / write operation mode switching and bank switching. , Accurate reading and writing of data can be performed.

As a control system for independently driving the banks # 1 and # 2, a first control signal generation circuit 2
0, a second control signal generating circuit 22 and a clock counter 23 are provided.

The first control signal generating circuit 20 controls the externally applied control signal, that is, the external row address strobe signal ext. / RAS, external column address strobe signal ext. / CAS, external output enable signal ext. / OE, external write enable signal (write enable signal) ext. / WE and mask designating signal WM are, for example, an external clock signal CLK which is a system clock.
The internal control signals φxa, φya, φ
Generate W, φO, φR, and φC.

Second control signal generating circuit 22 includes bank designating signals B1 and B2 and internal control signals φW, φO, φ.
Bank # in response to R and φC and clock signal CLK
Control signals for driving 1 and # 2 independently, that is, sense amplifier activation signals φSA1 and φS
A2, preamplifier activation signals φPA1 and φPA2, write buffer activation signals φWB1 and φWB2, input buffer activation signals φDB1 and φDB2, and output buffer activation signals φOE1 and φOE2 are generated.

The SDRAM further includes, as a peripheral circuit, an external address signal ext.
/ A0 or ext. X address buffer 24 which takes in / Ai and generates internal address signals x0-xj and bank selection signals B1 and B2, and a column selection signal which is activated in response to internal control signal φya and specifies a column selection line. Y3 to Yk and wrap address bits Y0 to Y that specify the first bit line pair (column) during continuous access
2, a Y address buffer 26 for generating bank designating signals B1 and B2, register driving signals φRr1 and φRr2 for controlling wrap addresses WY0 to WY7 and read registers 10a and 10b, and write registers 16a and 16b. A register control circuit 28 for generating control signals φRw1 and φRw2 for driving is included.

Bank designating signals B1 and B2 are applied to register control circuit 28, and a register driving signal is generated only for the selected bank.

[Chip Layout] FIG. 8 shows a conventional SD.
It is a figure which shows the chip layout of RAM. In FIG. 8, as an example, 16M of 2M words × 8 bits configuration is used.
The chip layout of the bit SDRAM is shown.

The SDRAM includes four memory mats MM1 to MM4 each having a storage capacity of 4 Mbits. Each of memory mats MM1 to MM4 includes 16 memory arrays MA1 to MA16 each having a storage capacity of 256 Kbits.

Row decoders RD1 to R are provided on one side of the memory mats MM1 to MM4 along the chip long side direction.
D4 is arranged respectively. Also, the memory mat MM1
Column decoders CD1 to CD4 are arranged on the chip center side of the to MM4 along the short side direction.
Column decoder CD (column decoders CD1 to CD
4 is used generically, a CD is used as a reference), and a column selection line CSL extending across each array of the corresponding memory mats MM (memory mats MM1 to MM4 are generically shown) is arranged at the output of each. To be done. One column selection line CSL simultaneously sets 8 pairs of bit lines to the selected state.

Global I for transmitting internal data
An O line pair GIO is also arranged to cross each array along the long side direction of memory mat MM4.

For each of the memory mats MM1 to MM4, a preamplifier P for amplifying the data read from the selected memory cell is provided on the center side of the chip.
Input / output circuit PW1 including A and a write buffer WB for transmitting write data to the selected memory cell
To PW4 are arranged.

A peripheral circuit PH including a circuit for generating an address signal and a circuit for generating a control signal is arranged in the central portion of the chip.

As shown in FIG. 7, the SDRAM shown in FIG. 8 independently performs a precharge operation and an activation operation (word line selection / sense operation and column selection operation).
It is provided with two banks # 1 and # 2 capable of performing. Bank # 1 has memory mats MM1 and MM2.
Bank # 2 includes memory mats MM3 and MM4.
including. The number of this bank can be changed.

Each of the memory mats MM1 to MM4 includes two array blocks (storage capacity 2 Mbits). One array block is composed of memory arrays MA1 to MA8, and the other array block is composed of memory arrays MA9 to MA16. A maximum of one memory array is selected in one array block.

The number of memory arrays activated simultaneously is four.
8, the memory arrays MA8 and MA16 of the memory mat MM3 and the memory mat MM4 in FIG.
The memory arrays MA8 and MA16 of are activated. That is, in the selected bank,
One memory array is selected from each array block of each memory mat.

The number of column selection lines CSL selected simultaneously is eight.
It is a book. One column selection line CSL selects eight pairs of bit lines. Therefore, 8 × 8 = 64 bit memory cells are simultaneously selected.

The input / output circuit PW corresponds to the corresponding memory mat M.
It is commonly used for each of M memory arrays. The number of preamplifiers PA and write buffers WB included in one input / output circuit PW is 32, respectively.
The total number is 128 (= 32 × 4).

Preamplifier PA and write buffer WB (input / output circuit PW) centrally arranged in the central portion of the chip
Are driven by a control circuit included in the peripheral circuit PH. As a result, the signal lines for controlling the operations of the preamplifier PA and the write buffer WB are shortened, the load on the signal lines is reduced, and high-speed operation can be realized.

Further, by centrally arranging the peripheral circuits PH in the central portion of the chip, data input / output is performed through this central portion of the chip, and the pin arrangement at the time of package mounting is data input / output. The terminals will be arranged in the center of the package. Therefore, the distance between the peripheral circuit PH and the data input / output terminal is shortened, and data can be input / output at high speed.

FIG. 9 is a diagram specifically showing the arrangement of IO lines in the SDRAM shown in FIG. In FIG. 9, two two
M-bit memory arrays MSA1 and MSA2 are shown. The 2M bit memory array MSA2 is a 2M bit array block arranged at a position far from the center of the chip, and the 2M bit memory array MSA1 is a 2M bit array block close to the center of the chip.

2M bit memory arrays MSA1 and M
SA2 is 64 pieces of 32 arranged in 8 rows and 8 columns.
It includes a K-bit memory array MK. The 2M-bit memory array MSA (collectively showing the memory arrays MSA1 and MSA2) has 4 memory cells along the extending direction of the word line WL.
Two array blocks AG1, AG2, AG3 and AG
It is divided into four. A word line shunt region WS is provided between the 32K bit memory arrays MK adjacent to each other in the direction of the word line WL. Normally, in DRAM,
In order to reduce the resistance of the word line, a low resistance metal wiring such as aluminum is arranged in parallel with the word line WL made of polysilicon, and the polysilicon word line and the low resistance metal wiring are electrically connected at a predetermined interval. Connect to. A region for connecting the polysilicon word line and the low resistance metal wiring is called a word line shunt region. In this word line shunt region, it is necessary to connect the polysilicon word line existing under the bit line BL to the low resistance metal wiring layer existing above the bit line. There is no cell.

In one word line shunt region WS, a 2M bit memory array MSA near the center of the chip
In No. 1, four global IO line pairs are arranged.
Of these 4 pairs of global IO lines, 2 pairs of global I lines
The O line further extends to the 2M bit memory array area MSA2 farther from the center of the chip. That is, two global IO line pairs GIO are arranged in the word line shunt region in the 2M-bit memory array region MSA2 farther from the center of the chip. Two global IO
The line pairs are utilized by one 2M bit memory array MSA.

A local IO line pair LIO for connecting the global IO line pair IGO and the selected memory array
Is provided. Array group AG1, AG2, AG3
And AG4, a local IO line pair LIO is provided for each array block MK.

Two local IO line pairs LI arranged on one side of one 32K-bit memory array MK
Two local IO line pairs LIO connected to O and the other side
And a total of 4 pairs of local IO lines are arranged. The local IO line pair LIO is shared by the 32K-bit memory arrays MK in the same array group that are adjacent to each other in the extending direction of the word line WL, and the 32K-bit adjacent to each other in the extending direction of the bit line BL. It is also shared by the memory array MK.

The memory array MK has an interleaved shared sense amplifier structure, as will be described later. A sense amplifier is arranged in a region between two 32K bit memory arrays MK adjacent to each other in the direction in which bit line BL extends. A block selection switch BS is arranged to connect global IO line pair GIO and local IO line pair LIO. Block selection switch BS
Are arranged at the intersections of the word line shunt regions WS and the sense amplifier columns.

One column selection line CSL for transmitting a column selection signal from the column decoder is selected in each of the array groups AG1 to AG4. One column selection line C
SL is a 2M bit memory array M far from the center of the chip
In SA2, four bit line pairs BLP are selected and connected to the corresponding local IO line pair LIO, and in 2M bit memory array MSA1 near the center of the chip, four bit line pairs BLP are selected and the corresponding local IO line pair is selected. LI
Connect to O.

That is, one column selection line CSL is used for 8
One bit line pair BLP is selected and local IO
It is connected to eight global IO line pairs GIO via the line pair LIO. Since two memory mats are selected and 8 × 4 = 32 bit line pairs BLP are selected in one memory mat MM, a total of 64 bit line pairs B are selected.
Since LP is selected, it is possible to simultaneously access a total of 64 bits of memory cells.

[Arrangement of Memory Cell] FIG.
It is a figure which shows the structure of the part relevant to a 2K bit memory array. In FIG. 10, a 32K-bit memory array M
K2 is a word line WL to which a row selection signal from the row decoder is transmitted, a bit line pair BLP arranged in a direction crossing the word line WL, and an intersection of the word line WL and the bit line pair BLP. It includes a dynamic memory cell MC arranged correspondingly.

Memory cell MC includes a transistor for access and a capacitor for information storage. The bit line pair BLP is a bit line BL through which complementary signals are transmitted.
And / BL included. In FIG. 10, the bit line BL
A state is shown in which memory cells MC are arranged corresponding to the intersections between the word lines WL and the word lines WL.

Array select gates SAG1 and SAG2 are arranged on both sides of memory array MK. Array selection gate SAG1 and array selection gate SAG2 are alternately arranged for bit line pair BLP. Array select gate SAG1 is rendered conductive in response to array select signal φA1, and array select gate SAG2 is rendered conductive in response to array select signal φA2.

The bit line pair BLP is connected to the sense amplifier SA via array selection gates SAG1 and SAG2, respectively.
1 and SA2. That is, the sense amplifier SA1 includes the word line WL on one side of the memory array MK2.
The sense amplifier SA2 is arranged in parallel with the word line WL on the other side of the memory array MK2.
The sense amplifiers SA1 and SA2 are the memory array MK.
The two bit line pairs BLP are alternately arranged on both sides. The sense amplifier SA1 is shared by the memory array MK1 and the memory array MK2. Sense amplifier SA2
Are shared by the memory array MK2 and the memory array MK3.

Local IO line pairs LIO1 and LIO2 are arranged parallel to the column of sense amplifiers SA1. In parallel with the column of the sense amplifier SA2, the local IO line pair LIO
3 and LIO4 are arranged. In FIG. 10, 2
An arrangement is shown in which one local IO line pair is provided on one side of the sense amplifier SA. The local IO line pairs may be arranged on both sides of the sense amplifier SA.

Data sensed and amplified by the sense amplifier SA1 is sent to the sense amplifier SA1 as a local IO.
A column select gate CSG1 for transmitting to the line pair LIO1 and LIO2 is provided. Similarly, the sense amplifier SA
For 2, a column select gate CSG2 for transmitting the data sensed and amplified by the sense amplifier SA2 to the local IO line pair LIO3 and LIO4 is provided.

The column selection line CSL receiving the signal from the column decoder simultaneously turns on the two column selection gates CSG1 and CSG2. This makes 4
One bit line pair BLP is a local IO line pair LIO1, L
Connected to IO2, LIO3 and LIO4 simultaneously.
The data detected and amplified by the sense amplifier SA1 is transmitted to the local IO line pair LIO1 and LIO2. The data detected and amplified by the sense amplifier SA2 is the local I
It is transmitted to O line pair LIO3 and LIO4.

Local IO line pair LIO and global IO
A block selection switch BS which is rendered conductive in response to a block selection signal φB is provided between line pair GIO. FIG.
At 0, the block selection switch BS1 for connecting the local IO line pair LIO1 to the global IO line pair GIO1 and the local IO line pair LIO2 are connected to the global I line.
Block selection switch BS2 connected to O line pair GIO2
And are indicated.

Local IO line pair LIO3 and LIO4
Is connected to two adjacent global IO line pairs GIO via block selection switches BS as shown in FIG. 9 (not shown in FIG. 10).

Next, the operation will be briefly described. When the selected word line WL is included in memory array MK2, array select signals φA1 and φA2 are activated, and bit line pair BLP included in memory array MK2 is connected to sense amplifiers SA1 and SA2. Array select gates SAG0 and SAG3 provided for memory arrays MK1 and MK3 are rendered non-conductive.
The memory arrays MK1 and MK3 maintain the precharged state.

In memory array MK2, after the memory cell data appears on each bit line pair BLP, sense amplifiers SA1 and SA2 are activated to detect and amplify the memory cell data.

Then, when the signal on column select line CSL rises to the active state of "H", column select gates CSG1 and CSG2 are rendered conductive, and the data sensed and amplified by sense amplifiers SA1 and SA2 are transferred to the local IO line pair. It is transmitted to LIO1 to LIO4.

Subsequently or simultaneously, the block selection signal φB
Becomes "H" in the active state, and the local IO line pair LIO1
To LIO4 are global IO line pairs GIO1 to G
Connected to IO4. At the time of data reading, the data of the global IO line pair is amplified through the preamplifier PA and stored in the reading register, and then sequentially output. When writing data, write buffer W
The write data given from B is the global IO line pair G
The data is transmitted to the selected bit line pair BLP via IO and the local IO line pair LIO, and data writing to the memory cell is executed.

The block selection signal φB is the selected word line W.
Only the memory array MK2 to which L belongs is activated. The same applies to array selection signals φA1 and φA2. Block selection signal φB and array selection signal φA
1 and φA2 can be generated using a predetermined number of bits (for example, 4 bits) of the row address signal.

[Designation of Operation Mode] The operation mode of the SDRAM is determined by the state of the external control signal at the rising edge of the clock signal CLK. The external control signal is given only in the cycle that specifies the operation mode in the form of pulse. All control signals, address signals and write data are all taken in at the rising edge of clock signal CLK. The operation mode designated inside the device is discriminated according to the combination of the states of the external control signals at the rising edge of clock signal CLK, and the operation control corresponding to the designated operation mode is executed according to the discrimination result. Next, the correspondence between the external control signal and the operation mode will be described.

(A) / RAS = "L" and / CAS =
/ WE = “H” This state is called an active command, and row address acquisition is designated and array activation is designated. That is, the row address is fetched and the bank address is fetched together, and the operation related to the row selection is executed in the selected bank.

(B) / CAS = "L" and / RAS =
/ WE = “H” This state is referred to as a read command, in which column address acquisition is designated and a data read operation mode is designated.
In this operation mode, the bank address is also taken in with the column address, the read data register corresponding to the selected bank is selected, and the data transfer operation of the selected memory cell to the read data register is selected. Executed in a bank.

(C) / CAS = / WE = “L” and /
RAS = “H” This combination of the states of the external control signals is called a write command, and specifies the column address fetch and data write operations. In this operation mode, the write register is activated in the selected bank, and the applied data is written to the write register and the selected memory cell.

(D) / RAS = / WE = “L” and /
CAS = “H” This combination of the states of the external control signals is called a precharge command, and the array is brought into a precharge state.

There are various other commands such as an auto refresh command, but the description thereof is omitted.

[Specific Operation Sequence] [Data Read] FIG. 11 is a timing chart showing the states of external signals during normal data read (Ramdom Read Cycle) of the SDRAM. The data read operation will be briefly described below with reference to FIG.

In cycle 1, clock signal CLK
At the rising edge of, the signal / RAS is set to "L" and the signals / CAS and / WE are both set to "H",
An "active command" is given. At this time, the row address signal bit Add. Is taken in as a row address signal Xa and an internal address is generated. At this time, the bank address signal BA is also taken in at the same time, and the bank designation signal B1 or B2 is generated. In the following explanation,
When the bank address signal BA is "0", the bank # 1
Is specified and the bank address signal BA is "1",
Bank # 2 shall be specified.

In bank # 1, row decoder operation and array activation are executed. In clock cycle 4, a signal / is generated at the rising edge of clock signal CLK.
RAS and / WE are set to "H", signal / CS is set to "L", and "read command" is applied.
Data read is designated, and at the rising edge of clock signal CLK in cycle 3, address signal bit Add. Are taken in as a column address signal Yb.
At this time, bank address BA is given again. The bank address BA is "0" indicating the bank # 1. Internally, the row and column selecting operation is executed for bank # 1 in accordance with row address signal Xa and column address signal Yb, and the data of the selected memory cell is stored in the read data register (read register). Data is read in cycle 7.

From cycle 7 to cycle 14,
Eight pieces of data stored in the read register are sequentially read in synchronization with the rising edge of the clock signal CLK. Continuous 8-bit data is shown as b0 to b7. The data input / output terminals are DQ0 to DQ7 and 8 bits, and one data b is byte data.

In parallel with data reading, signal / RA is generated at the rising edge of clock signal CLK in cycle 7.
S and / WE are set to "L" and signal / CAS is set to "H". At this time, the bank address signal BA is also set to "0". Bank # 1
Is designated, and the array of bank # 1 is precharged.

Bank # 1 which has entered the precharge state,
It can be activated again after a predetermined RAS precharge period (2 to 3 clock cycles) has elapsed.

In cycle 11, the clock signal CL
At the rising edge of K, signal / RAS is "L", signal / RAS
Both CAS and / WE become "H". The bank address signal BA is "0" again. Bank # 1 is activated again, and the row selecting operation is started in accordance with the row address signal Xc applied at that time.

Clock signal CLK in cycle 14
Signal / CAS is "L" at the rising edge of, signal / RA
Both S and / WE are set to "H". The column address signal Yd and the bank address signal BA are fetched and a data read operation is designated.

In bank # 1, the row and column selecting operation is executed according to the row address Xc and the column address Yd, and the data in the selected memory cell is transferred again to the read data register. The output of data to the outside of the device is
It is executed after counting 6 clocks from the start of the memory cycle when the signal / RAS enters "L".

From cycle 17, at the rising edge of clock signal CLK, eight pieces of data d0 to d7 selected by addresses Xc and Yd are sequentially clocked by clock signal CL.
It is read in response to the rise of K. At the same time in cycle 17, the signals / RAS and / WE are set to "0",
The bank address signal BA is set to "0". This causes bank # 1 to enter the precharged state again.

Further, FIG. 12 shows that when data is alternately and continuously read from two banks # 1 and # 2 (Dual Ban
It is a timing chart figure which shows the state of the external signal of (k Interleaved Read Cycle). Cycle 0 to cycle 8
Up to the above, the read operation is the same as that shown in FIG.

Next, in cycle 9, the signal / RAS
Is set to "L", signals / CAS and / WE are set to "H", and bank address signal BA is set to "1". In response to the active command, bank # 2 is selected, and the address signal bit Add. Are taken in as the row address Xc. After that, the row selecting operation according to the row address Xc is executed in the bank # 2.

Clock signal CLK in cycle 12
At the rising edge of, signals / RAS and / WE are set to "H" and signal / CAS is set to "L".
As a result, a read command for bank # 2 is given and a data read operation is designated. At this time, at the same time, the column address Yd is taken in together with the bank address signal BA.

After data b7 is read from bank # 1, data d0 from bank # 2 is read at the rising edge of clock signal CLK in the next clock cycle 15. At this time, again, the signal / RAS is "L", the signal / RAS
WE is set to "L" and signal / CAS is set to "H",
Bank address signal BA is "1", and precharge of bank # 2 is designated. Data read from bank # 2 is output from the data read data register. At this time, precharge is executed in bank # 2.

In cycle 17, the signal / RAS is restored again.
Is set to "L", signals / CAS and / WE are set to "H", and bank address signal BA is set to "0" to reactivate bank # 1.

In cycle 20, column address Yf is fetched into bank # 1. [Data Writing] FIG. 13 is a timing chart showing the state of external signals during data writing (Random Write Cycle) of the SDRAM. The write command designating the write operation is the rising edge of the clock signal CLK, and sets the signal / RAS to "H", the signals / CAS and / WE.
Are both set to "L". FIG.
In the operation sequence shown in (1), the data write operation for bank # 1 is designated first.

When this write command is given, a signal /
At the same time when CAS and / WE are set to "L", writing of data to the write register, that is, fetching of internal data is executed. That is, when writing data,
The data acquisition to the input buffer is executed at the same time as the write instruction. At this time, the state of the write register may not yet be completely reset. It suffices that the state of the register is determined and the data b0 can be written by the next clock cycle.

The operation sequence at the time of writing data shown in FIG. 13 is the same as the data read operation shown in FIG. 11 except for the above points, and detailed description thereof will not be given. A bank is selected according to the bank address signal BA, and writing of data to the selected bank (writing to the memory cell via the write register) is executed.

As described above, the SDRAM has the signal / RAS, the signal / CA at the rising edge of the clock signal CLK.
Since it operates by fetching S, address, data, etc., compared to a conventional DRAM which fetches and operates address, data, etc. in synchronization with signal / RAS, signal / CAS, etc.
It is not necessary to secure a data input / output margin due to a skew (timing shift) of an address or the like, which has an advantage that the cycle time can be shortened. Further, depending on the system, there are cases in which several consecutive bits are accessed frequently, and the average access time can be made comparable to that of SRAM by increasing the continuous access time.

In the conventional DRAM, the precharge must be performed before the access, which causes the cycle time to be almost twice as long as the access time. On the other hand, in SDRAM,
If the bank # 2 is precharged while the bank # 1 is being accessed, the bank # 2 can be accessed immediately after the access to the bank # 1 is completed. That is, by alternately accessing / precharging banks # 1 and # 2, the loss time due to precharging can be eliminated. This is traditionally
It can be said that the method of interleaving, which was performed outside the DRAM, is taken inside the DRAM.

[0088]

[Problems to be Solved by the Invention] However, the conventional SDR
In the AM, as shown in FIG. 8, the two memory mats MM1 and MM2 on one side are simply bank # 1 and the two memory mats MM3 and MM4 on the other side are bank # 2. Global IO line bus GIO and preamplifier group 8 for # 1 and # 2 respectively
a, 8b, write buffer groups 14a, 14b, etc. are required, which causes an increase in chip area. Further, the chip area increases as the number of internal banks increases.

Therefore, a main object of the present invention is to provide a synchronous semiconductor memory device and a semiconductor memory device capable of suppressing an increase in chip area caused by division into a plurality of banks.

[0090]

A first synchronous semiconductor memory device of the present invention is a synchronous semiconductor memory device for receiving an external signal including an external control signal and an address signal in synchronization with an external clock signal. A plurality of memory banks having a memory cell array having a plurality of memory cells and a memory cell selection circuit for selecting one of the memory cells from the memory cell array, a data read circuit commonly provided to the plurality of memory banks, A plurality of data output circuits provided corresponding to each of the plurality of memory banks, and a corresponding data output circuit of the data read circuit and the plurality of data output circuits according to a bank address signal included in the address signal. It is characterized in that it is provided with a bank control means for coupling with.

The second synchronous semiconductor memory device of the present invention is a synchronous semiconductor memory device for receiving an external signal including an external control signal and an address signal in synchronization with an external clock signal. A plurality of memory banks each having a memory cell array having memory cells and a memory cell selection circuit for selecting one of the memory cells from the memory cell array; a data write circuit commonly provided to the plurality of memory banks; A plurality of data input circuits provided corresponding to each of the memory banks, and a data write circuit and a corresponding data input circuit of the plurality of data input circuits according to a bank address signal included in the address signal. It is characterized in that it is provided with a bank control means for connection.

A third synchronous semiconductor memory device of the present invention is a synchronous semiconductor memory device which takes in an external signal including an external control signal and an address signal in synchronization with an external clock signal. A plurality of memory banks having a memory cell array having a memory cell selection circuit and a memory cell selection circuit for selecting one of the memory cells from the memory cell array, a data read circuit commonly provided in the plurality of memory banks, and a plurality of memory banks A plurality of data output circuits provided corresponding to each, a data writing circuit commonly provided to the plurality of memory banks, a plurality of data input circuits provided corresponding to each of the plurality of memory banks, and the address. According to a bank address signal included in the signal, the data read circuit and the data read circuit A bank control means for coupling a corresponding data output circuit of the plurality of data output circuits and coupling the data write circuit and a corresponding data input circuit of the plurality of data input circuits at the time of writing data. It is characterized by that.

Further, the semiconductor memory device of the present invention is a semiconductor memory device having a plurality of banks, the memory cell array having a plurality of memory cells arranged in a matrix,
A plurality of word lines arranged corresponding to each row, each including a plurality of sub-word lines grouped corresponding to the plurality of banks, and connected to the memory cells of the corresponding row, and a row address signal. A word line selection signal generating means for generating a word line selection signal for selecting a word line of a corresponding row of the memory cell array according to the above, and a selected word in response to a bank designation signal and the word line selection signal. It is characterized in that it is provided with a word line selecting means for bringing a corresponding sub-word line among the lines into a selected state.

[0094]

In the first synchronous semiconductor memory device of the present invention, since the data read circuit is commonly provided for a plurality of memory banks, the conventional data read circuit is provided for each memory bank. In comparison, it is possible to suppress an increase in chip area due to an increase in the number of memory banks.

Further, in the second synchronous semiconductor memory device of the present invention, since the data write circuit is commonly provided for a plurality of memory banks, the data write circuit is provided for each memory bank. It is possible to suppress an increase in chip area due to an increase in the number of memory banks, as compared with the conventional case.

Further, in the third synchronous semiconductor memory device of the present invention, since the data read circuit and the data write circuit are commonly provided for a plurality of memory banks, data read for each memory bank is performed. It is possible to suppress an increase in chip area due to an increase in the number of memory banks, as compared with the conventional case where a circuit and a data write circuit are provided.

Further, in the semiconductor memory device of the present invention, the memory cell array is divided into memory banks in units of sub-word lines, and when the word line is selected and the bank is designated, the sub-word line is brought into a selected state. Therefore, the data read circuit and the like can be commonly provided for a plurality of memory banks. Therefore, it is possible to suppress an increase in chip area due to an increase in the number of memory banks.

[0098]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an SDRAM according to an embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

Referring to FIG. 1, the SDRAM is different from the SDRAM of FIG. 7 in that it has global IO line bus GI.
O, preamplifier group 9, write buffer group 15, input buffer 17 and output buffer 11 are two banks # 1,
This is a point provided in common with # 2.

The read registers 10a and 10b and the write registers 16a and 16b are provided corresponding to the banks # 1 and # 2 as in the conventional case. Further, as shown in FIG. 2, a MOS transistor T for distributing the output of the preamplifier 9a to the two read registers 10a and 10b.
r1 and Tr2 and two read registers 10a and 10
MOS transistors Tr3 and Tr4 for selectively passing the output of b to the output buffer 11 are provided.
Each of the MOS transistors Tr1 to Tr4 has a signal φ.
It is controlled by PA1, φPA2, φRr1, and φRr2. Further, the MOS transistors Tr5 and Tr6 for distributing the output of the input buffer 17 to the two write registers 16a and 16b, and the two write registers 1
MOS transistors Tr7 and Tr for selectively passing the outputs of 6a and 16b to the write backup 15a.
And 8 are provided. MOS transistors Tr5 to Tr8
Are signals φRw1, φRw2, φWB1, and φW, respectively.
It is controlled by B2.

The read register and the write register are provided for each bank in order to enable continuous reading and writing in the interleave cycle shown in FIG. That is, this is so that the data can be prefetched from the other bank while the data is continuously read from the one bank.

FIG. 3 is a diagram showing a chip layout of the SDRAM shown in FIG. Referring to FIG. 3, this SD
In the RAM, one of the memory mats MM1 to MM4 is 2M
Bit memory array MSA1 (that is, 256K bit memory arrays MA1 to MA8) constitutes bank # 1,
The other 2M-bit memory array MSA2 (that is, 256K-bit memory arrays MA9 to MA16) of each memory mat MM1 to MM4 constitutes bank # 2.

In the selected bank, one 2 from each 2M bit memory array MSA of each memory mat MM.
The 56K-bit memory array MA is selected similarly to the conventional SDRAM. However, since the banks # 1 and # 2 are configured as described above, the memory mats
256K bit memory array MA (MA1 in the figure
Only 6) is selected. Therefore, each memory mat M
The number of global IO lines GIO, preamplifiers PA, and write buffers WB can be reduced by half compared to the conventional case in which two 256K-bit memory arrays MA (MA8 and MA16 in FIG. 8) are simultaneously selected from M.

That is, as shown in FIG. 4, the global I for the memory array MSA1 provided in FIG. 9 is used.
The O line pair GIO can be eliminated, and the number of global IO line pairs GIO can be reduced from 32 pairs to 16 pairs. Also, the number of preamplifiers PA and write buffers WB provided corresponding to each global IO line pair GIO can be reduced from 32 to 16. Therefore, the chip area can be reduced.

FIG. 5 shows an SDR according to another embodiment of the present invention.
FIG. 6 is a block diagram showing the configuration of the AM, and FIG. 6 is a diagram specifically showing the arrangement of the IO lines.

Referring to FIGS. 5 and 6, this SDRA
A so-called divided word line system is applied to M, and two array blocks AG of each memory mat MM are applied.
1, 1 and AG3 form a bank # 1, and the other two array blocks AG2 and AG4 form a bank # 2.

Explaining in detail, this SDRAM has 4
Main word lines 33, 34, ... Provided commonly to one array block AG1 to AG4, and each main word line 3
Main row decoders 31, 32, ... Provided corresponding to 3, 34 ,. Main row decoder 31, 3
.. respond to internal address signals x0 to xj to raise corresponding main word lines 33, 34 ,.

Array block AG1 includes sub-word lines 33.34 provided corresponding to main word lines 33.
, 34.1, ..., and sub word lines 33.1, 34.
Sub row decoders 31.1 provided corresponding to 1 ...
32.1, ... And. Also, the array block AG1
Are a plurality of bit line pairs BLP arranged to intersect with sub word lines 33.1, 34.1, ...
, And memory cells MC arranged at each intersection of the bit line pair BLP. Further, array block AG1 includes a sense amplifier 35.1 for amplifying the potential difference between bit line pair BLP, and a block selection line 36.1 to which bank designating signal B1 is input.

Sub row decoders 31.1, 32.1, ...
Responds to the corresponding main word lines 33, 34, ... Raising to the selection level and the group selection line 36.1 to the selection level.
3. 1, 34.1, ... are raised to the selection level. Sense amplifier 35.1 operates in response to block select line 36.1 being raised to the select level. Since the other array blocks AG2 to AG4 are similar, the description is omitted.

In the selected bank, one 2 from each 2M bit memory array MSA of each memory mat MM.
The 56K-bit memory array MA is selected similarly to the conventional SDRAM. However, since banks # 1 and # 2 are configured as described above, only four of the eight 32K-bit memory arrays MK of each 256K-bit memory array MA are activated. FIG. 6 shows a state in which two memory arrays MA8 and MA16 of each memory mat MM are selected and only the memory array MK belonging to array blocks AG2 and AG4 among the memory arrays MA8 and MA16 is activated.

Therefore, two memory arrays MA are selected from each memory mat MM and two memory arrays M are selected.
The number of global IOs to GIOs, preamplifiers PA, and write buffers WB can be reduced by half compared to the conventional case where all memory arrays MK of A are activated.

That is, as shown in FIG. 6, the global IO line pair G dedicated to the 2M-bit memory array MSA1 of the array blocks AG1 and AG3 provided in FIG.
IO and the global IO line pair GIO dedicated to the 2M-bit memory array MSA2 of the array blocks AG2, AG4 can be eliminated, and the number of global IO line pairs GIO can be reduced from 32 pairs to 16 pairs. However, the local IO line pair LIO of array block AG1 and the local IO line pair LIO of array lock AG2 are connected to each other. The local IO line pair LIO of the array block AG3 and the local IO line pair L of the array block AG4 are also included.
IO is connected to each other. Global IO like this
Since the number of line pairs GIO can be reduced to half, the number of preamplifiers PA and write buffers WB provided corresponding to each global IO line pair GIO can also be reduced to half. Therefore, the chip area can be reduced.

[0113]

As described above, in the first synchronous semiconductor memory device of the present invention, since the data read circuit is commonly provided for a plurality of memory banks, data read is performed for each memory bank. It is possible to suppress an increase in chip area due to an increase in the number of memory banks, as compared with the conventional case in which a circuit is provided.

Further, in the second synchronous semiconductor memory device of the present invention, since the data write circuit is commonly provided for a plurality of memory banks, the data write circuit is provided for each memory bank. It is possible to suppress an increase in chip area due to an increase in the number of memory banks, as compared with the conventional case.

Further, in the third synchronous semiconductor memory device of the present invention, since the data read circuit and the data write circuit are commonly provided for a plurality of memory banks, the data read for each memory bank is performed. It is possible to suppress an increase in chip area due to an increase in the number of memory banks, as compared with the conventional case where a circuit and a data write circuit are provided.

Further, in the semiconductor memory device of the present invention, since the memory cell array is divided into memory banks in units of sub-word lines, a data read circuit or the like can be provided commonly to a plurality of memory banks. It is possible to suppress an increase in chip area due to an increase in the number of banks.

[Brief description of drawings]

FIG. 1 is a block diagram functionally showing an overall structure of an SDRAM according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the SDRAM shown in FIG.

FIG. 3 is a diagram showing a chip layout of the SDRAM shown in FIG.

FIG. 4 is a diagram showing a layout of a memory array of the SDRAM shown in FIG.

FIG. 5 is a partially omitted circuit block diagram showing a structure of an SDRAM according to another embodiment of the present invention.

6 is a diagram showing a layout of a memory array of the SDRAM shown in FIG.

FIG. 7 is a block diagram functionally showing an overall configuration of a conventional SDRAM.

FIG. 8 is a diagram showing a chip layout of the SDRAM shown in FIG.

9 is a diagram showing a layout of a memory array of the SDRAM shown in FIG.

10 is a diagram showing a structure of an array of the SDRAM shown in FIG.

11 is a timing chart showing an example of an operation sequence of the SDRAM shown in FIG.

12 is a timing chart showing another example of the operation sequence of the SDRAM shown in FIG.

FIG. 13 is a timing chart showing still another example of the operation sequence of the SDRAM shown in FIG.

[Explanation of symbols]

1a, 1b memory array, 2a, 2b X decoder group, 4a, 4b Y decoder group, 6a, 6b sense amplifier group, 9 preamplifier group, 10a, 10b read register, 11 output buffer, 15 write buffer group, 16a, 16b Write registers, 17 input buffers, 31 and 32 main row decoders 31.1 to
32.4 sub row decoder, 33, 34 main word line, 33.1 to 34.4 sub word line, WL word line, BLP bit line pair, CSL column select line, GIO global IO line pair, LIO local IO line pair, BS
Block selection switch, Tr1-Tr8 N channel M
OS transistor, PA preamplifier, WB write buffer, PW input / output circuit, MK 32K bit memory array, MA 256K bit memory array, MSA 2
M-bit memory array, MM 4M memory mat, AG
1-AG4 array block.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoya Watanabe 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation ULS Development Research Center

Claims (4)

[Claims] 1. A synchronous semiconductor memory device for fetching an external signal including an external control signal and an address signal in synchronization with an external clock signal, each comprising: a memory cell array having a plurality of memory cells; A plurality of memory banks having a memory cell selection circuit for selecting one of the memory cells, a data read circuit provided commonly to the plurality of memory banks, and a plurality of data outputs provided corresponding to each of the plurality of memory banks. A synchronous semiconductor memory device comprising: a circuit; and bank control means for coupling the data read circuit and a corresponding data output circuit of the plurality of data output circuits according to a bank address signal included in the address signal. 2. A synchronous semiconductor memory device for fetching an external signal including an external control signal and an address signal in synchronization with an external clock signal, each comprising: a memory cell array having a plurality of memory cells; A plurality of memory banks having a memory cell selection circuit for selecting one of the memory cells, a data write circuit commonly provided to the plurality of memory banks, and a plurality of data provided corresponding to each of the plurality of memory banks. A synchronous semiconductor memory device including an input circuit and bank control means for coupling the data write circuit and a corresponding data input circuit of the plurality of data input circuits according to a bank address signal included in the address signal. . 3. A synchronous semiconductor memory device for fetching an external signal including an external control signal and an address signal in synchronization with an external clock signal, each comprising: a memory cell array having a plurality of memory cells; A plurality of memory banks having a memory cell selection circuit for selecting one of the memory cells, a data read circuit provided commonly to the plurality of memory banks, and a plurality of data outputs provided corresponding to each of the plurality of memory banks. A circuit, a data write circuit provided commonly to the plurality of memory banks, a plurality of data input circuits provided corresponding to each of the plurality of memory banks, and a bank address signal included in the address signal, at the time of data reading. The corresponding one of the data read circuit and the plurality of data output circuits By combining the over data output circuit includes a bank control means for coupling the data input circuit of a corresponding one of said data write circuit and said plurality of data input circuit during data writing, the synchronous semiconductor memory device. 4. A semiconductor memory device having a plurality of banks, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns, arranged corresponding to each row, each corresponding to the plurality of banks. A plurality of word lines each including a plurality of sub-word lines to be grouped, each word line being connected to a memory cell in a corresponding row, and a word line for selecting a word line in a corresponding row of the memory cell array according to a row address signal Word line selection signal generating means for generating a selection signal, and word line selection means for setting a corresponding sub-word line of the selected word lines in a selected state in response to the bank designation signal and the word line selection signal. A semiconductor memory device comprising.