JP2002318686A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor capable of enhancing execution speed by shortening read time of instruction data. SOLUTION: In a control part 2 of the processor 1, it is constituted so that an instruction decoder 21 issues an instruction to a data path part 3 by providing an instruction definition storage memory 24 and using definition information stored in the instruction definition storage memory 24 when an instruction issuing device 23 judges that an instruction read from an external memory 6 is a defined instruction. Thus, data quantity of the instruction to be read is reduced and the read time is shortened by defining a plurality of instructions to be frequently used in the instruction definition storage memory 24 by short data quantity. In addition, the instructions becomes executable by other processors with different instruction systems without changing a program main body and diversity of the program is enhanced by replacing the definition information of the instruction definition storage memory 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a processor.
In particular, the present invention relates to a processor capable of realizing an improvement in execution speed by dynamically changing an instruction system and reducing a data amount of an instruction to be read.

[0002]

2. Description of the Related Art At present, microprocessors are used not only in computers and portable terminals but also in all electronic devices. Such a microprocessor has a unique instruction system, and a program operates according to the read instruction by being created in accordance with the instruction content. The instructions that the microprocessor has are determined when the microprocessor is created,
Fixed and cannot usually be changed.

[0003] Recently, a microprocessor capable of reading a special program at the time of startup and internally converting an instruction into an instruction peculiar to the processor has been put into practical use. Since the change of the instruction is realized by reading a special program at the time of startup, the change of the instruction is limited only at the time of startup.

[0004]

In a conventional processor, the instruction system is constant regardless of the program. Therefore, when a program having completely different properties is used by switching, a processor having a certain instruction system requires one or a small number of instructions. Even if operations can be performed, processors with different instruction systems may require many instructions,
In the latter case, since the data amount of the instruction to be read becomes large, there is a problem that it takes time to read the instruction and the execution speed does not increase.

The present invention has been made in view of the above circumstances, and dynamically changes an instruction system by a program, thereby simplifying the instructions of the program, shortening the time for reading instruction data, and reducing the execution speed. While improving
An object of the present invention is to provide a processor capable of improving the degree of diversion of a program between processors having different architectures.

[0006]

According to the present invention, there is provided a processor having a control unit for acquiring an instruction from an external memory and issuing the instruction to a data path unit for performing an operation. Storage means for storing definition information defined by expressing the instruction in different data, determination means for determining whether or not the obtained instruction is a defined instruction, and determining that the obtained instruction is a defined instruction. And a command issuing unit for issuing an instruction to the data path unit using the data of the definition information stored in the storage unit in the event that the processor is provided.

According to the above arrangement, the storage means stores definition information in which a plurality of instructions are defined as one instruction, and when the acquired instruction is a defined instruction, the stored definition information is stored in the storage means. An instruction is issued using data. The definition information stored in the storage unit can freely change the instruction system unique to the processor according to the characteristics of the program by redefining frequently used instructions with a short data amount. Thus, by using the redefined instruction having a short data amount, the data amount of the entire program can be reduced, and the acquisition time of the instruction can be shortened.
In addition, by defining a plurality of instructions as one instruction, the disturbance of the pipeline is reduced, and the execution speed of the program can be improved. Further, by using only the instruction defined by the instruction, it is possible to eliminate the dependence of the program on the processor.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing the configuration of the processor of the present invention.

The processor 1 includes a control unit 2 for acquiring an instruction and issuing an instruction, a data path unit 3 for executing an operation according to the instruction, and an external bus for reading a program or the like from the outside and outputting the operation result. Interface section 4
It is composed of Outside the processor 1, a memory 6 is connected from the external bus interface unit 4 via an address bus 51 and a data bus 52.

The control unit 2 comprises an instruction decoder 21, an address generator 22, and an instruction issuer 23. In the processor of the present invention, one or more existing instructions,
That is, an instruction definition storage memory 24 is provided for storing instruction definition information in which instructions unique to the processor are represented by different data and defined.

The instruction decoder 21 decodes an instruction and generates an internal control signal for executing the instruction. The address generator 22 generates an execution address of an instruction. The instruction issuer 23 determines whether the acquired instruction is a defined instruction. If the instruction is a defined instruction, the instruction issuer 23 refers to the instruction definition storage memory 24 and issues the defined instruction to the instruction decoder 21. I do. If not, the instruction is issued as it is.

The data path unit 3 comprises an arithmetic unit 31 and a general-purpose register 32. The arithmetic unit 31 performs various operations according to the instruction from the instruction decoder 21, and the general-purpose register 32 stores various data during the operation and the operation result.

The external bus interface unit 4 converts an internal signal into an external bus signal,
To read and write data. The external memory 6 stores an instruction 61 and data 62, and supplies an instruction 61 or data 62 of an address requested by the external bus interface unit 4 via the address bus 51 via the data bus 52.

The flow of instruction execution in the processor 1 having the above configuration will be described with reference to flowcharts.
FIG. 2 is a flowchart showing the flow of instruction execution of the processor of the present invention.

First, the processor 1 includes an address generator 2
2 generates an address for acquiring an instruction (step S1). The address generated by the address generator 22 is output to the external bus interface unit 4 by the instruction issuer 23, and accesses the memory 6 based on the address to read a predetermined amount of data including the specified address from the memory 6 (step S2). .

Next, the instruction issuer 23 determines whether the instruction in the read data is an instruction definition execution instruction for executing the instruction definition (step S3). The definition information is stored in the instruction definition storage memory 24 (step S4), and if it is not an instruction definition execution instruction, step S4 is passed.

Next, the instruction issuer 23 determines whether the instruction in the read data is a defined instruction (step S5). Here, if the read instruction is not a defined instruction, the instruction issuer 23 passes the read instruction to the instruction decoder 21 as it is. The instruction decoder 21 decodes the received instruction, generates an internal control signal (Step S6), and passes the internal control signal to the arithmetic unit 31 of the data path unit 3. Arithmetic unit 31 of data path unit 3
Executes the instruction based on the internal control signal (step S7), writes the executed operation result back to the general-purpose register 32 (step S8), and completes a series of operations. By the way, in the above operation, steps S1, S2, S6 ~
S8 is the same operation as that performed by the conventional processor.

If it is determined in step S5 that the read instruction is a defined instruction, the instruction issuer 23
Accesses the instruction definition storage memory 24, reads the defined instruction therefrom (step S9), and executes an operation using the defined instruction. That is, the defined instruction is passed to the instruction decoder 21 by the instruction issuer 23, where it is decoded (step S1).
0), the arithmetic unit 31 of the data path unit 3 executes the decoded instruction (step S11), and writes the executed operation result back to the general-purpose register 32 (step S1).
2). Then, in the case of the defined instruction, since a plurality of instructions may be defined, it is determined whether or not the instruction definition is completed (step S13). If not, the process returns to step S9. The processes of steps S9 to S12 are repeated, and if completed, the process is completed here.

Next, the instructions of the processor 1 and the instructions described in the program will be described by way of examples and in comparison with the conventional case. FIG. 3 is a diagram showing examples of instructions of a processor and instructions in a program.

Here, it is assumed that the processor 1 has instructions A, B, and C. As shown in the drawing, the instructions in the conventional program are formed by combining the instructions of the processor 1 and the programs are arranged in the order of “A, B, B” and “A, C, C”. It is assumed that a description is made in combination with some units of processing consisting of these instructions.

In such a case, in the instruction of the program according to the present invention, first, an instruction is defined for each processing unit. In the illustrated example, the instruction “P” is defined to perform “A, B, B”, and the instruction “Q” is defined to perform “A, C, C”. As a result, the processor 1 having the instructions A, B, and C can behave as if it has the instruction system of “ABB” or “ACC”.

Therefore, the program instructions in the present invention need only be instructions for each unit of processing such as "perform P" and "perform Q", so that the data amount of the instructions to be executed is reduced. Since the data amount of the read instruction is small, the read time of the instruction is shortened, which leads to the reduction of the execution time and the capacity of the memory 6 for storing the program can be reduced.

Although not shown, in a processor equipped with a cache, instructions stored in the cache are:
In the conventional program, “ABB” and “ACC” are stored, whereas in the case of the program of the present invention, since the instructions P and Q are stored, the instructions themselves are also shortened, and It can be used effectively.

Further, in the illustrated example, the instructions P and Q each defining three instructions are represented by codes compressed by Huffman codes as shown in the column of "instruction code of the present invention". On the other hand, the conventional instruction codes that are not Huffman-coded have the same bit length. Each instruction code is prefixed with “B ′” to indicate that the numerical notation is a binary number.

As described above, when the definition information of an instruction is stored in a compressed form, the instruction issuer 23 for reading the defined instruction has a function of expanding the compressed data. The unit 23 decompresses the read instruction and passes it to the instruction decoder 21.

In the program according to the present invention, the code lengths of the instruction codes of the instructions P and Q in the execution part described after the definition part depend on the frequency of appearance of the instructions. In the example shown in FIG.
Is greater than the number of instructions P, the code length of instruction Q is shorter than the code length of instruction P.

FIG. 4 is a diagram showing examples of instructions of another processor and instructions in a program. Here, it is assumed that the processor 1a has instructions D, E, and F. Instructions in the conventional program are programmed by combining instructions of the processor 1a, and the program is composed of, for example, "D, E, E" and "D, F,
It is assumed that a unit of processing consisting of instructions in the order of "F" is described in combination.

In the case of the program for the processor 1a, it can be seen that the instructions in the conventional program do not have exactly the same parts as compared with the program shown in FIG. However, as can be seen by comparing the columns of the program of the present invention between the processor 1 and the processor 1a, they are exactly the same except for the definition part of the instruction. As described above, by dividing the program into the definition part and the execution part, it is possible to create a program that operates on another processor 1a by rewriting only the definition part. Therefore, when a program for the processor 1 is ported to a program for the processor 1a, basically, only the definition part needs to be changed.

In addition, when the program is not very simple, such as the program described in the example, the execution of the program is overwhelmingly larger than the definition of the instruction, and the program is almost the same. Therefore, when a program that has been operating on the processor 1 is to be operated on the processor 1a, the operation can be performed only by changing the instruction definition portion, and the applicability of the program is greatly increased.

In the above embodiment, all the definition information is stored in the instruction definition storage memory 24. However, when the task or instruction system changes, for example, all the definition information is stored in the instruction definition storage memory 24. May not fit. If the definition information is input beyond the storage capacity of the instruction definition storage memory 24, the definition information used so far is temporarily saved in an external memory, and the instruction definition storage memory is stored when necessary. 24. In this case, for example, the instruction issuer 23 monitors the free space of the instruction definition storage memory 24 and the data amount of the newly read definition information.
4 cannot store the newly read definition information,
The stored definition information may be moved to an external memory, for example, the memory 6, or the saved definition information may be transferred from the memory 6 to the instruction definition storage memory 24 when necessary.

Further, in the above-described embodiment, an example in which the definition information stored in the instruction definition storage memory 24 is compressed by the Huffman code is shown, but an arithmetic code may be used as the compression code.

In the above embodiment, the code lengths of the instruction codes of the instructions P and Q in the execution part of the program depend on the frequency of occurrence of the instructions.
The form may depend on the execution frequency.

Further, the configuration of the processor according to the present invention is not limited to a single processor, but can be similarly applied to a microprocessor having a peripheral processing function, a microcontroller having a built-in program, and the like. .

The processing contents of the functions that the processor should have as shown in FIG. 2 can be described in a recording medium readable by the processor, for example, a program recorded in a ROM (Read Only Memory). . By executing this program with a processor, the above processing can be realized with the processor. The instruction 61 in the memory 6
The data 62 can be a program stored in a storage device in a device in which the processor 1 is mounted, or a program transferred from a storage device of another device through a network.

[0035]

As described above, according to the present invention, there is provided storage means for storing definition information in which one or more existing instructions are represented by different data and defined, and the acquired instruction is a defined instruction. The configuration is such that an instruction is issued using the data of the definition information by referring to the storage means. In this way, a plurality of frequently used instructions are defined in a short data amount and stored in the storage means, and the program instruction uses the defined and stored instruction to reduce the data amount of the entire program. Thus, the read time of the instruction data can be reduced.

Since the frequency of use of each instruction differs depending on the program, the amount of instruction data can be further reduced by changing the definition of the instruction when the nature of the processing of the task or the program changes.

In addition, by defining the processing which has been conventionally performed in a branching manner in order to make a plurality of instructions common, into one instruction, the disturbance of the pipeline due to the re-fetching and the like and the data amount of the instruction are reduced. Execution speed can be improved.

The program executable by the processor is divided into an instruction definition part and a program body, and by rewriting only the instruction definition part, the dependence of the program on the processor can be eliminated, and the instruction definition part is changed. Just be able to run on other processors.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a configuration of a processor according to the present invention.

FIG. 2 is a flowchart showing a flow of instruction execution of the processor of the present invention.

FIG. 3 is a diagram showing an example of an instruction of a processor and an instruction in a program.

FIG. 4 is a diagram illustrating an example of an instruction of another processor and an instruction in a program.

[Explanation of symbols]

1 ... processor 2 ... control unit 3 ... data path unit 4 ... external bus interface unit 6 ... memory
21 ... instruction decoder, 22 ... address generator, 23
.... Instruction issuer, 24 .... Instruction definition storage memory, 31 ...
.. Arithmetic unit, 32 general-purpose register, 51 address bus, 52 data bus.

Claims (10)

[Claims] 1. A processor having a control unit for acquiring an instruction from an external memory and issuing the instruction to a data path unit for performing an operation, wherein one or more existing instructions are represented by different data and defined. Storage means for storing the obtained definition information; determining means for determining whether the obtained instruction is a defined instruction; and storing the information in the storage means when the obtained instruction is determined to be the defined instruction. An instruction issuing means for issuing an instruction to the data path unit using data of definition information. A control unit having an address generator for generating an address for reading the instruction, an instruction issuer for reading data including the generated specified address and issuing the instruction, and an instruction decoder for decoding the issued instruction; A data path unit for executing an instruction based on an instruction issued from the instruction decoder, wherein the control unit includes one or more existing instructions defined by different data. The instruction issuer determines whether an instruction in the read data is a defined instruction, and stores the instruction in the instruction definition storage memory if the instruction is a defined instruction. Using the instructions in the data of the defined information, and using the instructions in the read data if the instructions in the read data are not the defined instructions. Processor, characterized by having a function of issuing a decree. 3. A storage function for storing new definition information of the instruction definition in the instruction definition storage memory when the instruction in the read data is an instruction definition execution instruction for executing the instruction definition. The processor of claim 1, comprising: 4. The data of the definition information stored in the instruction definition storage memory is a compression code, and the instruction issuer has a data decompression function of decompressing the data of the definition information. Item 3. The processor according to Item 2. 5. The processor according to claim 4, wherein said compression code is a Huffman code or an arithmetic code. 6. The processor according to claim 3, wherein the code length of the execution instruction corresponding to the defined instruction depends on the frequency of appearance or execution in a program. 7. The function of the instruction issuer to read the definition information of the instruction from the instruction definition storage memory to the outside of the processor, and to write the definition information of the instruction to the instruction definition storage memory from the outside of the processor. The processor according to claim 2, comprising: 8. A method of operating a processor that operates in accordance with an instruction, comprising: generating an address for reading the instruction; reading data including the generated specified address; and executing an instruction definition in which the instruction in the read data executes the instruction definition. It is determined whether or not the instruction is an instruction. When the instruction in the read data is the instruction definition execution instruction, the definition information in which one or more existing instructions are represented by different data is stored, and the instruction in the read data is stored. Judge whether the instruction is a defined instruction, use the instruction in the data of the definition information stored when the instruction in the read data is a defined instruction, and when the read instruction is not the defined instruction Issuing an operation execution instruction using the read instruction. 9. A processor generates an address for reading an instruction, reads data including the generated specified address, and determines whether an instruction in the read data is an instruction definition execution instruction for executing an instruction definition. When the instruction in the read data is the instruction definition execution instruction, one or more existing instructions are represented by different data to store definition information, and whether the instruction in the read data is the defined instruction is determined. Judgment is performed using the instruction in the data of the stored definition information when the instruction in the read data is a defined instruction, and using the read instruction when the read instruction is not the defined instruction. A processor-readable recording medium recording a program for executing a procedure for issuing an execution instruction. 10. A processor generates an address for reading an instruction, reads data including the generated specified address, and determines whether an instruction in the read data is an instruction definition execution instruction for executing an instruction definition. When the instruction in the read data is the instruction definition execution instruction, one or more existing instructions are represented by different data to store definition information, and whether the instruction in the read data is the defined instruction is determined. Judgment is performed using the instruction in the data of the stored definition information when the instruction in the read data is a defined instruction, and using the read instruction when the read instruction is not the defined instruction. A program for executing a procedure for issuing an execution instruction.