JPS62210542A - Register selecting system - Google Patents

Abstract

PURPOSE:To refer to plural registers by providing a base register where a part of a micro operand address is stored as the base address before the start of execution of a software instruction. CONSTITUTION:The micro operand address given from a decoding part is transferred to a base register 1 and an operand pointer 3 through a signal line 12. A write permitting signal INSTBGN 21 is outputted when execution of a preceding software instruction is terminated, and values of the register 1 and the pointer 3 are settled at the time of the execution of a current software instruction is started. When the register 1 is referred, information of a microprogram latch 2 and the register 1 are used as the micro operand address to refer to a variable number of registers.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a register selection method, and particularly to a register selection method in a microprogram-controlled information processing device.

[Conventional technology]

Conventionally, in register selection systems in microprogram-controlled information processing devices, registers to be referenced in a microprogram are designated by the microprogram itself by storing the microoperand address in an operand pointer or by decoding a software instruction to be executed by a decoder. This is done by storing the obtained micro-operand address in an operand pointer before starting execution of the software instruction, and transferring the micro-operand address of this operand pointer to the micro-operand decoder via the micro-operand bus.

[Problem that the invention seeks to solve]

In the register selection method in the conventional microprogram-controlled information processing device described above, only one register can be referenced for one microoperand address in the operand pointer. When referring to a plurality of registers as one operand, the value of the operand pointer must be sequentially rewritten by a microprogram, which has the drawback of increasing the capacity of control memory and increasing the execution time of software instructions.

In view of the above points, an object of the present invention is to provide a register selection method that can refer to a plurality of registers for one micro-operand address in an operand pointer.

[Means for solving problems]

The register selection method of the present invention includes a control memory that stores a microprogram, and a microoperand address obtained by decoding a software instruction in a decode section, which is stored at the start of execution of the software instruction, or by controlling the microprogram. It includes an operand pointer that stores the contents of a data bus, and a micro-operand bus that transfers the micro-operand address to a micro-operand decoder, and the micro-operand decoder decodes the micro-operand address to access a register to be referenced. In the register selection method, a microprogram latch that holds the microprogram each time before its execution, a base register that stores a part of the microoperand address as a base address before starting execution of a software instruction, and a microprogram control means for controlling data transfer to the base register and simultaneous data transfer from the microprogram latch and the base register to the microoperand bus.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

The figure is a block diagram showing one embodiment of the present invention.The register selection method of this embodiment consists of a base register 1 that holds the base address of the microoperand address, and a microprogram from the control memory (not shown). A microprogram latch 2 for holding a microoperand address, an operand pointer 3 for holding a microoperand address, a data bus 11 controlled by the microprogram, and a microoperand for transferring the microoperand address for a source operand to a microoperand decoder (not shown). Its main parts are composed of a source bus 18 and a microoperand destination bus 19 that transfers a microoperand address for a destination operand to a microoperand decoder.

Operand pointer 3 has a 7-bit configuration,
An input is connected to a data bus 11, and is also connected to a decoding section (not shown) via a signal line 12. The output of operand pointer 3 is connected to micro-operand source bus 18 and micro-operand destination bus 19.

The microprogram latch 2 has a 4-bit configuration, with 2 bits each for specifying a source operand and 2 bits for specifying a destination operand. The input of the microprogram latch 2 is connected to the control store via a signal line 13, and the output is connected to a microoperand source bus 18 and a microoperand destination bus 1 via a signal line 15 and output signal lines 16 and 17.
9 is connected.

The base register 1 has a length of 5 bits, and has an input connected to a decoding section via a signal line 12, and is also connected to a data bus 11. The output of base register 1 is connected to microoverand source bus 18 and microoverando destination bus 19 via signal line 14 and output signal lines 16 and 17.

Note that two bits each of the 5-bit signal line 14 and the 4-bit signal line 15 are combined to form 7-bit signal lines 16 and 17.

Reference numerals 20 to 23 indicate write permission signals for the base register 1, microprogram latch 2, and operand pointer 3, and 24 to 27 indicate output permission signals for the base register 1, microprogram latch 2, and operand pointer 3, respectively.

Next, the operation of the register selection system of this embodiment configured as described above will be explained.

First, a case will be described in which a micro-operand address of a software instruction is given from the decoding section.

The microoperand address given from the decoding section is transferred to the base register 1 and operand pointer 3 via the signal line 12. Write permission signal (INS
TBGN) 21 is output at the end of execution of the previous software instruction, and the values of base register 1 and operand pointer 3 are fixed at the start of execution of the current software instruction.

Let's now assume that the microoperand address is 0000111B (B
is a binary number (the same applies hereafter) is specified in the decoding section, operand pointer 3 contains 000.
0111B is stored, and base register 1 stores 00001B.

When the current software instruction is a multiple-length operation instruction that requires referencing four registers as one operand, the microprogram specifies the operand using base register 1. Data transfer for base register 1 is performed using data bus 11. The write permission signal (BRWR) 20 is activated by the microprogram control means via the
Writing to base register l can be performed at the start of execution of a software instruction or during a read routine.

Base register 1 contains 0000 as the base address.
Since 1B is held, OR4 to GR7 can be referenced. Which register among these GRs is referred to is determined by the value held in the microprogerum rafter 2.

If reference to GR5 is specified in the microprogram, OIB is held on the source operand side of the microprogram latch 2, and the microprogram control means activates the output enable signal (BR-3-3EL) 25 to read the microprogram. 0000101 to operand source bus 18
Output B. This micro-operand source bus I
The micro-operand address on B can be decoded by the micro-operand decoder to make a reference to GR5.

Subsequently, if reference to GR6 is designated in the microprogram, IQB is held on the source operand side of the microprogram latch 2, and 0000110B is output to the microoperand source bus 18. Therefore, a reference to GR6 is made.

Similarly, by using the base address stored in the base register 1 without rewriting the operand pointer 3, operand references in multiple-precision operation instructions can be sequentially performed.

When a software instruction is a normal instruction and refers to the register for one operand, the microprogram specifies the operand using operand pointer 3. Since 0000111B is held in operand pointer 3, GR7 can be referenced. It is. The microprogram control means uses the signal m (PR-3-3EL)
24 can be used to make a reference to Sete GR7.

Note that in the above description of the operation, the case where a register is referred to as a source operand is described, but when a register is referred to as a destination operand, the output permission signal line (BR -D-3EL) 27 Oyohi output permission signal! I (
PR-D-3EL) 26 may be activated.

In addition, since the operand pointer 3 and the base register 1 are also connected to the data bus 11, the signal line (BRWR) 20 and the signal line (
PRWR) 23 can be used to rewrite the contents of operand pointer 3 and base register 1, and by doing this, multiple registers can be referenced for one microoperand address in the operand pointer even during execution of the microprogram. be able to.

〔Effect of the invention〕

As explained above, the present invention performs register reference by providing a microprogram latch that holds a microprogram to be executed and a base register that holds a base address of a microoperand address prior to starting execution of a software instruction. Sometimes, by using information from the microprogram latch and base register as a microoperand address, it becomes possible to refer to a variable number of registers, reducing the control memory capacity and instruction execution time. effective.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of the register selection method of the present invention. In the figure, 1... Base register, 2... Micro program latch 3... Operand pointer, 11... Data bus, 18... Micro operand source bus, 19...
It is a micro-operando destination syllombus.

Claims (1)

[Scope of Claims] A control memory for storing a microprogram, and a microoperand address obtained by decoding a software instruction in a decoding section are stored at the start of execution of the software instruction, or a data bus is stored under the control of the microprogram. and a micro-operand bus that transfers the micro-operand address to a micro-operand decoder, and the micro-operand decoder decodes the micro-operand address to access a register to be referenced. The method includes: a microprogram latch that holds the microprogram each time before its execution; a base register that stores a part of the microoperand address as a base address before starting execution of a software instruction; A register selection method comprising: microprogram control means for controlling data transfer to a register and simultaneous data transfer from the microprogram latch and the base register to the microoperand bus.