JPS6162174A - Information processor - Google Patents

Abstract

PURPOSE:To remove overhead and to effect asymptotic operation at a high speed by supplying operand input to at least one operator connected to the vector registors so as to supply directly the outputs from any operator element in the operator. CONSTITUTION:The information processor has plural vector registors 100-103 for storing a plurality of element data. A reading means 200 reads out the element data from registors 100-103 by actuating operation control means 470. Operator elements 400-402 (m sets m>=1) receiving the 1st and 2nd operand inputs operate the read-out elemental data. Operand switching means 300-305 (2m sets) supply operands selected from operator elements 400-402 and the operated data supplied from reading means 200 as the 1st and 2nd operand inputs for operator elements 400-402 (k sets k<=m). Writing means 450 of the vector registor write the operated outputs from operator elements 400-402 (m sets) into registors 100-103. The asymptotic operation is carried out in such a manner.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to speeding up recurrence formula operations in vector processing in the information processing device.

[Conventional technology]

A conventional vector data processing device has two, for example, vector registers 10 to 13, which store a plurality of element data, as shown in FIG. Vector register reading means 2 for fetching element data from vector registers 10 to 13
0. Arithmetic units 30 to 32 that perform operations on element data taken out from vector registers 10 to 13.
The calculation outputs of the calculation units 30 to 32 are stored in the vector register 1.
It consists of an operand writing means 4° for writing into 4° to 13°.

VO(i)=VO(i-1)XVI(i)+V2(i)
When executing a recurrence formula calculation such as , this recurrence formula calculation was performed by repeating steps ① to 3).

1) V3(i)←VO(t-1), xvx(t)2
) VO(i)←V3(i)+V2(i)3)
i ← i + 1 In Figure 1, VO(i), Vl(i), V2
(i) and V3(i) are vector register 1, respectively.
The 1 multipliers and adders stored in numbers 0 to 13 correspond to arithmetic units 30 and 31, respectively. It takes 1 machine cycle to write element data to the vector register and retrieve element data from the vector register (hereinafter machine cycle is expressed as T), 1 machine cycle to execute multiplication and 5 each to execute addition.
If T and 6T are required, the above recurrence formula calculation will be as shown in the time chart of FIG. First, from vector registers 10 and 11, v o (0) and V 1 (
1) is extracted by IT and supplied to the 2 multiplier 30, and the 5T
v 0(o)x V 1 (1) is executed.

The multiplication result is stored in v3(1) of the vector register 13 by IT. Next, vector registers 13 and 12
V 3 (1) and V 2 (1) are read out by IT and supplied to the adder 31, and V 3 (1) + V at 6T.
2(1) is executed, and the addition result is stored in the vector register 10.
It is stored by applying IT to V O(1) of . Then V O(1) and V 1 from vector registers 10 and 11
(2) is extracted by IT and supplied to the 2 multiplier 30, and V
O(1)XV 1 (2) is executed in 5T and the squaring result is stored in V 3 (2) of the vector register 13. Next, from vector registers 13 and 12, V
3 (2) and V2 (2) are read out by IT and supplied to the adder 31, and V 3 (2) + V 2 (2
) is executed, and the addition result is V in the vector register 10.
Stored in O(2). Thereafter, the above-mentioned recurrence formula calculation is executed by repeating the same process.

[Problem that the invention seeks to solve]

As explained above, in each iteration of the above recurrence formula operation, 2
In addition to the time required for multiplication and addition, the time required to store element data in vector registers and to retrieve element data from vectors and registers.7. .

As the number of repeated operations increases, the overhead increases accordingly.

In general, in recurrence formula operations, the results of the previous operation are used for the next operation, so when performing recurrence formula operations with a conventional vector data processing device, each iteration of the recurrence formula operation requires input to the vector register. When the number of repetitions of operations increases due to writing of element data and retrieval of element data from vector registers.

This method has the disadvantage that it takes an extremely large amount of processing time compared to the actual processing time of recurrence formula calculations.

[Failure to solve the problem]

An object of the present invention is to provide a vector register reading means for reading element data from a vector register.

m with a first operand input and a second operand input
(m≧1) arithmetic units, and 1 ((k≦m) of the arithmetic units
2m operand switching means for supplying operands selected from outputs of the arithmetic units and operation data supplied by the vector register reading means as first and second operand inputs of the m arithmetic units, respectively; , further comprising vector register writing means for writing the calculation outputs of the m calculation units into the vector register, and the element data extracted from the outputs of the m calculation units and the element data taken out from the vector register. By making it possible to supply it as an operand to any one of the m arithmetic units, it is possible to store element data in the vector register and retrieve elements from the vector register, which conventional vector data processing devices had in recurrence formula operations. It is an object of the present invention to provide an information processing device that can perform high-speed recurrence formula calculations while significantly reducing overhead due to data retrieval.

According to the present invention, in an information processing device that includes a plurality of vector registers that store a plurality of element data and performs an operation on element data taken out from a front white vector register, the element data is extracted from the vector register. a vector register reading means, m (m≧1) arithmetic units having a first operand input and a second operand input, and k (k≦m) arithmetic units among the arithmetic units; The operand selected from the output and the operation data supplied by the vector register reading means is
It is characterized by comprising 2m operand switching means for respectively supplying the first and second operand inputs of the m arithmetic units as the first and second operand inputs, and vector register writing means for writing the calculation outputs of the m arithmetic units to the vector register. An information processing device is obtained.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings. Referring to FIG. 3, the information processing apparatus according to the first embodiment of the present invention has an LiO2 vector register 100 for storing a plurality of element data.

Vector register reading means 200 for extracting element data from vector registers 100 to 103, 1 multiplier 400, adders 401 to 402, and arithmetic unit 40
The output of 0 to 402 and the operation data supplied from the vector register reading means 200 are selected and the operation unit 40
Operand switching means 300 to 303 that supply operand inputs 0 and 401, and adders 401 to 40
Operand switching means 304 selects the output of 2 and the operation data supplied from the vector register switching means 200 and supplies it to the operand input of the adder 402, and the adder 40
Operand switching means 305 selects the output of 2 and the operation data supplied from the vector register reading means 200 and supplies it to the operand input of the adder 402;
It has a vector register writing means 450 for writing to 0 to 103, and an arithmetic control means 470.

Next, the manifestation formula V 0 (i) - V O (i -1) XV
The operation when executing the calculation 1(i)t-V2(i) will be described with reference to the time chart of FIG. First, vo(i), vl(i).

V2(i) are vector registers 100 to 1, respectively.
02, and it takes IT (machine cycles) to write the element data to the vector register and take out the element data from the vector register, and 2 multiplication and addition take 5T and 6T, respectively.
1.1. First, by activation of the arithmetic control means 470, the vector register reading means 200 reads v from the vector registers 100 and 101.
o (o) and Vl (1) are taken out by IT and supplied to operand switching means 300 and 301, respectively. The operand switching means 300 and 301 are connected to the arithmetic control means 47.
0 instruction, selects V O(O) and vl(1) supplied from the vector register reading means and supplies them to the multiplier 400. The multiplier 400 is 5 T TEVO(0)X
VI(1) is executed and the multiplication result M(1) is supplied to the operand switching means 302. By activation of the arithmetic control means, the vector reading means 200fd and the vector register 10
Read V2 (1) in synchronization with the 5th multiplication from 2,
It is supplied to the operand switching means 303. Operand switching means 302 and 303 are operated according to instructions from arithmetic control means 470.

M(1) supplied from the 2 multiplier 400 and V2 supplied from the vector register reading means 200, respectively.
(1) is selected and supplied to the adder 401.゛Adder 40
1 is M(1)+V2(1) 6T-1? The execution value addition result A(1) is supplied to the operand switching means 300.

The vector register writing means 450 writes the addition result A
(1) Write to VO(1) of the vector register 100. Upon activation of the arithmetic control means, the vector register reading means reads V 1 (2) from the vector register 101 by IT in synchronization with the sixth addition and supplies it to the operand switching means 301. Operand switching means 30
0 and 301 are A(1) supplied from the adder 401 and V 1 supplied from the vector register reading means 200, respectively, according to instructions from the arithmetic control means 470.
(2) is selected and supplied to the multiplier 400. Multiplier 40
0 executes A(1)XV1(2) in 5T and supplies the multiplication result M(2) to the operand switching means 302.

The vector register reading means is the arithmetic control means 470.
When activated, V2(2) is read out from the vector register 102 and supplied to the operand switching means 303 in synchronization with the fifth one multiplication. Operand switching means 302 and 3
03 is a 9 multiplier 40 according to instructions from the arithmetic control means 470.
M(2) supplied from 0 and vector reading means 2
V2(2) supplied from 00 is selected and supplied to the adder 401. The adder 401 is.

M(2) + V 2 Execute (2) in 6T and add result A
(2) is supplied to the operand switching means 300. The vector register writing means 450 writes the addition result A(2) to the vector register 100 by activation of the arithmetic control means 470.
Write to VO(2) of The vector register reading means 200 is activated by the arithmetic control means 470.

In synchronization with the sixth addition, Vl(3) is supplied from the vector register 101 to the operand switching means 300. By repeating the same procedure, ? @formula operation VO(i)=VO
The final result can be obtained by executing (i-1)XVI(i)+V2(i) a predetermined number of times.

As explained above, in the first embodiment of the present invention, fetching element data from the vector register and storing it in the vector register are executed while overlapping multiplication and addition. The overhead caused by fetching and reading can be extremely reduced, and recurrence formula calculations can be performed at high speed.

Referring to FIG. 5, the vector data processing device according to the second embodiment of the present invention has four vector operation line sets 500, 510, 520 and 530.

The vector operation A eve line set 500 includes a vector register W 501 and an intra-set vector register reading means 502 for extracting element data from the vector register group 501.

An intra-set arithmetic unit 503 that performs an operation on the element data taken out from the vector register 501, and an intra-set vector register writing means 504 that writes the arithmetic output of the in-set arithmetic unit 503 to the vector register group 501.
It has Vector Arithmetic Line Set 5
10.520.

Each of 530 is a vector operation routine set 5.
It has the same configuration as 00. Two more data processing devices are
Vector operation noguibline set 500°510.5
It has a non-cent operand extracting means 600 which receives and takes element data from the intra-cent vector lanester reading means 502, 512', 522, 532 of 20,530, a 1 multiplier 800, and adders 801 to 802. Furthermore, outside of St. [,,.

Operand switching means 700 to 703 select the outputs of the arithmetic units 800 to 802 and operation data supplied from the out-of-set operand extraction means 600 and supply them to the operand inputs of the multiplier 800 and the adder 801, and the adders 801 to 802. Operand switching means 704 selects the operation data supplied from the output and non-set operand extracting means 600 and supplies it to the operand input of the adder 802; The operand switching means 705 selects and supplies the calculated data to the operand input of the adder 802, and the calculation control means 900 is provided.

The calculation outputs of the out-of-set calculation units SOO to 802 are the vector calculation pipeline sets 500.510.520.
530 in-set vector register writing means 504
, 514° 524.534.

Next, the recurrence formula V 0(i)” (VO(+ −1)+V
1(i))XV2(i)° operation will be described with reference to the time chart of FIG. First, V O (1), V 1 (+) + V2 (i) are interleaved and stored in the vector register group of each vector calculation pipeline set, and element data is taken out from the vector register to the non-cent calculation unit and It is assumed that 2T is required to write element data from an out-of-set arithmetic unit to a vector register, and 5T and 6 are required for squaring and addition, respectively.

First, upon activation of the arithmetic control means 900, the in-set vector register reading means 502 of the vector arithmetic pipeline set 500 reads VO(O) from the vector register group 501 and supplies it to the The inner vector register reading means 512 reads Vl(1) from the vector register group 511.
) is supplied to the reading out-of-set operand extraction means 600. The out-of-set operand extraction means 600 is
Operand switching means 70 for VO(O) and vl(1)
2 and 703. Operand switching means 702 and 703 are operated according to instructions from arithmetic control means 900.

VO supplied from the out-of-set operand extraction means
(0) and Vl(1) are selected and supplied to the adder 801. The above operation is performed at 2T. Adder 801.

V O(0)+Vl (1) is executed in 6T and the calculation result A(1) is supplied to the operand switching means 700. By activation of the arithmetic control means 900, the intra-cent vector register reading means 512 and the non-cent operand extracting means 600 extract v2(g) from the vector register group 511 in synchronization with additions 5T and 6T, and perform operand switching. Operand switching means 700
and 701 are '
A (1) and V2 (1) are selected and supplied to the multiplier 800. Multiplier 800 is.

A(1)XV 2(1) is executed in 5T and the multiplication result M(1
) is supplied to the operand switching means 702. The in-set vector register writing means 514 is the arithmetic control means 9
00 writes the squaring result M(1) into the vector register group 511. Intra-set vector register reading means 522 and out-of-set operand retrieval means 6
00 is multiplied by 4T and 5 by the arithmetic control means.
V 1 from vector register group 521 in synchronization with
(2) Take out the output and supply it to the operand switching means 703. Operand switching means 702 and 703 supply M(1) and Vl(2) to adder 801 according to instructions from arithmetic control means 900. The adder 801 is M(1)+V
1 (2) is executed in 6T and the addition result A(2) is supplied to the operand switching means 700. The in-set vector register reading means 522 and the out-of-set operand extracting means 600 are controlled by the arithmetic control means 900 to
In synchronization with T and 6th streets, V2(2) is taken out from the vector register group 521 and supplied to the operand switching means 701. Operand switching means 700 and 701 select A(2) and V2(2) according to instructions from arithmetic control means 900 and supply them to multiplier 800. The multiplier 800 is
A (2)

The in-set vector register writing means 524 is.

Write the multiplication result M(2) to the vector register 521. The intra-set vector register reading means 532 and the non-cent operand extracting means 600 are as follows.

(;1 By activation of the arithmetic control means 900, in synchronization with the 11 multiplications 4T and 5th, V 1 is
(3) is taken out and supplied to the operand switching means 703. Operand switching means 702 and 703 select M(2) and v1(3) according to instructions from arithmetic control means 900 and supply them to adder 801. By repeating the same procedure a predetermined number of times, the recurrence formula VO(i
)=(VO(i −1)+V1(i)) XV2(i)
The final calculation result can be obtained.

As explained above, even in the second embodiment of the present invention, the first
Similar to the embodiment, the extraction of element data from the vector register and the storage of element data into the vector register are performed in two steps.
It is possible to realize a high-speed recursion formula operation by overlapping the multiplication and addition, so that the overhead caused by this can be extremely reduced).

〔Effect of the invention〕

As explained above, the device of the present invention enables the output of any one of the arithmetic units to be directly supplied as an operand input to at least one arithmetic unit connected to a vector register. This has the effect of eliminating the overhead of accessing vector registers in recurrence formula operations, which conventional vector data processing devices had, and realizing high-speed recurrence formula operations. Another advantage is that the number of vector registers used can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional vector data processing device, and FIG. 2 is a time chart showing the operation of the vector data processing device shown in FIG. 1. FIG. 3 is a block diagram showing an example of a conventional vector data processing device. A block diagram showing an example. FIG. 4 is a time chart showing the operation of the information processing apparatus of the first embodiment, FIG. 5 is a block diagram showing the second embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the information processing device of Example 2. 10 to 13 and 100 to 103... vector register, 20 and 200... vector register, reading means, 30 to 32 and 400 to 402.
...Arithmetic units, 40 and 450...Vector register writing means, 300 to 305...Operand switching means, 470...Arithmetic control means, 500°510.5
20.530 . . . Vector operation no. 503.513.523.533... In-cent arithmetic unit, 504, 514, 524, 534... In-set vector register writing means, 600... Out-of-set operand extraction means, 700 to 705... Operand switching means, 800 to 802... Figure 3 Figure 4

Claims (1)

[Claims] 1. In an information processing device that includes a plurality of vector registers that store a plurality of element data, and performs an operation on the element data taken out from the vector register,
a vector register reading means for reading element data from the vector register; m (m≧1) arithmetic units having a first operand input and a second operand input; and k (k≦m) of the arithmetic units; 2m operand switching means for supplying operands selected from the outputs of the arithmetic units and the operation data supplied by the vector register reading means as first and second operand inputs of the m arithmetic units, respectively; An information processing device comprising vector register writing means for writing calculation outputs of the m arithmetic units into the vector register.