JPS58168151A - Pipeline controlling type information processor - Google Patents

Abstract

PURPOSE:To speed up the entire processing, by providing plural number of arithmetic devices for parallel processing at the inside of a pipeline controlling type information processor and equalizing an execution processing time assigned to each phase. CONSTITUTION:The pipeline controlling type information processor is provided with a controller 7, multipliers 1, 2, an adder 6 and selectors 21-23, and the processing time is equalized and assigned in correspondence to each phase. The controller 7 controls the plural number of phases with a high-speed timing pulse, and the plural number of phases comprise an instruction executing process including the extraction of instruction and of operand, calculation of the operand address, execution of operation and storage of result. The multipliers 1, 2 and the adder 6 correspond to one of the plural number of phases, perform parallel processing, select outputs and obtains the result of operation of parallel processing at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pipeline-controlled information processing apparatus configured to perform parallel processing using a plurality of arithmetic units, thereby speeding up the execution cycle.

Conventionally, when increasing the speed of each machine cycle in order to increase the processing speed in a pipeline-controlled information processing device, the instruction execution processing process has to be further subdivided to avoid reducing the amount of information that can be processed within each execution phase. The number of phases was significantly increased. However, it is difficult to equalize the processing time allocated to all phases using this method, so the processing time is determined according to the phase that requires the longest processing time. For this reason, it was not possible to effectively utilize the performance of the phase with a short processing time of 1%, and high-speed processing was not possible as a whole.

An object of the present invention is to solve the above-mentioned drawbacks by providing a plurality of arithmetic units for performing parallel processing inside a pipeline-controlled information processing device, and to equalize the nine execution processing times allocated to each phase. It is an object of the present invention to provide a round pipeline control type information processing device configured so as to speed up the overall processing.

The pipeline-controlled information processing apparatus according to the present invention includes a controller, a plurality of arithmetic units, and a plurality of selectors, and uniformly allocates processing time corresponding to each phase. The controller controls multiple phases using high-speed timing pulses, and the multiple 7 aids control the instruction execution process, including instruction fetch, operand fetch, operand address calculation, operation execution, and result storage. Established. The plurality of arithmetic units correspond to one of the plurality of phases, and are interconnected to perform parallel processing in order to reduce the processing time required to execute the arithmetic operations. These plurality of arithmetic units are operated with phases shifted from each other by a unit i syncycle.

With this K, each phase is allocated at high speed, so that processing can be speeded up. Therefore, when the calculation result is finalized, multiple selectors are operated to select the output from each calculation unit while maintaining the tie-building relationship that matches the operating phase of each calculation unit, allowing for high-speed parallel processing. It is possible to obtain the calculation result of .

DESCRIPTION OF THE PREFERRED EMBODIMENTS A pipeline-controlled information processing apparatus according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a pipeline-controlled information processing apparatus constructed according to the present invention. In Figure 1, the command is a phase ■
The program is divided into 7 aes ■ and executed. In Fig. 1, 1 is the hardware for executing instructions in phase ■, the mark is hardware for executing instructions in phase 3, and ■ is the hardware for executing instructions in 7A phase ■. , ■ is the hardware for executing the instruction in 7 x − x y, ■ is the hardware for executing the instruction in phase V: ■ is the phase ■
hardware for executing instructions.

In Phases I to ■, the following operations are performed. Suwachi.

Phase I: Retrieval of instructions from the first buffer memory for instructions; Phase I: Reading of operands from the instruction register;
and Calculation of operand addresses in the cache memory Phase II: Continuation of operands from the cache memory Phase (1): Multiplication execution phase (2); Addition execution phase (2): Result storage. In FIG. 1, the pipeline-controlled information processing device of this embodiment includes a first buffer memory 8 for the instruction 8, an instruction register 101 for holding the instruction 1, and a general-purpose register that can read two independent words at the same time. 3. Address adder 4, first and second rounding buffer registers 11 and 12 for successively retaining the contents of general-purpose register 3, and third buffer register 13 for retaining the address addition result. The cache memory 5 is accessed according to the address held in the buffer register 13, and the first selector 21 selects the content read from the cache memory 5 or the content of the second buffer register 12.
The fourth and sixth si receive the contents of the buffer register 11 of
Buffer register 14.16. Fifth and seventh buffer registers 15 and 17 that receive the output of the first selector 21, a first multiplier l that multiplies the contents of the fourth and sixth buffer registers, and a sixth and seventh buffer A second multiplier 2 for multiplying the contents of registers, a second selector 22.23 for selecting the output of the first straddling second multiplier 1.2, and a third selector 22.23. 2nd and 3rd respectively
8th and 9th buffer registers 18.19 for receiving the outputs of selectors 22.23 of , adder-1 adder for adding the contents held in the 8th and 9th buffer registers 18.19; 6, a second buffer memory 9 for storing the contents held in the first O buffer register 20, and a controller 7. The controller 7 includes an instruction register 10 and first to first O buffer registers 11.12.13, 14.15.16.17.
18.19.20 give load signal, second and third
A select signal is given to selectors 22 and 23 of. The processing time of the first and second multiplications 91.2 is twice that of the adder 6. 1st to 1st O buffer alysis-11
,12,13,14,ILIL17.18.19.20
Input data is loaded into the input data at the rising edge of the load signal.

The second and third selectors 22 and 23 select the output of the first multiplier 1 when the select signal state is 00, and select the output of the second multiplier 2 when the select signal state is 1. FIG. 2 shows the operation timing of the pipeline control type information processing apparatus shown in FIG. In the 1142 diagram, (1) is the machine cycle, (2) is the first load signal - (3) is the second load signal, (4) is the third load signal, (5) is the select signal, and (6) is the second load signal. )~(9) is instruction A~
This is the instruction execution phase. Figure 2 (6) and (8)
), fV (multiplier 1) indicates that the operation is executed by the first multiplier IK in phase ①. Figure 2 (7
) and (9), ff (multiplier 2) indicates that the operation is performed by the second multiplier 2 in phase (2). The execution of each phase will be discussed below with reference to FIGS. 1 and 2. In machine cycle I, phase I of the instruction is executed and instruction A is fetched from the first buffer register 8.

Machine cycle 2. In machine cycle 3, the instruction person's phase (1) and phase amount are respectively executed, and the instruction person's operands necessary for the operation are connected to the signal line 108,
112 Kl! Served. In machine cycle 4, the instruction's phase (3) is executed, and in the rising phase of the second load signal from the controller 7, the operands on the signal lines 108.112 are transferred to the fourth and fifth buffer registers 14.1, respectively.
5 and the first multiplier l starts multiplication.

On the other hand, in machine cycle 4, phase ■ of instruction B is also executed, and the operands of instruction B are connected to signal lines tos and ttz.
taken out above. In machine cycle 5, the third load signal rises, so the operand of instruction B is taken into the sixth and seventh buffer registers 16 and 17, and the multiplication in the second multiplier 2Fi phase ■ starts. . Arguably, the first multiplier l has completed phase (2) of instruction A and outputs the operation result on signal lines 117 and 118. signal fIs
The select signal on 128 causes the second and third selectors 22.23 to select the output of the first multiplier 1.

In machine cycle 6, the second and third selectors 22.
The operation result of the instruction A selected at 23 is taken into the eighth and ninth buffer registers 18 and 19, and the adder 6 executes the addition of 7 azes. At this time, the second multiplier 2 executes the 7-Aze (2) of the instruction B, and the operation result is output onto the signal lines 119 and 120. Second and third selector 22
, 23 select the results of these calculations. At the same time, the operands of instruction C are set in the fourth and fifth buffer registers 14, 15 by the second load signal, and multiplier l starts phase 2 of instruction C. In machine cycle 7, phase (2) of instruction A is executed, and the result of the instruction's operation is set in the 100th buffer register 20 and then stored in the second buffer memory 11. On the other hand,
The multiplication results of the instruction B selected by the second and third selectors 22 and 23 are stored in the eighth and ninth buffer registers 1.
8.19, adder 6 executes phase V to perform the addition. At this time, the instruction C is processed by the first multiplier IK.
, and the multiplication results are selected by the second and third selectors 22 and 23. Thereafter, the instructions are repeatedly executed in the same manner. Execution of the above series of instructions [Th
Although the processing time is twice as long, the cycle time is set so as to perform high-speed processing similar to the apparent phase.

Phase I if the invention is not applied.

1.1. Since the processing time must be set long for phase V and phase ■ as well as for phase ■, it goes without saying that the processing time is approximately twice as long. A pipeline-controlled information processing device is configured by comprising a controller that controls phases, a plurality of arithmetic units, and a plurality of selectors, and the processing time is allocated equally to each phase.
This has the effect that the cycle time can be set so that even a phase with a long processing time is processed at the same high speed as a phase with an apparently short processing time, and it is possible to effectively increase the instruction execution speed. There is.

[Brief explanation of the drawing]

The first is a block diagram showing an embodiment of the pipeline control type information processing apparatus according to the present invention, and FIG. 42 is a timing diagram showing the processing process of the pipeline control type information processing apparatus shown in FIG.・l... Multiplier 3... General-purpose register 4... Address adder "... Cache memory 6... Adder 7... Controller 8.9.
... Buffer candy 10 - ... Instruction register 11.12, 13, 14.15.16.17.18.1
9.20...Buffer register 21.2L2B...Selector 101~izs...Signal line Patent applicant NEC Corporation Representative Patent attorney Hisashi Inoro

Claims (1)

[Claims] A pipe that is equipped with a means to divide and execute the instruction execution processing process into multiple phases, including calculation of the instruction fetch/O"7" address and fetch/Oland address, execution of operations, and storage of results. In a line control type information processing device, a controller for controlling the plurality of phases using high-speed timing pulses, and a controller corresponding to one of the plurality of phases and for reducing the processing time required to execute the operation The plurality of arithmetic units are connected to each other to perform parallel processing, and the plurality of selectors are configured to select outputs of the plurality of arithmetic units according to instructions from the controller. 1. A pipeline-controlled information processing device characterized in that the processing time corresponding to each of the phases is allocated equally.