JPH0328898A - Data processor - Google Patents

Abstract

PURPOSE:To improve the throughput by varying the interval from a read of each process instruction of one step of a parallel processing program to a read of each process instruction of a next step according to an external command. CONSTITUTION:This data processor consists of a memory 19 stored with the parallel processing program consisting of plural process insutruction sequences, a control means 18 which read process instruction of the parallel processing program out of the memory, step by step, and generates instruction signals corresponding to the read process instructions and a processing means 21 which executes data processing operation corresponding to the respective instruction signals. Further, the control means 18 has an adjusting means 21 which adjusts the interval from a read of each process instruction of one step to a read of each process instruction of a next step according to the external command. Therefore, a program where a few instructions NOP are inserted can be generated. Consequently, the throughput is improved without increasing the capacity of the program memory 19.

Description

TECHNICAL FIELD The present invention relates to a data processing device for processing signal data such as audio signal data.

BACKGROUND ART Audio signal data processing devices capable of controlling a sound field in order to create reverberation and a sense of presence in acoustic spaces such as concert halls and theaters in homes and cars are well known. This is shown in Japanese Patent No. 72615. Such an audio signal data processing device is provided with a DSP (digital signal processor) that performs sound field control by digitally processing an audio signal output from an audio signal source such as a tuner. The DSP includes arithmetic means for performing arithmetic operations such as arithmetic operations, and a data memory for storing audio signal data to be supplied to the arithmetic means. Further, a delay memory for creating signal delay data by delaying the signal data stored in the data memory can be externally attached. The DSP is configured to transfer signal data between each memory and from the memory to the calculation means according to a predetermined program so that calculation processing of the signal data can be repeatedly performed at high speed.

This program is written in a rewritable memory such as a RAM within the DSP, and is changed by a microcomputer outside the DSP each time the sound field mode is switched by operation.

In other words, by changing the program, you can create any acoustic space.

Further, such a program is usually a parallel processing program consisting of two processing instruction sequences. By executing the parallel processing program, two processing operations, such as a signal data transfer instruction from the delay memory to the data memory and a predetermined arithmetic operation instruction, are executed simultaneously within the DSP.

In such parallel processing operations, an execution operation by one processing instruction in one processing instruction string is executed by one processing instruction in the other processing instruction string.
It may take longer than the execution operation by the processing instruction. Therefore, as shown in FIG. 8, when the program count value is added as N, N+1, and N+2, the first program as one processing instruction string is added as a processing instruction OP every time the program count value is added by 1. is newly read, the processing instruction OP is read every time the program count value of the second program as the other processing instruction string is incremented by 2, and processing is not performed with the program count value in between. Instruction NOP is read. That is, the processing instruction OP in the second program requires an execution operation period corresponding to the number of steps in which the program count value is incremented by three.

In such a parallel processing program, the processing operation according to the processing instruction OP of the first program is performed by the processing instruction OP of the second program.
Since the processing instruction oP is not controlled by the processing operation result of the first program, a new processing instruction oP is read every time the program count value of the first program is incremented by one. However, there are cases where the processing operations based on the processing instructions of the first program are dominated by the processing operations results based on the processing instructions of the second program. For example, the processing operation of transferring the signal delay data from the delay memory to the data memory takes more time than the calculation operation, and after the signal delay data is transferred to the data memory, the processing operation when using that data The outcome of the action is controlled. In such a case, the processing operation of one processing instruction OP in the first program is completed, and the processing instruction OP of the next step cannot be read as the program count value increases. Therefore, as shown in FIG. 9, the instruction NOP is inserted into the first program in the same way as the second program, and until the program count value is incremented by 2, each instruction NOP is read and the result of the processing operation by the second program is calculated. The timing is adjusted so that the first program can be used for processing operations by the first program.

However, when the instruction NOP is inserted into a program in this way, the number of steps in the program increases, and the DSP
There were problems in that it could not fit into the internal program memory, and the processing efficiency per program memory capacity decreased.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data processing device that can improve processing efficiency without increasing the capacity of the program memory.

A data processing device according to the present invention includes a memory that stores a parallel processing program consisting of a plurality of processing instruction sequences, and a command signal that reads each processing instruction of the parallel processing program from the memory step by step and corresponds to each read processing instruction. The $IJ control means is comprised of a control means that generates each command signal, and a processing means that executes a data processing operation according to each command signal. The present invention is characterized by having an adjustment means for adjusting the interval between the two in accordance with an external command.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the audio signal data processing device as an embodiment of the present invention shown in FIG.
The signal is supplied to the input/output interface 3 in the DSP 2 via the /D converter 1. A first data bus 4 is connected to the input/output interface 3. Two signal data RAMs 5.6 are connected to the first data bus 4 as data memories for storing audio signal data. Further, a buffer memory 7 is connected to the data bus 4, and the output of the buffer memory 7 is connected to one input terminal of a multiplier 8. A buffer memory 9 for holding coefficient data is connected to the other input of the multiplier 8, and a coefficient data RAMIO for storing a plurality of coefficient data is further connected to the buffer memory 9. ALU (computing unit) 1
1 is provided for performing calculations such as accumulation of the calculation output of the multiplier 8, and the calculation output of the multiplier 8 is supplied to one input. The other human power is supplied with the output of an accumulator 12 that holds the calculation output of ALU II. Further, the output of the accumulator 12 is connected to the data bus 4.

A memory control circuit 31 is connected to the signal data RAM 5. The memory control circuit 31 generates a control signal for controlling writing of data to a designated address in the RAM 5 and reading of data from the designated address. Signal data RAM
6 includes a memory control circuit 32 similar to the memory control circuit 31;
are connected via a switching circuit 33. Switching circuit 33
is controlled by the RAM 6 by a control signal from the memory control circuit 31.
Switching is performed so that data is written to the designated address and data read from the designated address. Further, a memory control circuit 34 similar to the memory control circuit 31 is connected to RAMIO.

The signal data RAM 6 is also connected to a second data bus 14 different from the first data bus 4. Specifically, as shown in FIG. 2, 3-state buffers 39a. 39b is provided, and RA
Three-state buffers 40a and 40b are provided between M6 and the second data bus 14. buffer 39a,
39b, 40a. 40b is turned on and off individually in response to command signals from a sequence controller 18, which will be described later.

That is, the signal data from the first data bus 4 is transferred to the RAM.
6, the buffer 39a is turned on and R
When reading signal data from AM6 to first data bus 4, buffer 39b is turned on. Similarly, when writing signal data from the second data bus 14 to the RAM 6, the buffer 40a turns on, and when reading signal data from the RAM 6 to the second data bus 14, the buffer 40a turns on.
0b is turned on. In this way, the three-state buffers that are turned on according to the command signal are 3 9 a, 3 9 b.
．． It is always one of 40a and 40b.

An interface 16 for data transfer with an external RAM 15 is connected to the data bus 14 .

The external RAM 15 is a delay memory provided for creating delayed signal data of audio signal data, and the larger the storage capacity, the more signal data with a longer delay time can be created. A memory control circuit 35 is provided to designate write and read addresses of the RAM 15, and a delay time data RAM 17 is connected to the memory control circuit 35. Writing and reading of delay time data in the RAM 17 is controlled by a memory control circuit 38.

Interfaces 3, 16, multiplier 8, buffer memories 7, 9, ALU II, accumulator 12, memory control circuits 31, 32, 34, 35, 38, and switching circuit 33
The operation of is controlled by a sequence controller 18. The sequence controller 18 has a program RAM.
19 is connected, and operates according to the program written in the program RAM 19. Program RAM
A program counter 20 is connected to 19, and each time the count value of the program counter 20 is added, the instruction code of the step corresponding to the new count value is added to the program RA.
It is read out from M19 and supplied to the sequence controller 18. Further, a register 21 that holds a plurality of commands from a microcomputer 24, which will be described later, is connected to the sequence controller 18.

Program RAMI9 and register 21 are main bus 2
2, respectively. A microcomputer 24 is connected to the main bus 22 via an interface 23. Also, the main bus 22 has a transfer buffer 26.
．． 27 are connected. The transfer buffer 26 transfers coefficient data supplied from the microcomputer 24 to RAMI.
Temporarily held in order to be stored in O. The transfer buffer 27 temporarily holds delay time data supplied from the microcomputer 24 in order to be stored in the RAM 17.

The microcomputer 24 is a microprocessor, RA
ROM, and an interface (both not shown). A keyboard 25 is connected to the microcomputer 24.

The keyboard 25 has a plurality of mode keys for specifying sound field modes such as Hall 1 and Hall 2 with different sound field characteristics, a frequency band setting key for graphic equalizer adjustment, a level adjustment key, and a mute key (both A plurality of keys such as (not shown) are provided. The ROM of the microcomputer 24 stores, in addition to the DSP control program processed by the microcomputer 24 itself, a plurality of sequence control programs processed by the sequence controller 18, a plurality of coefficient data groups supplied to RAMIO, and the RAM1.
A plurality of delay time data groups for setting read addresses to be supplied to 7 are written in advance.

A clock generator 28 is provided within the DSP 2, and clock pulses are supplied from the clock generator 28 to the sequence controller 18 and also to the program counter 20 via the frequency divider 13. The frequency divider 13 changes the frequency division ratio according to the command held in the command register 21. Further, a clock pulse generated from the clock generator 28 is supplied as a sampling timing signal to the A/D converter 1.

Furthermore, audio signal data output from the interface 3 is supplied to a mute switch circuit 30. When the mute switch circuit 30 is on, the audio signal data is further supplied to the D/A converter 37 via the digital filter 36.

The on/off state of the mute switch circuit 30 is controlled by a command signal output from the sequence controller 18.

In such a structure, the mute switch circuit 3 described above
In addition to the ON/OFF command signal of 0, the sequence controller 18 sends a command signal to transfer the coefficient data group held in the transfer buffer 26 to RAMIO, a command signal to transfer the address data group held in the transfer buffer 27 to the RAM 17, A command signal to transfer the audio signal data from the interface 3 to a designated address in the signal data RAM 5.6, a command signal to read signal data from the designated address in the signal data RAM 5.6 and transfer it to the buffer memory 7, and a command signal to read the signal data from the designated address in the signal data RAM 5.6 and transfer it to the buffer memory 7, from the designated address in RAMIO. ALUII, a command signal for reading coefficient data and transferring it to the buffer memory 9
various arithmetic operation command signals, transfer command signals of the signal data held in the accumulator 12 to the specified address of the signal data RAM 5.6 or the buffer memory 7, transfer from the specified address of the signal data RAM 6 to the write specified address of the external RAMI 5 It generates command signals such as a command signal, a transfer command signal from a delay designated address of external RAM 15 to a designated address of signal data RAM 6, and a reset command signal for initializing RAM 5.6 and external RAMI 5. These command signals are generated at appropriate timings according to commands from the microcomputer 24 or programs stored in the program RAM 19. Note that commands from the microcomputer 24 are sent to the command register 21.
During operation according to the program, the sequence controller 18 monitors the contents of the command register 21 and generates a command signal in response to a command from the microphone computer 24 through an interrupt operation. The command held in the command register 21 is canceled by, for example, the sequence controller 18 when a corresponding command signal is generated.

When any mode key on the keyboard 25 is operated, the microcomputer 24 determines whether or not the mode key is operated to specify a sound field mode different from the current sound field mode, as shown in FIG. 41). If a sound field mode different from the current sound field mode is specified, the sequence controller 18 issues a mute command to immediately turn off the mute switch circuit 30 and enter the mute state.
(step 42), and the sequence control program and coefficient data group α1.corresponding to the operated key are generated.
α2...αn and delay time data group tl, t2
. . . tn is read from the ROM and transferred (steps 43 to 45). The sequence control program is connected to the RA via the interface 23 and the main bus 22.
The data is transferred to M19 and written by a program memory control circuit (not shown). The coefficient data group is transferred to the transfer buffer 26 via the interface 23 and the main bus 22. The delay time data group is transferred to the transfer buffer 2 via the interface 23 and the main bus 22.
Transferred to 7.

When the coefficient data and delay time data are transferred to the transfer buffers 26 and 27 in this way, the microcomputer 24
reads out from the ROM a read timing command specifying the read timing of the transferred sequence control program from the RAM 19 and transfers it (step 46).
. When this timing command is held at a predetermined position in the command register 21, the command is supplied to the frequency divider 13 as a frequency division ratio variable signal, and the frequency divider 13 divides the frequency division ratio according to the contents of the timing command. Make a circular motion. The clock pulse from the clock generator 29 is divided by the frequency division ratio of the frequency divider 13 and supplied to the program counter 20. Therefore,
The counting speed of the program counter 20 corresponds to the sequence control program written in the RAM 19, and the count value of the program counter 20 is incremented by 1 at a timing determined by that speed. RA each time it is added
New processing instructions from the first and second programs among the parallel processing programs stored in the M19 are sent to the sequence controller 18 by the program memory control circuit described above.
The processing commands are respectively read out, command signals corresponding to the processing commands are generated, and processing operations are performed within the DSP 2.

Therefore, when the processing operation according to the processing instruction OP of the first program is not controlled by the processing operation result according to the processing instruction OP of the second program, the counting interval of the program counter 20 is set to one step execution as shown in FIG. This corresponds to hours.

On the other hand, when the processing operation according to the processing instruction OP of the first program is controlled by the processing operation result according to the processing instruction OP of the second program, for example, the counting interval of the program counter 20 is set to 3 as shown in FIG. This corresponds to the execution time of the step.

In other words, in this case, even if the processing operation exceeds the execution time of one step, the count of the program counter 20 will not advance, so the sequence controller 18 side will mark the instruction NOP that is not included in the sequence control program with diagonal lines in FIG. This is the same as inserting it as shown in .

After executing step 46, the microcomputer 24 issues a data switching command to the sequence controller 18 (step 47), and further issues an initialization command (step 48). The sequence controller 18 generates a predetermined command signal to the memory control circuits 34 and 38 in response to the data switching command to write the coefficient data group transferred to the transfer buffer 26 into a predetermined area of RAMIO, and also writes the coefficient data group transferred to the transfer buffer 26 into a predetermined area of RAMIO. The delay time data group transferred to R
It is written to a predetermined area of AM17. In addition, the sequence controller 18 generates the above-mentioned reset command signal to the program counter 20 and the memory control circuits 31, 32, and 35 in response to the initialization command, so that the memory control circuit 31, 3235 outputs the signal data RAM 5.6 and “O” is written to all storage areas of the external RAMI 5.

After executing step 48, a mute release command is issued to the sequence controller 18 to turn on the mute switch circuit 30 and release the mute state (four steps). That is, mute switch circuit 3
0 is turned off only during the period when data and programs in RAMI 0.17 and 19 are changed in order to switch the current sound field mode to another sound field mode. This is to prevent noise signals caused by changes in data or programs from being output.

Next, the signal data processing operation within the DSP 2 will be explained. The audio signal input to the A/D converter 1 is converted into digital audio signal data groups dl, d2...dn at every sampling period synchronized with the clock pulse from the clock generator 28, and the audio signal The data group is supplied to the first data bus 4 via the interface 3. The signal data group supplied to the data bus 4 is supplied to the RAM 5 or 6 and stored therein.

The signal data written in the RAM 6 is sequentially transferred to an output register (not shown) in the interface 16 by the data bus 14, and is further transferred from the output register to an external R.
It is written to the storage location specified by the write address of AM15. This write address is written to the memory control circuit 35.
The number of addresses corresponding to the number of storage locations in the external RAM 15 is changed in a predetermined order for each transfer signal data. Signal data at a storage location specified by the read address in the external RAM 15 is read out and transferred to an input register (not shown) in the interface 16. Since the delay time data stored in the RAM 17 is read by the memory control circuit 38 and supplied to the memory control circuit 35, the read address is set based on the write address according to the delay time data supplied by the memory control circuit 35. is set to That is, the delay time data provides a delay time between the writing timing of one signal data to the RAM 15 and the reading timing thereof. The signal data transferred and held in the manual register in the interface 16 is transferred to the signal data RAM 6 via the data bus 14. This external RAM1
5, delayed audio signal data for sound field control is created.

On the other hand, the coefficient data read from the RAM 10 is supplied to the buffer memory 9 and held there. By properly timing the sequence controller 18, signal data is transferred from the RAM 5.6 or the accumulator 12 to the buffer memory 7, and the multiplier 8 transfers the signal data held in the buffer memory 7 and the signal data held in the buffer memory 9. Multiply the calculated coefficient data. For example, when performing a product-sum operation on a signal data group d++d2...dn and a coefficient data group α1, α2...αn, first, d1 is held and output to the buffer memory 7, and the buffer α1 is held and output to the memory 9, α1・d1 is summed in the multiplier 8, and the ALUI is applied to this α1・d1.
0 is added at I, and the result of the operation is held in the accumulator 12. Next, the buffer memory 7
d2 is held and outputted, α2 is held and outputted to the buffer memory 9, and when α2 ・d2 is calculated in the multiplier 8, α1 ・d1 is outputted from the accumulator 12, and α1 d1 + α2 d2 is calculated in the ALU 11. It will be done. By repeating this, Σα4 −dj is calculated. This value 1αU'dL is output from the interface 3.

As shown in Figure 5, the graphic equalizer (G.E.Q) processing for the right channel and the sound field control (S.
．． F. C) processing, left channel graphic equalizer processing, and right channel sound field control processing are repeated in this order. These four processes are processes using the first data bus 4. On the other hand, the process of creating the delayed audio signal data described above is performed in parallel with the graphic equalizer process and the sound field control process.

That is, as shown in FIG. 4, during the graphic equalizer processing of the right channel and the sound field control processing of the left channel, the delayed audio signal for the sound field control processing of the right channel is transferred from the external RAM 15 to the signal data RAM 6 via the second data path. Data transfer processing is performed, and during left channel graphic equalizer processing and right channel sound field control processing, the external RAM 1 is
5 to the signal data RAM 6, delayed audio signal data for left channel sound field control processing is transferred.

In the case of graphic equalizer processing, the RAM 10 stores coefficient data corresponding to the levels of each frequency band of the left and right channels set in advance by key operations for the graphic equalizer. Coefficient data is read from RAMIO in response to a command signal from sequence controller 18 and transferred to buffer memory 9. On the other hand, the memory control circuit 31 specifies a read address of the RAM 5 for each execution step, and signal data is read from the specified address and transferred to the buffer memory 7 via the data bus 4. Each time the signal data and coefficient data are sequentially transferred to the buffer memories 7 and 9, each data is transferred to the multiplier 8.
Multiplied by The multiplication results are accumulated for each frequency band by the ALUI 1 and the accumulator 12 and outputted via the interface 3.

Next, the switching operation of the switching circuit 33 will be explained. When the processing operation of the DSP 2 is changed by a key operation, the microcomputer 24 stores data in the external RAM 1 as shown in FIG.
5 is used (step 5).
1). For example, when performing the above-mentioned sound field control processing, the processing uses the external RAMI5, and when processing only graphic equalizer processing and filter processing, the external RAMI 5 is used.
This is a process that does not use 5. In the case of processing using the external RAM 15, a memory independent use command is issued to the sequence controller l8 (step 52), and the external RAM 15 is
In the case of processing that does not use M15, a memory sharing command is issued to the sequence controller 18 (step 53). These commands are held in register 21.

The sequence controller 18 generates a command signal to switch the switching circuit 33 according to the content of the command regarding the memory held in the command register 21. That is, in the case of a memory independent use command, the control signal from the memory control circuit 32 is R.
When performing sound field control processing or when performing sound field control processing and graphic equalizer processing in parallel as described above, the writing and reading of signal data RAM 6 is controlled by the memory control circuit 32. Ru.

On the other hand, in the case of a memory sharing command, a control signal is supplied from the memory control circuit 31 to the RAM 5.6, and in the case of processing only for graphic equalizer processing or filter processing that does not use external RAM, the signal data RAM 5, 6 is supplied. Writing and reading are controlled by a memory control circuit 31.

Therefore, the memory control circuit 31 not only specifies the write and read addresses of the RAM 5 but also specifies the address of the RAM 6.

For example, when writing to RAM 5, if the write address becomes equal to or higher than the upper limit address of RAM 5, the writing proceeds to RAM 6 by specifying the address.

Next, the operation when the mute key of the keyboard 25 is operated will be described. microcomputer 24
When the mute key is operated, it is determined whether or not it is in the mute state as shown in FIG. 7 (step 61).
. This is now determined from the contents of the mute flag FM. If it is not in the mute state, it is FM-0, so a mute command is generated (step 62), and the mute flag F
Set the bolt to 1 (step 63). Since the mute command is held in the command register 21, the sequence controller 18 turns off the mute switch circuit 30. On the other hand, if the mute state is FM-1, a mute release command is issued (step 64), and the mute flag FM is reset to ◯ (step 65). Since the mute release command is held in the command register 21 in place of the mute command, the sequence controller 18 turns on the mute switch circuit 30.

Therefore, when the mute key is operated, the mute switch circuit 30 is turned off, and when the mute key is operated again, the mute switch circuit 30 is turned on. While the mute switch circuit 30 is off, the sequence controller 18 continues to generate commands according to the program.

Effects of the Invention As described above, in the data processing device of the present invention, the interval between reading each processing instruction of one step of a parallel processing program and reading each processing instruction of the next step is changed in accordance with an external command. It looks like this. Therefore, if one of the parallel processing programs has a processing instruction OP that requires an execution operation period longer than one step, and the processing operation result is dominated by the processing operation by the processing instruction OP of the other program, the instruction Since it is possible to create a program in which almost no NOPs are inserted into the program, processing efficiency can be improved without increasing the capacity of the program memory. For example, even if the processing operation of transferring signal delay data from the delay memory to the data memory takes more time than the calculation operation, the number of transfers can be executed more often than before with one program.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram specifically showing a part of the device shown in FIG. 1, and FIG.
6 and 7 are flowcharts showing the operation of the microcomputer in the device shown in FIG. FIG. 5 is a diagram showing the temporal relationship with instructions, and FIG. 5 is a diagram showing the order of each processing operation. Explanation of symbols of main parts 2... DSP 4, 14... Data path 5.6... Signal data RAM 7.9... Buffer memory 8... Multiplier 10... Coefficient data RAM 11 ...ALU 12...Accumulator]7...Delay time data RAM]8...Sequence controller book 5 Figure

Claims (3)

[Claims] (1) A memory that stores a parallel processing program consisting of a plurality of processing instruction sequences, reads each processing instruction of the parallel processing program from the memory for each step, and generates an instruction signal corresponding to each read processing instruction. and a processing means that executes a data processing operation according to each of the command signals, the control means reads each processing command of one step to each processing of the next step. A data processing device characterized by having an adjusting means for adjusting an interval until command readout according to an external command. (2) The adjusting means includes a frequency dividing means that divides the clock pulse at a frequency division ratio according to the external command, and performs a counting operation according to the output pulse of the frequency dividing means, and performs a counting operation according to fluctuations in the counted value. 2. The data processing device according to claim 1, further comprising a program counter that determines timing for reading each processing instruction from the memory. (3) The data processing apparatus according to claim 1, wherein one of the plurality of processing instruction sequences includes a processing instruction that is executed after waiting for the completion of an operation by one processing instruction in the other processing instruction sequence.