JPS5790765A - Microprogram controller - Google Patents
Microprogram controllerInfo
- Publication number
- JPS5790765A JPS5790765A JP55165819A JP16581980A JPS5790765A JP S5790765 A JPS5790765 A JP S5790765A JP 55165819 A JP55165819 A JP 55165819A JP 16581980 A JP16581980 A JP 16581980A JP S5790765 A JPS5790765 A JP S5790765A
- Authority
- JP
- Japan
- Prior art keywords
- error
- designation
- register
- circuit
- byte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To facilitate an diagnosis for an error detecting circuit, by providing an error occurrence byte designation bit that designates the byte that caused a fault to a microinstruction word plus an expected error code that can decides an error at the position of the designated byte. CONSTITUTION:The data of a register 200 is inverted and delivered through a parity bit inverting circuit 400 by an error designation occurrence indication signal produced based on the diagnosis designation of a microinstruction register 100 to be set to a register 500. The parity is checked by an error detecting circuit 600, and an error output is registered to a registering circuit 700. Then the output of the circuit 700 is compared 800 with the output of an error code register 900. Thus the normal operation of the circuit 600 is decided, and the microinstructions are successively read and execued. In this case, an expected error code 106 by which the designated byte position can be decided among the microinstruction words is directly fetched to the register 900. Then the AND condition is obtained between error occurrence byte designation bits 104/105 and a diagnosis designation bit 103 to obtain error designation occurrence indication signals 111 and 121.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55165819A JPS5790765A (en) | 1980-11-27 | 1980-11-27 | Microprogram controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55165819A JPS5790765A (en) | 1980-11-27 | 1980-11-27 | Microprogram controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5790765A true JPS5790765A (en) | 1982-06-05 |
Family
ID=15819592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55165819A Pending JPS5790765A (en) | 1980-11-27 | 1980-11-27 | Microprogram controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5790765A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01231134A (en) * | 1988-03-11 | 1989-09-14 | Nec Corp | Artificial fault generating system for information processor |
JPH05166090A (en) * | 1991-12-11 | 1993-07-02 | Ibaraki Keibi Hoshiyou Kk | Burglar monitoring system |
-
1980
- 1980-11-27 JP JP55165819A patent/JPS5790765A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01231134A (en) * | 1988-03-11 | 1989-09-14 | Nec Corp | Artificial fault generating system for information processor |
JPH05166090A (en) * | 1991-12-11 | 1993-07-02 | Ibaraki Keibi Hoshiyou Kk | Burglar monitoring system |
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