JPS5588151A - Diagnostic processing system - Google Patents

Diagnostic processing system

Info

Publication number
JPS5588151A
JPS5588151A JP16388278A JP16388278A JPS5588151A JP S5588151 A JPS5588151 A JP S5588151A JP 16388278 A JP16388278 A JP 16388278A JP 16388278 A JP16388278 A JP 16388278A JP S5588151 A JPS5588151 A JP S5588151A
Authority
JP
Japan
Prior art keywords
logic
check
register
error
read route
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16388278A
Other languages
Japanese (ja)
Inventor
Tetsuo Isaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16388278A priority Critical patent/JPS5588151A/en
Publication of JPS5588151A publication Critical patent/JPS5588151A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to make a check on the propriety of the contents of an error register all the time, by providing a bit modification circuit in the read route of the error register.
CONSTITUTION: To check the read route of error register 5 in diagnostic mode, [1] is set entirely or at a fixed bit position of rewritable register 7 previously, and an [error REG selective] signal is held at logic [1] with AND circuit 13 ON by a [diagnostic mode] signal. Consequently, bit modification circuit 8 outputs logic [1] corresponding to a bit position where logic [1] is set in rewritable resister 7. Therefore, as far as no fault of a logic-[0] stack occurs in the read route, logic [1] is led to processing part 9. If a stack fault occurs, logic [0] is led to processing part 9 and a check is made.
COPYRIGHT: (C)1980,JPO&Japio
JP16388278A 1978-12-27 1978-12-27 Diagnostic processing system Pending JPS5588151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16388278A JPS5588151A (en) 1978-12-27 1978-12-27 Diagnostic processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16388278A JPS5588151A (en) 1978-12-27 1978-12-27 Diagnostic processing system

Publications (1)

Publication Number Publication Date
JPS5588151A true JPS5588151A (en) 1980-07-03

Family

ID=15782577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16388278A Pending JPS5588151A (en) 1978-12-27 1978-12-27 Diagnostic processing system

Country Status (1)

Country Link
JP (1) JPS5588151A (en)

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