JPS5684051A - Data check system - Google Patents

Data check system

Info

Publication number
JPS5684051A
JPS5684051A JP16105179A JP16105179A JPS5684051A JP S5684051 A JPS5684051 A JP S5684051A JP 16105179 A JP16105179 A JP 16105179A JP 16105179 A JP16105179 A JP 16105179A JP S5684051 A JPS5684051 A JP S5684051A
Authority
JP
Japan
Prior art keywords
parity
data
registers
circuit
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16105179A
Other languages
Japanese (ja)
Inventor
Hiroshi Nakamura
Matao Ito
Yoshiro Yoshioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16105179A priority Critical patent/JPS5684051A/en
Publication of JPS5684051A publication Critical patent/JPS5684051A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041Arrangements at the transmitter end

Abstract

PURPOSE:To detect errors in an all-''0'' state and all-''1'' state by providing parity bits as checking bits for data and by giving some of them ODD parity and the others EVEN parity. CONSTITUTION:Data 1 of data bus 1 is given ODD parity by ODD parity generating circuit 4 and the data and parity bits are inputted to registers 6 and 7; and data 2 of data bus 2 is given EVEN parity by EVEN parity generating circuit 5 and the data and parity bits are inputted to registers 8 and 9. Then, contents of registers 6-9 are inputted to registers 10-13 via a data bus and ODD parity check circuit 14 and EVEN parity check circuit 15 make checks respectively. If an all-''0'' state is set owing to a fault of the data bus, circuit 14 detects a parity error and when an all-''1'', circuit 15 detects the parity error.
JP16105179A 1979-12-12 1979-12-12 Data check system Pending JPS5684051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16105179A JPS5684051A (en) 1979-12-12 1979-12-12 Data check system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16105179A JPS5684051A (en) 1979-12-12 1979-12-12 Data check system

Publications (1)

Publication Number Publication Date
JPS5684051A true JPS5684051A (en) 1981-07-09

Family

ID=15727665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16105179A Pending JPS5684051A (en) 1979-12-12 1979-12-12 Data check system

Country Status (1)

Country Link
JP (1) JPS5684051A (en)

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