JPS58220298A - Semiconductor integrated circuit incorporating rom - Google Patents

Abstract

PURPOSE:To deliver simply the contents of an ROM in order of their array, by increasing the content of a program counter one by one just by switching mode signal and then supplying the content of the ROM successively to an instruction decoder and at the same time delivering the contents of the ROM to the outside of an IC. CONSTITUTION:When the logic of a signal 45 supplied from a mode signal register 8 is switched to 0, a load signal 41 if delivered from an instruction decoder 3 is prevented by an AND gate 46. The contents of a program counter 5 are increased by numerical value 1, and the contents of an ROM2 are supplied successively to the decoder 3 and then delivered outside an IC1. The logic of the signal 45 is set at 1 in a normal operation mode. Thus it is possible to take out the contents of an ROM to the outside of an IC with a simple circuit constitution and at a high speed. This makes it possible to test independently the contents of an ROM of a microcomputer, etc. or to use an ROM as a code generator.

Description

[Detailed Description of the Invention] This invention is a semiconductor integrated circuit that has a built-in K ROM in a microcomputer, and generates a code in order to test only the contents of - alone or by sequentially reading the contents of the ROM. The present invention relates to a circuit configuration when used as a code generator.

Conventionally, this type of circuit was shown in Figure O1.

In the figure, (1) comprehensively shows a semiconductor integrated circuit (hereinafter abbreviated as IC) used as a microcomputer, (2) a ROM, (31 an instruction decoder,
(4) is the operand register, +51tl! A program counter, (6) an address register, (7) a selector/decoder, and (81 a mode signal register).

In normal operation mode, the contents of the program counter (51) become an address to the ROM 121 via the selector write decoder (7), and the data stored at that address location is read from I (2) to the instruction decoder (3). hand,
The data is decoded and data processing is performed according to the decoded result. This data processing also includes processing to determine all the addresses of the instructions to be read from the ROM 121 in the next step.If there is no particular command from the instruction decoder (3) to the program counter (5), Counter (5) increment
t) A circuit (not shown) adds a value l to the current content to obtain the next address.

Therefore, in this case, instructions arranged in address order are sequentially read from ROM (2). The operand register (4) may be set with a numerical value (included in the contents of the instruction decoder (3)) that becomes the next address according to the decoding result of the instruction in the instruction decoder (3;). (The contents of the operand register (41 may be input from 31 to the program counter (51). This corresponds to a branch instruction, and the address that accesses ROM +21 is not a contiguous 7 address from the conventional address, but an operand register.) The address register of the numerical value set in the register (41) is performed. Control by the ICD is performed in the above manner.

By the way, depending on the situation, it may be necessary to read out the entire contents of ROM +21 and test it, or if this IC (11
ROM + for the purpose of simply using it as a code generator
The contents of 21 may be read out sequentially. For such cases, a board is provided that can derive the contents of the instruction decoder (3) to the outside, as shown in Figure 1, but in this case,
Since it is undesirable for the contents of the program counter (51) to jump under the control of the instruction decoder (3),
Set all addresses to the address register (6) externally,
The selector/decoder (7) creates an address for ROM +21 from the contents of the address register (6). Switching control of the selector/decoder (7) is performed according to the logic of a mode signal set externally in a mode signal register (81).

FIG. 2 shows the program counter (51, complete) of FIG.

In the block diagram showing all related circuits of the address register (61 and selector/decoder, f9+, in) is a control line that transmits the mode signal output from the mode signal register (81), and 01. (11, (26) are Each bit is a flip-flop that constitutes the program counter (51).

For example, if an address consists of n bits, flip-flops (1, 2), (19), ... (
26) The in-stage consists of a program counter (51), and 13), (20), . . . (27) are its output terminals, respectively. Address register (61 is also a flip-flop for each bit (16), (23),...
・It consists of n flip-flops as shown in (29),
(15,l, (22,1,...(29) are their output terminals, respectively, and (17).

(24) ,...(31) U are each its input terminal. Both the counter (5) and the register (6) have parallel inputs and parallel outputs, but the counter (5) has interstage coupling (32
, 1, (33), ... (34). In addition, (11), (18), ... (25) are signal input terminals from the operand register (41) to each parallel bit of the program counter (5), and (41) is a signal input terminal from the instruction decoder (3) to the program counter. The output load signals are shown.(35), (36),...(37)
), (3B), (39), ... (40).

(42), (431 (44)) are transistors, respectively, and the selector part of the selector decoder (7) is transistors (35), (36), ... (37),
(38), (39), ... (40), terminals (13), (20), ... (2
7) and the signal from terminal α→.

Input the signals from (22),...(29) and connect any signal to the terminals (14), (2υ,...(28)
Output to. (7 is the decoder section of the selector decoder (7).

In the normal operating mode, the signal on the control line (9) is logic "L"
In this case, the signal on the control line 11 is logic "0", and the terminal (14)
, (2υ,...(28) is connected to terminal (13),
(20), ... (27) are connected, and when the load signal (41) is logic "1", the signal from the operand register (4) is connected to the terminal 1ull, Q8),
...(25)' is input to the program counter (51, and the program jumps.The load signal (4
When the logic of 1) is “0”, the program counter (51
The contents of #) are sequentially changed by l by an increment circuit.

Switch the operation mode and set the signal on the control line (9) to logic "o"
If the signal on the control line (1o) is set to logic "1", the output of the address register (6) will be terminals (14) and (21).
, ... (28). Address register (6
) contents are externally connected to terminals (17), (24),...
- (Can be changed by inputting an arbitrary address via 31, 1'e.

ROM 121k When testing, use the instruction decoder (3
) can be output to the outside and compared with a predetermined bit pattern.

Since the conventional circuit is configured as described above, it is necessary to separately provide a register address register 16) and a selector/decoder (7), which not only complicates the circuit and increases the integrated circuit area. Terminal (17).

(24,),...(3υ) had the disadvantage that the address signal input to it had to be created externally.

This invention was made to eliminate the above-mentioned deficiency A' (i = i) in the conventional circuit.
R that can display the contents of +21 in the order of their arrangement
The purpose is to provide a semiconductor integrated circuit with built-in OM.

The present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention.
The same reference numerals as those in Figures and Figure 2 indicate the same or equivalent parts; (
45) is a signal that becomes "l" only in the normal operation mode, similar to signal (9) in FIG. 2, and (46) is an AND gate.

The circuit in Figure 3 is different from the circuit in Figure 2 in that the address register (
6) and the selector decoder (7) are missing, but if the logic of the signal (45) from the mode signal register (8) is "L", the same operating sound as the circuit in Figure 2 will not occur. it is obvious. You can also switch the mode signal and send the signal (
45) If you set the logic to 1rOJ, the instruction decoder (3)
Even if the load signal (41) is output from the AND gate (
46), the contents of the program counter (5) are incremented by the numerical value l, and the contents of ROM +21 are correspondingly sequentially input to the instruction decoder (31) and input to lC.
It is derived outside f1+.

Furthermore, if necessary, the contents of the program counter (5) (
i.e. terminal (131, (20), -(27) +7)
Signal) k It is also easy to provide a hole that leads out the signal to the outside of the IC (1). In addition, some address counters (51) are configured so that their upper bits are not affected by the power applied from the increment circuit. In such cases, only the upper bits are changed under the control of the instruction decoder + 31. All you have to do is make it possible.

In addition, in the case of the mode in which the logic of the signal (45) is set to "o", the connection may be made such that the other control (load signal (other control other than 4υ) decoded by the instruction decoder (31) is executed) You can also leave it connected so that it does not run.

As described above, according to the present invention, the contents of the ROM can be exported to the outside of the ROM at high speed with a circuit configuration that is simpler than the conventional one.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional circuit, Figures 1 and 2 are
FIG. 3 is a block diagram showing the relationship among the program counter, address register, and selector decoder shown in the figure. FIG. 3 is a block diagram showing one embodiment of the present invention. (11...IC, +21...ROM, +31...
・Instruction decoder, 15)...Program counter, (
8)...Mode signal register, (46)...AND gate. In addition, the same reference numerals in the figures indicate the same or corresponding parts. Agent Shin Kuzuno - 2nd v! J Figure 3 L-J Showa Year, Month, Day 21 Name of the Invention ■Built-in Medium Conductor Integrated Circuit 3, Relationship with the Amendment Case Patent Applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name ( 601) Mitsubishi Electric Co., Ltd. Representative: Hitoshi Katayama 4, Agent address: 2-2-3 Chiyo, Tokyo [1 Okibi-no-uchi 2-chome
No. 5, Subject of amendment (1) Detailed explanation of the invention column 6 of the specification, Contents of amendment (1) Page 5 of the specification (r) Replaced the phrase "(29)" with (3)
Correct it as ``0)''. (2) Same book, page 6, line 4 r (43), (44) J
Correct it as r (43),...river...(44) J. (more than) 635-

Claims (1)

[Claims] A ROM (read-only memory), an instruction decoder that stores the contents read from this RAM, a port that outputs the contents of this instruction decoder to the outside, and a program counter that outputs an address signal for reading the ROM. an increment circuit that sequentially increments by l a numerical value determined by at least a predetermined number of lower-order bits of the address signal output from the program counter; The operation mode is switched in accordance with the means for setting the program counter and a signal input from the outside, and in this switched operation mode, the operation of setting all numerical values in the program counter according to the result of decoding the instruction in the instruction decoder is generally performed. the content of the program counter is changed only by the operation of the increment circuit; A semiconductor integrated circuit with a built-in ROM, comprising mode switching means for controlling only the upper bits only when controlling according to the decoded result.