JPH07182156A - Microprogram controller - Google Patents

Abstract

PURPOSE:To detect a delay-over state of the microinstruction read out of a control storage at an early stage by providing a check flag to check the coincidence of value of a read register that holds the exclusive OR of the microinstruction read out of the control storage. CONSTITUTION:When the reading check of a control storage 5 is carried out during and after the FW loading, a selector 4 selects the data where all bits of a microinstruction to be written into the storage 5 are inverted and the data where all bits of the microinstruction are usually not inverted respectively under the control of a pointing flag 7. The selected microinstruction is stored in a read register 6 and a data register 3 respectively. Then a check flag 8 checks the coincidence between the value of the EXOR(exclusive OR) of the output of the resister 6 and the 1-cycle delayed signal of the EXOR of the microinstruction read out of the storage 5. Thus it is possible to detect a delay- over state at an early stage for the microinstruction read out of the storage 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram controller, and more particularly, to detecting a delay of a microinstruction read from a control memory when changing a microinstruction pattern when a clock cycle is accelerated to improve performance. Regarding

[0002]

2. Description of the Related Art FIG. 2 shows the configuration of a conventional example. In FIG. 2, reference numeral 21 is a control unit that controls writing to the control memory 24 and the data register 23.

An address register 22 stores an address of a microinstruction read from the control memory 24 in the next cycle or an address for writing the microinstruction stored in the data register 23 in the control memory 24 in the next cycle.

Reference numeral 23 is a data register for writing a microinstruction into the control memory 24, 24 is a control memory for storing a microprogram having an odd bit width, and 25 is a memory for storing the microinstruction read from the control memory 24. This is a read register.

Reference numeral 26 is a check for storing the result of a match check based on a signal delayed by one cycle of the exclusive OR (EXOR) of the microinstructions read by the control memory 24 and the EXOR value of the output of the read register 25. It is a flag.

A signal from the signal line 201 gives an instruction to write the microinstruction stored in the data register 23 to the control memory 24, and a signal from the signal line 202 writes the microinstruction read by the control memory 24 into the data register 23. Instructions are given.

[0007]

In the above-described conventional microprogram control device, in a microinstruction stored in the control memory and having a bit width of an odd number of bits, a certain bit of the microinstruction read from the control memory at a specified address. In some cases, the delay may be delayed due to the influence of crosstalk in the LSI.

Therefore, although the normal clock operates normally, the exclusive OR (E) of the read microinstruction (E) is used when the clock cycle for improving the performance is accelerated.
XOR) EX of the microinstruction read in the previous cycle
If the value is the same as the value of OR, the EXOR of the microinstruction read from the control memory may not be detected despite the delay over, and the microinstruction was changed for the sake of hardware and firmware (hereinafter referred to as FW). In this case, the EXOR of the read microinstruction differs from the value of the EXOR of the microinstruction read in the previous cycle, and there is a problem that an error is detected for the first time.

[0009]

SUMMARY OF THE INVENTION A microprogram controller according to the present invention includes a control memory for storing a microinstruction having an odd bit width, and which address of the control memory to read or which address. An address register that holds an address that indicates whether to write,
A data register that holds a microinstruction for writing to the control memory, an inverting gate that inverts all bits of the microinstruction stored in the data register, address value control, control memory write instruction, and data register data retention And a read register for holding the exclusive OR of the microinstruction read from the control memory and the microinstruction read from the control memory, and the exclusive instruction generated by the microinstruction held in the read register. A micro program control device having a check flag for performing a match check between the logical sum value and the read register value holding the exclusive logical sum of the microinstructions read from the control memory. Characterize.

[0010]

EXAMPLE FIG. 1 shows the configuration of an example.

In FIG. 1, reference numeral 1 controls the strobe of the address register 2 during the FW load and after completion of the FW load, during which the micro-instruction is read from the control memory 5 one by one and checked, and the control memory 5 and the data register 3 are written. It is a control unit that controls.

2 is an address register for storing the address of a microinstruction read from the control memory 5 in the next cycle or an address for writing the microinstruction stored in the data register 3 in the control memory 5 in the next cycle. It is a data register for writing a micro instruction to the control memory 5.

In the case of checking the reading from the control memory 5 during FW loading and after the FW loading is finished, all bits of the microinstruction written in the control memory 5 are inverted and all bits of the microinstruction are inverted. A microinstruction that selects a microinstruction and writes it in the control memory 5 during normal operation is a selector that selects a microinstruction whose bits are not inverted, and is controlled by an instruction flag 7 described later.

Reference numeral 5 is a control memory for storing a microprogram having an odd bit width, and 6 is a register for storing a microinstruction read from the control memory 5.

Reference numeral 7 is an instruction flag which becomes "1" during the FW loading and after the FW loading is finished and during the read check of the microinstruction from the control memory 5, and controls the selector 4 to select the inverted data. Further, during normal operation, control is performed so that a microinstruction that does not invert all bits of the microinstruction written in the control memory 5 is selected.

Reference numeral 8 is a match check flag for storing the result of a match check based on a signal delayed by one cycle of EXOR of the micro instruction read from the control memory 5 and the value of EXOR of the output of the read register 6, and 9 is a calculation process. It is an address generation unit that generates an address during normal operation after the unit is activated.

Data stored in the address register 2 according to the signal on the signal line 100, hold data, address +
1. Control which address is used among addresses during normal operation. In addition, the timing of writing the micro instruction selected by the selector 4 in the control memory 5 is controlled by the signal of the signal line 101. The signal on the signal line 102 controls the operation of writing the micro instruction read from the control memory 5 into the data register 3.

Next, the operation of this embodiment will be described.

Before the arithmetic processing unit is activated, the micro instruction is written from the address 0 to the final address of the control memory 5.

The address register 2 stores "0", and the data register 3 stores the micro instruction corresponding to the address 0. Since the instruction register 7 is not activated yet, the selector 4 controls the data in which all bits of the microinstruction stored in the data register are inverted. In the next cycle, data in which all bits of the microinstruction to be written are inverted is written in address 0 of the control memory 5. When the writing to the 0th address is completed, the value of the address register 2 is incremented by 1, this operation is repeated until the last address, and the microinstruction in which all the bits for all the addresses are inverted is written in the control memory 5.

When the writing of all the microinstructions to the control memory 5 is completed, "0" is stored in the address register 2, and the microinstruction in which all the bits of the address 0 are inverted is read from the control memory 5 and read. At the same time as it is stored in the register 6, the signal line 102 becomes “1” and is also stored in the data register 3. In the next cycle, control memory 5
A match check is performed based on the EXOR value of the read EXOR of the microinstruction read by one cycle and the EXOR value of the output of the read register 6. In addition, the micro instruction at address 0 in which all the bits stored in the data register 3 are inverted, all the bits are inverted again, and the signal line 101 becomes "1".
And is written in the address 0 of the control memory 5.

At this point, the microinstruction written at address 0 becomes the same microinstruction in which the bit is not inverted in the initial stage.

In the next cycle, the address register 2 indicates the address 0 again, and the microinstruction at the address 0 is read, but the signal line 102 does not become "1" and is not stored in the data register 3.

In the next cycle, a coincidence check is carried out by a signal delayed by one cycle of EXOR of the micro instruction read from the control memory 5 and the value of EXOR output from the read register 6. If there is no error in the match check, the microinstruction one cycle before and the value of all bits are changed at the same address, and the EXOR of the read microinstruction
Therefore, when the pattern of the microinstruction is changed, the delay of the microinstruction read from the control memory by the same address and the EXOR value of the microinstruction is checked. Further, the current address + 1 is stored in the address register 2 according to the signal on the signal line 100.

When the read check from the control memory 5 is completed up to the microinstruction at the final address, the arithmetic processing unit is activated and the instruction flag 7 becomes "0". The address register 2 stores an address generated by an address generation unit that generates an address during normal operation, and controls the arithmetic processing unit by a micro instruction read from the control memory 5. After the arithmetic processing unit is activated, the control memory 5
When writing is performed in the selector 4, the selector 4 selects the microinstruction stored in the data register 3 by the instruction flag 7.

[0026]

As described above, according to the present invention, the EXOR value of the microinstruction read from the control memory is delayed when the pattern of the microinstruction is changed when the clock cycle is accelerated to improve the performance. That is, it is possible to read each microinstruction from the control memory after FW loading and check it, and at the same time, check the delay of the EXOR value of the microinstruction read from the control memory. The delay of the micro-instruction read from can be detected, and the reliability of the arithmetic operation is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional example.

[Explanation of symbols]

 1 control unit 2 address register 3 data register 4 selector 5 control memory 6 read register 7 instruction flag 8 check flag 9 address generation unit 21 control unit 22 address register 23 data register 24 control memory 25 read register 26 check flag

Claims (2)

[Claims] 1. A control memory for storing a microinstruction having an odd bit width, and an address register for holding an address for instructing which address of the control memory the microinstruction to read or write to. A data register that holds a microinstruction for writing to the control memory, an inverting gate that inverts all bits of the microinstruction stored in the data register, address value control, control memory write instruction, and data register data retention And a read register for holding an exclusive OR of the microinstruction read from the control memory and the microinstruction read from the control memory, and an exclusive register generated by the microinstruction held in the read register. Exclusive OR of the OR value and the microinstruction read from the control memory Microprogram control apparatus characterized by having a check flag for performing matching check of the read register value that holds the physical sum. 2. An instruction flag indicating that a firmware memory is being loaded and a read check is being performed from the control memory after the firmware is loaded, and during the read check, all bits of the data register are inverted and written to the control memory. 2. The micro program control device according to claim 1, further comprising a selector for selecting a value of the data register during operation and an address generation unit for generating an address during normal operation.