JPH05298140A - Self-diagnostic system - Google Patents

Abstract

PURPOSE:To shorten self-diagnosis time at the time of starting an information processor by performing another circuit test by a processor while writing test data in a memory by a test circuit. CONSTITUTION:A processor 1 starts the test circuit by writing the test data in a test data store register 10 and afterwards writing start information (1, for example), in a test circuit control register 12. Thus, a test address control circuit 11 successively generates addresses to a memory 2, and the test data are successively written from the test data store register 10 to the memory 2 by a memory read/write control circuit 3. At Such a time, the memory 2 and the test circuit are disconnected from a bus by an address buffer 13 and a data buffer 14. The processor 1 parallelly tests an input/output device control circuit 4. When the input/output device control circuit 4 is completely tested, the test circuit control register 12 is referred to and in the case of an end state (0, for example), the data are read from the memory 2 and comparatively diagnosed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-diagnosis system, and more particularly to a self-diagnosis system for an information processing apparatus having a self-diagnosis circuit other than a memory.

[0002]

2. Description of the Related Art A conventional self-diagnosis method of this type is, as shown in FIG. 2, a processor 1a, a memory 2, and a memory 2.
In an information processing device including a memory read / write control circuit 3a for controlling writing and reading operations to and from the input / output device control circuit 4 which is a self-diagnosis target circuit other than the memory, first of all, when starting up the system, The processor 1a is configured to execute all self-diagnosis in the order of testing the I / O device control circuit 4 after testing the memory 2.

When the processor 1a tests the memory 2, first, the test data is written in the memory 2 and then the data is read from the memory 2 and compared with the written test data for comparison. The operation of the processor 1a, the memory 2, and the memory read / write control circuit 3a in this series of operations will be described below. In the following description, it is assumed that the processor 1a has a data width of n bytes (n is an integer), and the memory 2 has a capacity of m × n bytes (m is an integer).

First, when the processor 1a writes the test data to the memory 2, the processor 1a outputs the address and the test data to the memory 2 to the address bus 5 and the data bus 6, and the read / write signal 7 is written. And As a result, the memory read / write control circuit 3
a activates the memory write signal 8 and the test data from the processor 1a is instructed by the address bus 5 in the memory 2
Is written to the address. Next, the processor 1a
An address obtained by adding n to the previous address is output, and the above operation is repeated. The processor 1a repeats this operation up to the final address of the memory 2, and then moves to read and check the written data.

Next, when the processor 1 reads data from the memory 2, the processor 1a outputs an address to the memory 2 on the address bus 5 and puts the read / write signal 7 into a read state. As a result, the memory read / write control circuit 3a validates the memory read signal 9, and valid data is output from the memory 2 to the data bus 6. The processor 1a takes in this data internally,
Compare with the test data above. If they match, the processor 1a outputs an address obtained by adding n to the previous address, and repeats the above operation. Processor 1
After repeating this operation up to the final address of the memory 2, a shifts to the test of the input / output device control circuit 4. If it does not match the test data, the processor 1a moves to an operation of reporting that an error has occurred.

[0006]

In the above-described self-diagnosis method in the conventional information processing apparatus, the processor executes all data writing and reading in the memory, and the processor remains until the memory test is completed. The circuit under test other than the memory could not be diagnosed. In addition, since the memory access of the processor is 2m in total for writing and reading, the execution time of the memory test increases in proportion to the increase of the memory capacity, and the self-diagnosis by the processor at system startup is performed. There was a problem that the time required for it increased.

An object of the present invention is to provide a self-diagnosis method capable of suppressing an increase in self-diagnosis time at startup even if the memory capacity increases.

[0008]

The self-diagnosis method of the present invention includes a memory capable of writing and reading data,
Self-diagnosis method of information processing apparatus including memory read / write control circuit for controlling writing and reading to and from the memory, a circuit under test other than the above, which is a target of self-diagnosis, and a processor for executing a self-diagnosis program In a test data storage register for storing test data of the memory, a test address control circuit for generating address signals to the memory in a predetermined order, and inserted between the memory and the address bus and data bus. Stored buffer, a test circuit control register for storing control information for instructing activation and stop of these circuits and the memory read / write control circuit, and the processor stores test data in the test data storage register. After storing start-up instruction information in the test circuit control register, It is configured to perform the diagnosis of other circuit under test in parallel with the writing of the test data.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

According to the self-diagnosis method of the present invention, the processor 1
A memory 2, a memory read / write control circuit 3,
In addition to the input / output control circuit 4, a test data storage register 10 for storing test data, and a test address control circuit 11 for generating address signals in a predetermined order.
And an address buffer 13 and a data buffer 14 inserted between the memory 2 and the address bus 5 and the data bus 6, and control information for instructing activation and deactivation of these circuits and the memory read / write control circuit 3. And a test circuit control register 12 for operating the test circuit. The processor 1 writes test data in the test data storage register 10, writes start instruction information (1 or 0) in the test circuit control register 12, and starts the test circuit to the memory 2. Write test data of. During this time, the processor 1 executes the test of the input / output device control circuit 4, reads the data from the memory 2 after the end of this test, and compares it with the test data. The operation of each component in this series of operations is shown below.

First, the initial value of the test circuit control register 12 is a value at which the operation of the test circuit is stopped, and the test data storage register 10 and the test address control circuit 11 are provided.
Does not output the address and test data to the memory 2. On the other hand, the address buffer 13 outputs the address of the address bus 5 to the memory 2 and the data buffer 14
The output direction is determined by the read / write signal 7. That is, in the case of writing from the processor 1 to the memory 2, the data on the data bus 6 is output to the memory 2,
When reading from the memory 2, the data in the memory 2 is output to the data bus 6. Note that the actual writing and reading to and from the memory 2 are executed by the memory write signal 8 and the memory read signal 9 output from the memory read / write control circuit 3 in response to the read / write signal 7.

When starting the memory test, the processor 1
Writes test data to the test data storage register 10, then writes start instruction information (1 or 0) to the test circuit control register 12, and starts the test circuit. As a result, the test address control circuit 11 outputs the head address to the memory 2, and the test data storage register 10 outputs the stored test data to the memory 2. on the other hand,
The output of the address buffer 13 and the data buffer 14 is prohibited.

Next, the memory read / write control circuit 3 outputs the memory write signal 8 and the test data is written to the designated address of the memory 2. When one write is completed, the test address control circuit 11 outputs an address obtained by adding n to the previous address, and repeats the above operation. Each test circuit returns to the initial state after repeating this operation up to the final address of the memory 2, and the test circuit control register 12 is initialized to stop instruction information (0 or 1).
On the other hand, the processor 1 executes the test of the input / output device control circuit 4 while each test circuit is writing the test data in the memory 2.

When the test of the input / output device control circuit 4 is completed, the processor 1 refers to the test circuit control register 12,
It is determined whether the writing of the test data to the memory 2 is completed. If the writing of the test data to the memory 2 is not completed, the processor 1 repeats the above reference operation and waits for the end, and when it is completed, the data read from the memory 2 and comparison are started. Reading of data from the memory 2 and execution of comparison are the same as in the conventional case.

As a result, when the total time of the memory write processing by the test circuit is shorter than the test time of the input / output device control circuit 4 by the processor 1 as compared with the conventional method,
The self-diagnosis time by the processor 1 is shortened by the write time of m times, and when the total memory write processing by the test circuit is longer than the test time of the input / output device control circuit 4 by the processor 1, the input / output device by the processor 1 The time required for testing the control circuit 4 is shortened.

[0017]

As described above, according to the self-diagnosis method of the present invention, the test data is written to the memory in the memory test by the test circuit instead of the processor. While writing
The processor can execute the diagnosis of the circuit under test other than the memory, and has the effect of shortening the time required for self-diagnosis.

The access to the memory of the processor is m
Since the reading is performed only once, the time required for the self-diagnosis when the memory capacity is increased is reduced by the time required for the writing process m times as compared with the conventional method.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional self-diagnosis method.

[Explanation of symbols]

 1, 1a processor 2 memory 3, 3a memory read / write control circuit 4 input / output device control circuit 5 address bus 6 data bus 7 read / write signal 8 memory write signal 9 memory read signal 10 test data storage register 11 test address control circuit 12 Test Circuit Control Register 13 Address Buffer 14 Data Buffer

Claims (1)

[Claims] 1. A memory capable of writing and reading data, a memory read / write control circuit for controlling writing and reading to and from the memory, a circuit under test other than the above, which is a target of self-diagnosis, and a self-diagnosis. In a self-diagnosis method of an information processing apparatus including a processor for executing a program, a test data storage register for storing test data of the memory, and a test address control for generating address signals to the memory in a predetermined order A circuit, a buffer inserted between the memory and an address bus and a data bus, and a test circuit control register for storing control information for instructing start and stop of these circuits and the memory read / write control circuit. The processor stores test data in the test data storage register, A self-diagnosis method characterized in that after the start instruction information is stored in the path control register, the other test circuits are diagnosed in parallel with the writing of the test data in the memory.