JPS6239782B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method and apparatus for detecting an abnormality in a microprogram sequence.

A common method for detecting errors in microprogram storage devices is to add a 1-bit parity bit to the microinstruction and check whether the sum of data "1" in the microinstruction is an even number or an odd number. It is true.

A method in which parity bits are added so that the sum of data "1" becomes an even number is called an even parity method, and a method in which parity bits are added so that the sum of data "1" becomes an odd number is called an odd parity method.

Such an error detection method that adds parity bits is effective in detecting errors when reading microinstructions, but it is effective in detecting errors in microprogram address information and errors in address decoding of microprogram storage devices. cannot detect this error.

Additionally, a watchdog timer method is known as a method for detecting abnormalities due to software or hardware runaway.

A normal watchdog timer constantly counts clocks and is reset by a software command, and if the timer count exceeds a predetermined value before being reset, it outputs a system restart signal. It's summery.

The insertion point of the watch dog timer reset command and the timer setting value are selected so that under normal operation, the timer is always reset before the timer count reaches the set value, and in the case of a program runaway, etc. If the watchdog timer is not reset, the timer count value exceeds the set value and a restart signal is output to interrupt abnormality processing.

Such a watchdog timer system is used to prevent runaway at the software level, and the timer is usually set to a fairly long time. Therefore, although it is effective for detecting sequence abnormalities at the software level, it is not practical for detecting sequence abnormalities at the microinstruction level, which requires quick response.

The present invention was invented in view of the above points,
The object is to provide an abnormality detection method and apparatus that can detect abnormalities in microprogram control sequences caused by errors in address information, errors in address decoding of a microprogram storage device, etc. in a shorter time.

A feature of the present invention is that phase information with respect to a reference clock having a period multiple times that of the microinstruction execution clock is written in each microinstruction, and when the microinstruction is read, this phase information and the phase of the reference clock maintain a constant relationship. The presence or absence of an abnormality in the microinstruction control sequence is determined based on whether or not the microinstruction control sequence exists. In this case, the phase information used is 1 bit if the reference clock has a period twice that of the microinstruction execution clock, and 2 bits if the period is four times that of the microinstruction execution clock.

Hereinafter, the present invention will be explained in detail with reference to Examples. FIG. 1 shows a configuration diagram of an embodiment of a microprogram control device to which the present invention is applied.

The configuration of FIG. 1 includes a microprogram start address generation device 11, a microprogram address selection circuit 12, a microprogram address register 13, a microprogram storage device 14, a microinstruction register 15, and a frequency dividing circuit 3.
1. The main component is a phase error detection device 32. Among these, those closely related to the present invention are:
a phase information bit p added to the microinstruction;
They are a frequency dividing circuit 31 and a phase error detection device 32. 1 microinstruction from the main memory (not shown)
When the word is read, the microprogram start address generation device 11 generates the start address of the microroutine corresponding to the microinstruction word, and this address information is sent to the microprogram address selection circuit 12, the microprogram address selection circuit 12, and the microprogram address selection circuit 12.
Via the register 13, it is sent to the microprogram storage 14, where the corresponding microinstruction is read. The read microinstruction is stored in the microinstruction register 15, and its arithmetic control field 15a is sent to a microinstruction decoder (not shown) and used to generate various control signals. In addition, the address control field 15 of the microinstruction
b is the microprogram address selection circuit 12
is returned to the microprogram address register 13 via the microprogram address register 13, and a series of microinstructions are executed sequentially. On the other hand, the frequency dividing circuit 31 generates a reference clock 4b having a cycle that is an integral multiple of the microinstruction execution clock 4a, and this reference clock 4b is applied to one input of the phase error detection device 32. There is.

Phase information 4c, which will be described later, is applied to the other input of the phase error detection device 32.
The phase of the reference clock 4b at which each microinstruction should be executed is determined, and phase information is written in the phase bit p of the microinstruction.

Here, the phase information of phase bit p is shown as 4c.

Now, the phase error detection device 32 monitors whether the phase information 4c of the phase bit p of the microinstruction read into the microinstruction register 15 and the phase of the reference clock 4c match, and if they do not match, an abnormality detection signal 4d is output. is now output.

The abnormality detection signal 4d is supplied to a microprogram start address generation device, and the start address of the sequence abnormality processing microroutine is generated.

FIG. 2 shows the frequency dividing circuit 31 in the configuration of FIG.
2 shows a specific configuration of the phase error detection device 32. The frequency dividing circuit 31 is composed of one T-type flip-flop, and divides the frequency of the microinstruction execution clock 4a into half to obtain a reference clock 4b. As mentioned above, a phase bit 1 bit p is added to each microinstruction to indicate whether the microinstruction is to be executed at "1" or "0" of the reference clock. The phase error detection device 32 is
Consists of one EOR (exclusive OR) gate,
Reference clock 4b and microinstruction phase information 4c
is input, and outputs an abnormality detection signal 4d.

FIG. 3 shows a time chart of each signal corresponding to FIG. 2, and shows an example of the waveforms of the micro-instruction execution clock 4a, the reference clock 4b, the micro-instruction phase information 4c, and the abnormality detection signal 4d. ing. In the figure, in each microcycle from n-3 to n-1, the reference clock 4b and the microinstruction phase information 4c match, so the abnormality detection signal 4d is "0", but in the n-th microcycle, the abnormality detection signal 4d is "0". , even though the reference clock 4b is "0", the microinstruction phase information 4c becomes "1" and they do not match, so the abnormality detection signal 4d
becomes "1", indicating that an abnormality has occurred in the microprogram control sequence.

According to one embodiment of the present invention configured as described above, it is possible to detect an abnormality in a microprogram control sequence caused by an error in address information or an error in address decoding of the microprogram storage device 14. be. In an embodiment in which a 1/2 frequency divided microinstruction execution clock is used as the reference clock, about half of the microprogram control sequence abnormalities can be detected as phase errors. Furthermore, when an abnormality in the microprogram control sequence is detected, it can be processed by the microprogram, which has the effect that abnormality processing such as restart processing or interrupt processing can be easily performed.

FIG. 4 shows the configuration of the frequency dividing circuit 31 and phase error detection device 32 in another embodiment of the present invention having the configuration shown in FIG. The frequency divider circuit 31 is composed of a two-stage T-type flip-flop.
An instruction execution clock 4a is input, and a clock 4b-1 whose frequency is divided by one half and a clock 4b-2 which is divided by one fourth are obtained. Two phase bits are added to the microinstruction, and the bits are “00”, “01”, “10”, and “11” according to the execution order of the microinstruction.
The phase of is described. Microinstruction register 15
Phase bit 4c-1 of the microinstruction stored in
and 4c-2 are the reference clocks 4b-1 and 4.
b-2, and in a normal operating sequence they match. The phase error detection device 32 detects mismatch between the phase bit and the reference clock, and consists of two EOR gates and an OR (logical sum).
It consists of one gate. That is, 4b
-1 and 4c-1 mismatch or 4b-2 and 4c
-2, the abnormality detection signal 4d becomes "1" when any one of the mismatches occurs.

FIG. 5 shows a time chart of each signal corresponding to FIG. 4, including the microinstruction execution clock 4a, the reference clocks 4b-1 and 4b-2,
Microinstruction phase bits 4c-1 and 4c-
2. An example of each signal waveform of the abnormality detection signal 4d is shown. In the figure, in each microcycle from n-6 to n-1, the reference clocks 4b-1 and 4b-2
and microinstruction phase bits 4c-1 and 4c-2
Since they match, the abnormality detection signal 4d is "0". However, in the nth micro cycle, the reference clocks 4b-1 and 4b-2
Microinstruction phase bits 4c-1 and 4c-
2 are "0" and "1", and because of this mismatch, the abnormality detection signal 4d is "1". That is, in the n-th micro cycle, it is indicated that an abnormality occurred in the microprogram control sequence.

In the case of this embodiment, in which two microinstruction phase bits are added and the microinstruction execution clock is divided by a quarter and used as the reference clock, microprogram control sequence abnormalities are detected with a probability of approximately 75%. This has the effect that it can be detected as a phase error.

As explained in detail above, according to the present invention,
By comparing the phase information written in the microinstruction with the phase of the reference clock, abnormalities in the microprogram control sequence can be immediately detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprogram control device to which the present invention is applied;
4 is a partial specific example circuit diagram of FIG. 1, FIG. 3 is a time chart for explaining the operation of FIG. 2, and FIG. 5 is a time chart for explaining the operation of FIG. 4. 31... Frequency dividing circuit, 32... Phase error detection device.

Claims (1)

[Claims] 1. In a microprogram control sequence in which microinstructions stored in a microprogram storage device are sequentially read out and controlled in synchronization with a microinstruction execution clock, some of the microinstructions include:
Phase information with respect to a reference clock with multiple cycles of the microinstruction execution clock is written, and when the microinstruction is read, it is checked whether the phase information in the microinstruction has a certain relationship with the reference clock. A method for detecting an abnormality in a microprogram control sequence, characterized in that the abnormality detection method is performed by determining the abnormality in a microprogram control sequence. 2. A reference clock generating means for generating a reference clock with a period multiple times that of the microinstruction execution clock in a microprogram control sequence in which microinstructions stored in a microprogram storage device are read out and controlled in synchronization with the microinstruction execution clock. , has a phase comparison means for determining whether or not the phase information for the reference clock written in the microinstruction matches the phase of the reference clock, and the case where the phases do not match is determined to be abnormal. An abnormality detection device for a microprogram control sequence, characterized in that: 3. An abnormality detection device for a microprogram control sequence, characterized in that the reference clock generating means according to claim 2 is a frequency dividing circuit that divides the frequency of a microinstruction execution clock.