JPH11219293A - Address tracing method and tracer memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the consumption of a tracer memory by means of a loop without causing the shortage of trace data by identifying a loop instruction, making a loop part degenerate and writing a degenerate loop part in the tracer memory. SOLUTION: A tracer memory controller 100 is roughly constituted of a control storage part 1 and a tracer part 2. The loop instruction detecting circuit of a tracer control part 21 in the tracer part 2 detects the loop instruction. A control storage(CS) address copy register stores the copy of a CS read address. An OR circuit generates the hold signal of the address copy register. In this case, the loop instruction is identified, the loop part is made degenerate and the degenerate loop part is written in the tracer memory 28. When a CS address is looped at the time of every T-tracing, especially, a repetition part in the middle of the loop part is erased and only the last loop is left.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram address tracing method.

[0002]

2. Description of the Related Art A data processing device controlled by a microprogram includes a tracer memory control device for performing an address trace in order to improve RAS (reliability, availability, and maintainability). The tracer memory control device stores time-series data such as microinstruction addresses in the tracer memory as history information. By reading and analyzing this history information at the time of occurrence of a failure or at the time of debugging, it is possible to investigate the cause of the problem.

A configuration of a conventional tracer memory control device 300 will be described with reference to FIG. The tracer memory control device 300 includes a control storage unit 1 and a tracer unit 2.

The control storage unit 1 has the following elements. (1) Control storage (CS) address control unit 11 The read address of the control storage 13 is controlled. (2) Control storage (CS) read address register 12 The read address of the control storage 13 is set. (3) Control storage (CS) 13 Stores an instruction. (4) Control storage (CS) read data register 14 An instruction read from the control storage 13 is set. (5) Instruction Decoding Unit 15 Decodes an instruction and issues an instruction to HW (hardware).

[0005] The tracer unit 2 has the following elements. (1) Tracer control unit 21 The instruction decoding unit 15 controls the start and end of the trace. (2) Tracer write address selector 22 Selects a write address of the tracer memory 28. (3) Tracer write address register 23 The write address of the tracer memory 28 is set. (4) Tracer write data register 26 The trace data to be written to the tracer memory 28 is set. (5) Tracer memory 28 Stores trace data.

The signal lines have the following meanings. (1) Signal line 31 This is an output of the CS read address register 12. (2) Signal line 32 This is an output of the instruction decoding unit 15. (3) Signal line 35 This is a select signal of the tracer write address selector 22.

Next, address tracing by the tracer memory controller 300 will be described. Typical address trace methods include a T-trace method and an event trace method. In either case, an instruction is first read from the control storage 13 and stored in the CS read data register 14. Next, the instruction stored in the CS read data register 14 is decoded by the instruction decoding unit 15, and a trace start instruction is issued to the tracer control unit 21 to start the address trace.

In the case of the every-T trace method, an address trace is performed as follows. (1) Write trace data (CS address and HW state value) to the tracer memory 28. Here, the address to be written is the address indicated by the value of the tracer write address register 23, and the trace data is the data set in the tracer write data register 26. (2) The tracer write address register 23 is incremented. At the same time, tracer write data register 2
The next trace data is set in 6. (3) Return to (1) and repeat until a trace end instruction is issued.

As described above, in every T tracing method, all the CS addresses during the tracing period are traced. Therefore, if there is a loop, the tracer memory may be filled up by the repetition of the same CS address. In other words, it is necessary to prepare a large tracer memory for long-time tracing.

On the other hand, in the event tracing method, address tracing is performed as follows. (1) In the case of the designated event, for example, when a jump instruction is detected, the trace data (CS) set in the tracer write data register 26 is set at the address indicated by the value of the tracer write address register 23 of the tracer memory 28. Address and HW state value). (2) The tracer write address register 23 is incremented. At the same time, tracer write data register 2
The next trace data is set in 6. (3) Return to (1) and repeat until a trace end instruction is issued.

In the event trace, if the tracer memory has the same capacity, it is possible to trace for a longer time than every T trace. However, trace data may be insufficient depending on the occurrence interval of the event to be traced.

An invention for compensating for the drawbacks of the T-trace method and the event trace method is disclosed in Japanese Patent Laid-Open No. 2-103.
No. 642 (hereinafter referred to as Reference 1). In the tracing method described in the cited example 1, while there is no loop in the instruction, it is the same as the T tracing method, but when a loop appears in the instruction, address tracing is performed as follows. (1) First address (a) of a certain loop (supposed to be A)
And the number of repetitions (Na) is counted each time the same address (a) appears, and the next address (x + 1) of the address (x) of the tracer memory where the first address (a) of the loop A is written Is written the number of repetitions (Na). (2) The first address (a) of loop A is held until another loop (referred to as B) appears. When the loop B appears, the first address (b) is held, and thereafter, the number of repetitions (Nb) of the address (b) is counted. The first address (b) of the loop B is written to the address (x + 2) of the tracer memory. The number of repetitions (Nb) is stored at the next address (x + 3) of the address (x + 2) of the tracer memory storing the first address (b) of the loop B. (3) The same operation as (2) is repeated until a trace end instruction is issued.

According to the address tracing method of the cited example 1, the tracer memory can be saved. However, there are two problems. (Problem 1) When the address loop of the control memory is composed of a plurality of addresses, only the first address of the loop is traced. (Problem 2) There is a loop immediately after the trace starts,
If there are no loops thereafter, only the address of the first loop can be traced.

[0014]

As described above, in the conventional address tracing method, the use of the tracer memory is large in the every T tracing method, while the trace data may be insufficient in the event tracing method.

Further, according to the address tracing method of the cited example 1, the drawback of the every T tracing method can be compensated and the amount of the tracer memory used can be suppressed, but the trace data may be insufficient.

An object of the present invention is to provide an address tracing method and a tracer memory control device in which the amount of tracer memory used is suppressed and trace data does not run short.

[0017]

According to the present invention, especially when the control storage (CS) address is looped at every T trace, a repeated portion in the middle of the loop portion is deleted, and only the last loop is left. Thus, Problem 1 in Reference 1 is solved. In addition, by detecting the end of the loop using a timer, the problem 2 in Reference 1 is solved. As described above, it is possible to suppress the consumption of the tracer memory by the loop without causing a shortage of the trace data.

The tracer memory control device of the present invention includes the following circuit in the tracer section. (1) Tracer write address copy register A copy of the tracer write address register is set in order to record the start of the loop stored in the tracer memory. (2) Control storage read address repetition counter The number of loops of the control storage read address is counted during detection of a loop instruction. (3) Tracer Write Data Selector While the loop instruction is being detected, the HW state value during the trace and the value of the control storage read address repetition number counter are selected in order to trace the number of loops.

The tracer control unit includes the following circuits. (1) Loop instruction detection circuit This is means for detecting a loop instruction. (2) Loop flag Indicates that the loop instruction detection circuit has detected a loop instruction. (3) Control storage address copy register This register stores a copy of the control storage read address. (4) OR circuit Generates a hold signal for the control storage address copy register. (5) Loop start address holding period timer A period for holding the loop start address and the start address of the loop of the trace data is set. (6) Timeout detection circuit Means for detecting timeout of the loop start address holding period timer. (7) First comparison circuit A means for detecting that the control storage read address register and the control storage address copy register have become equal. (8) Second comparison circuit Means for detecting that the value of the control storage address repetition number counter is 2 or more. (9) First AND circuit Generates a select signal for the tracer write address selector. (10) Second AND Circuit Generates a select signal for the tracer write data selector.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a tracer memory control device 100 according to an embodiment of the present invention will be described with reference to the drawings. The tracer memory control device 100 is roughly composed of a control storage unit 1 and a tracer unit 2.

The control storage unit 1 has the following elements. (1) Control storage (CS) address control section 11 The address of the control storage is controlled. (2) Control storage (CS) read address register 12 The control storage read register is set. (3) Control storage (CS) 13 Stores an instruction. (4) Control storage (CS) read data register 14 The data read from the control storage 13 is set. (5) The instruction decoding unit 15 decodes the output of the CS read data register 14 and
Gives instructions to W.

The tracer unit 2 has the following elements. (1) Tracer control unit 21 The instruction decoding unit 15 controls the start and end of the trace. (2) Tracer write address selector 22 Selects a write address of the tracer memory 28. (3) Tracer write address register 23 The write address of the tracer memory 28 is set. (4) Tracer write address copy register 24 A copy of the tracer write address register 23 is set. (5) Control storage (CS) read address repetition counter 25 The number of loops of the CS read address is counted while detecting a loop instruction. (6) Tracer write data register 26 The trace data to be written to the tracer memory 28 is set. (7) Tracer write data selector 27 Selects the HW state value during tracing and the value of the CS read address repetition number counter 25. (8) Tracer memory 28 Stores trace data.

The signal lines are as follows. (1) Signal line 31 This is an output of the CS read address register 12. (2) Signal line 32 This is an output of the instruction decoding unit 15. (3) Signal line 33 This is the output of the CS read address repetition counter 25. (4) Signal line 34 This is a hold signal for the tracer write address copy register 24. (5) Signal line 35 This is a select signal of the tracer write address selector 22. (6) Signal line 36 This is a reset signal for the CS address repetition counter 25. (7) Signal line 37 This is a strobe signal of the CS address repetition number counter 25. (8) Signal line 38 This is a select signal of the tracer write data selector 27.

Next, an embodiment of the tracer control section 21 will be described with reference to FIG. (1) Loop instruction detection circuit 2101 This is means for detecting a loop instruction. (2) Loop flag 2102 Indicates that the loop instruction detection circuit 2101 has detected a loop instruction. (3) Control storage (CS) address copy register 210
4 Store a copy of the CS read address. (4) OR circuit 2103 Generates a hold signal for CS address copy register 2104. (5) Loop start address holding period timer 2105 A period for holding the address at which the loop started by the HW control instruction and the tracer address at the beginning of the loop stored in the tracer memory is set. A loop with a long loop is not regarded as a loop, or a loop with a large number of loops is used for control of tracing by dividing into several loops. (6) Timeout detection circuit 2106 This is a means for detecting a timeout of the loop start address holding period timer 2105. (7) Comparison circuit 2107 This is a means for detecting that the CS read address register 12 and the CS address copy register 2104 are equal. (8) Comparison circuit 2108 This is a means for detecting that the value of the CS address repetition number counter 25 is 2 or more. (9) AND circuit 2109 Generates a select signal for the tracer write address selector 22. (10) AND circuit 2110 Generates a select signal for the tracer write data selector 27.

Next, the operation of the tracer memory control device 100 will be described by taking as an example the case where the tracer controller 21 adopts the embodiment of FIG. (1) An instruction is read from the control storage 13 and stored in the CS read data register 14. (2) The instruction stored in the CS read data register 14 is decoded by the instruction decoding unit 15 and the tracer control unit 21
Is instructed to start tracing (tracing is started). (3) The trace data set in the tracer write data register 26 is written to the address indicated by the value of the tracer write address register 23 of the tracer memory 28. (4) The value of the tracer write address register 23 is set in the tracer write address copy register 24, the tracer write address register 23 is incremented, and the next trace data is set in the tracer write data register 26.

The addresses of the instructions are traced as in (1) to (4). When an instruction having the same address is repeated by a loop or a conditional branch instruction, the address trace of the repeated instruction group is traced to the tracer memory. And the number of repetitions is stored in the tracer memory, so that the same data is not traced.

The following (5) to (9) are operations when the instruction is repeated. (5) If the contents of the CS read data register 14 are a loop instruction and a conditional branch, the loop start address holding period timer 2105 of the CS address copy register 2104 is started. While the loop start address holding period timer 2105 is counting (referred to as loop A), the CS address copy register 2104 is held and stored in the tracer write data register 26 at the address indicated by the value of the tracer write address register 23. The trace data is written to the tracer memory 28. (6) In the loop A, if the content of the CS read data register 14 is not a loop instruction or a conditional branch instruction, and if the loop start address holding period timer 2105 does not detect a timeout, the CS address copy register 2104 And writes the trace data stored in the tracer write data register 26 to the tracer memory 28 at the address specified by the value of the tracer write address register 23. The tracer write address register 23 is incremented, and the next trace data is set in the tracer write data register 26. (7) In the loop A, the control storage read data register 1
4 is a loop instruction or a conditional branch instruction, and if the loop start address holding period timer 2105 does not detect a timeout, the control storage read address register 12 and the control storage address previously held The value of the copy register 2104 is compared.

If the two address values match, it means that the instruction is a loop instruction or a conditional branch instruction having the same control storage address.
And the reset / restart of the loop start address holding period timer 2105 is executed.

When the count value of the control storage read address repetition counter 25 is 2 or more while the loop start address holding period timer 2105 is counting, the tracer write address copy register 24 Set the value of
The trace data stored in the tracer write data register 26 and the value of the control storage address repetition number counter 25 are written to the tracer memory 28 at the address specified by the value of the tracer write address register 23. (8) In the loop A, the control storage read data register 1
4 is a loop instruction or a conditional branch instruction,
If the loop start address holding period timer 2105 has not detected a timeout, the control storage read address register 2 is compared with the value stored in the control storage address copy register 2104 previously held.

If the two address values do not match, it means that the instruction is a loop instruction or a conditional branch instruction having a different control storage address.
5 and the reset / restart of the loop start address holding period timer 2105 are executed.

While the loop start address holding period timer 2105 is counting (referred to as loop B), the control storage address copy register 2104 is held, and the tracer write address is designated by the value of the tracer write address register 23. Data register 26
Trace data stored in the tracer memory 28
Write to (9) In the loop A, the control storage read data register 1
4 is a loop instruction or a conditional branch instruction,
After the loop start address holding period timer 2105 detects a timeout, the same control storage address is treated as a new loop.

Therefore, as in (8), the control storage read address repetition number counter 25 is reset, and the loop start address holding period timer 2105 is reset and restarted.

While the loop start address holding period timer 2105 is counting, the control storage address copy register 2104 is held, and is stored in the tracer write data register 26 at the address indicated by the value of the tracer write address register 23. The trace data is written to the tracer memory 28.

[0034]

According to the address tracing method and the tracer memory control device of the present invention, a long trace can be performed with a small trace memory, and trace data resulting from an event occurrence interval and an address loop configuration can be obtained. An address trace of the control storage address without causing a shortage can be executed.

Although the present invention has been described based on the embodiments, the present invention is not limited to these embodiments, and it is understood that changes and improvements can be made within the ordinary knowledge of those skilled in the art. Of course.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a tracer memory control device 100 according to an embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment of a tracer control unit 21;

FIG. 3 is a block diagram showing a configuration of a conventional tracer memory control device 300.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 control storage unit 2 tracer unit 11 control storage (CS) address control unit 12 control storage (CS) read address register 13 control storage (CS) 14 control storage (CS) read data register 15 instruction decoding unit 21 tracer control unit 22 tracer Write address selector 23 Tracer write address register 24 Tracer write address copy register 25 Control storage (CS) read address repetition counter 26 Tracer write data register 27 Tracer write data selector 28 Tracer memory 31, 32, 33, 34, 35, 36, 37, 38 signal line 2101 loop instruction detecting circuit 2102 loop flag 2103 OR circuit 2104 control storage (CS) address copy register 2105 loop start address holding period Ma 2106 time-out detection circuit 2107 and 2108 comparison circuit 2109,2110 AND circuit

Claims (6)

[Claims] 1. An address tracing method for tracing a control storage address by a T-tracing method, comprising the steps of: identifying a loop instruction; degenerating a loop portion; and writing the degenerated loop portion to a tracer memory. An address tracing method comprising: 2. An address tracing method for tracing a control storage address by every T tracing method, wherein a step of detecting repetition of the same address, and a step of writing only the last loop of a loop portion into a tracer memory. An address tracing method comprising: 3. The address trace method according to claim 2, wherein the end of the loop is detected by a timer. 4. An address tracing method for tracing a control storage address by every T tracing method, wherein: a step of detecting repetition of the same address; a step of detecting the end of a loop by using a timer; Writing only the last loop to the tracer memory. 5. A tracer memory control device for tracing a control storage address by a T-trace method, a loop detecting means for detecting repetition of the same address, a repetition counter for counting the number of repetitions of a loop, Tracer memory control means for writing only the last loop into the tracer memory. 6. The tracer memory control device according to claim 5, further comprising: a timer; and a time-out detection circuit for detecting, by the timer, that a predetermined loop start address holding period has elapsed. Tracer memory controller.