JP2007241431A - Trace data recording device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a trace data recording device for suppressing the bit width of a trace memory, managing a time stamp with the minimum information quantity, and efficiently utilizing the trace memory. <P>SOLUTION: This trace information writing means keeps updating the value of a real time counter in a trace memory in the count-up state by an n bit counter, and when a cycle for writing bus information in the trace memory is decided by a cycle deciding means, the write address of the trace memory is incremented, and the bus information and the value of the n bit counter are written, the n bit counter is reset, and the counting of the n bit counter is started. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an in-circuit emulator and a debugging system used for program development and debugging, and more particularly to a trace data recording apparatus.

  In the development of embedded programs for various system devices, a technique is generally taken in which the operation status of a processor is taken into a trace memory, and the contents of the trace memory are analyzed and debugged.

  In recent years, the operating speed of processors has been significantly increased. For this reason, it is virtually impossible to analyze the debug by drawing the trace bus inside the processor to the outside. Therefore, in order to perform a real-time trace for the operation of the processor, it is necessary to mount a trace memory inside the processor.

  However, since the size of the trace memory greatly affects the cost, the memory size is also practically limited. Therefore, it is a problem to use the trace memory effectively.

The following method is generally used as a method for reducing the amount of data written to the trace memory when the trace memory is used.
(1) First, data is not taken into the trace memory while the program is executed at consecutive addresses.
(2) Data is taken into the trace memory only in the cycle of the branch instruction.

  According to the above method, the amount of memory used can be suppressed. In this method, since the time interval for writing to the trace memory is random, it is necessary to record a time stamp. Recording time stamps is usually handled by increasing the bit width of the memory.

  Thus, the bus information and time stamp are written in the trace memory. Here, in order to avoid frequent occurrence of overflow, the time stamp needs to have the same bit width as the bus information. However, this will halve the number of frames that can be captured as a trace memory.

The invention disclosed in Patent Document 1 relates to a program trace data recording method and a trace memory, and Patent Document 2 relates to a trace information recording apparatus of an information processing system. In any of the inventions, the time stamp difference is always recorded in the trace memory together with the trace data.
JP 2004-30505 A JP-A-4-257936

  An object of the present invention is to provide a trace data recording apparatus that suppresses the bit width of a trace memory, manages a time stamp with a minimum amount of information, and effectively uses the trace memory.

The present invention has been made to achieve the above object. The trace data recording apparatus according to claim 1 according to the present invention,
CPU status when CPU fetches or reads / writes data, bus information including address bus and data bus, and count value of real-time counter that counts the number of cycles in synchronization with CPU clock from the start of program execution In the trace data recording device that writes to the trace memory during the cycle of
A write cycle determination means for determining a cycle for writing bus information to the trace memory;
An n-bit counter that counts elapsed cycles from the cycle in which the bus information is written to the trace memory;
Controls whether the real-time counter value is written to the trace memory or the bus information and the n-bit counter value, and identifies whether the information recorded in each address of the trace memory is the value from the real-time counter or the bus information Trace information writing means for writing an information identification flag to the trace memory,
The trace information writing means continues to update the value of the real-time counter to the trace memory when the n-bit counter counts up.
If the cycle determination means determines that the cycle is to write the bus information to the trace memory, the trace memory write address is incremented, the bus information and the n-bit counter value are written, the n-bit counter is reset, and the n-bit counter is reset. It is characterized by starting the count.

The trace data recording device according to claim 2 according to the present invention,
The real-time counter clock and CPU operating clock are asynchronous or have different frequencies.
The time until the n-bit counter is counted up is set to be shorter than the time until the lower m bits of the real-time counter are counted up,
2. The trace data recording apparatus according to claim 1, wherein the trace information writing means writes the bus information and the lower m bits of the real-time counter to the trace memory when writing the bus information.

The trace data recording device according to claim 3 according to the present invention,
Real-time counter monitoring means for storing the value of the real-time counter immediately after the bus information is written in the trace memory and monitoring the rotation of the real-time counter is further included.
When the real-time counter monitoring means detects that the real-time counter has made a full turn since storing the value of the real-time counter immediately after the bus information is written in the trace memory, it notifies the trace information writing means to that effect,
3. The trace information writing means increments the write address to the trace memory and writes the value of the real-time counter to the trace memory when receiving the notification that the real-time counter has made a round. This is a trace data recording device.

  By using the present invention, in the trace data recording apparatus, the bit width of the trace memory can be suppressed, the time stamp can be managed with the minimum amount of information, and the trace memory can be effectively utilized.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments according to the invention will be described with reference to the drawings.

[First Embodiment]
The trace data recording apparatus according to the first embodiment of the present invention generally includes bus information and time stamp difference (n-bit) data in the trace memory within a certain time from the previous write to the trace memory. If a certain time has elapsed after writing, the time stamp is written in all bit trace memories until the next trace information is written.

  FIG. 1 shows a trace data recording apparatus according to the first embodiment of the present invention. FIG. 2 is a schematic diagram showing a recording state of the trace memory constituting the trace data recording apparatus according to the first embodiment of the present invention. FIG. 3 is a flowchart of the operation of the trace information writing means 12 constituting the trace data recording apparatus according to the first embodiment of the present invention.

  The CPU 2A of the evaluation chip 2 constituting the trace data recording apparatus shown in FIG. 1 operates in accordance with the system clock, and bus information such as status (54), address bus (52), data bus (50), etc. becomes trace data. .

  The real-time counter 4 starts counting simultaneously with the start of program execution by the CPU 2A. The write cycle determination means 8 monitors the bus information and, when detecting trace data to be written to the trace memory 6 such as a program fetch such as a branch instruction or a read / write cycle, writes the trace data to the trace information writing means 12. Request.

  When the program starts to be executed, the trace information writing means 12 sets the n-bit counter 10 in the “counted up state” (FIG. 3, S02), and repeatedly writes the value of the real-time counter 4 to the start address of the trace memory 6 (FIG. 3 S04, S06, S08, NO).

  When there is a trace data write request from the write cycle determining means 8 (FIG. 3, S08, YES), the trace information writing means 12 indicates that the n-bit counter 10 is in the “counted up state”, and therefore the trace memory 6 3 is incremented (FIG. 3, S10), the bus information and the value of the n-bit counter 10 are written to the trace memory 6 (FIG. 3, S12), and the n-bit counter 10 starts counting (FIG. 3). -S14).

  The trace information writing means 12 stops the writing of the value of the real-time counter 4 to the trace memory 6 until the n-bit counter 10 becomes “counted up” (FIG. 3, S16 / NO, S18 / NO). The n-bit counter 10 waits for a “count-up state” or the generation of a write request from the write cycle determination means 8.

  Thereafter, if there is a write request from the write cycle determining means 8 (FIG. 3, S18, YES) before the n-bit counter 10 becomes “counted up” (FIG. 3, S16, NO), the above operation ( S10, S12, S14) are repeated. That is, the trace information writing means 12 increments the write address to the trace memory 6 (FIG. 3, S10), writes the bus information and the value of the n-bit counter 10 to the trace memory 6 (FIG. 3, S12), The n-bit counter 10 is reset and starts counting again (S14 in FIG. 3).

  When the n-bit counter 10 is in the “counted up state” before the write request from the write cycle determination means 8 is received (S16 / YES in FIG. 3), the trace information writing means 12 sets the write address to the trace memory 6. It increments (FIG. 3, S20) and continues to write the value of the real-time counter 4 (FIG. 3, S06, S08, NO).

  FIG. 2 shows a recording state of the trace memory 6 constituting the trace data recording apparatus according to the first embodiment of the present invention, that is, a data structure on the trace memory 6. The information identification flag is “0” when the data content is the real-time counter 4 (value), and is “1” when the data content is the bus information and the n-bit counter 10 (value). The trace information writing unit 12 sets the information identification flag.

  In the first embodiment, the real-time counter 4 and the n-bit counter 10 operate with the same system clock as the CPU 1A. For this reason, the description regarding them is omitted in FIG.

  In the trace data recording apparatus according to the first embodiment, the debug control unit 16 controls the trace data reading unit 14 so that the trace data recorded in the trace memory 6 is read out via the communication unit 20. The data is expanded in the trace data restoring means 26 on the host computer 22. Here, the trace data may be output from the trace memory 6 using serial or parallel dedicated output means.

[Second Embodiment]
In general, the trace data recording apparatus according to the second embodiment of the present invention can calculate the elapsed time without contradiction even when the clock of the CPU and the clock of the time stamp are different, and the time stamp recorded in the trace memory 6 Therefore, the trace data can be recorded without increasing the bit width.

  That is, unlike the trace data recording apparatus according to the first embodiment described above, the time stamp clock (second clock generating means 42) by the real time counter 4 is the CPU system clock (first clock generating means 40). If it is different from the above, an error may be included in the calculation result of the elapsed time. Although it is possible to use the clock of the real-time counter 4 as the clock of the n-bit counter 10, when the clock of the real-time counter 4 is faster than the CPU clock, the count-up time of the n-bit counter 10 is shortened. As a result, the bit width of the data taken into the trace memory 6 must be increased.

  Therefore, in the trace data recording apparatus according to the second embodiment of the present invention, the lower bits (lower m bits) of the real-time counter 4 are used as differential data to be written together with the bus information. FIG. 4 is a part of a trace data recording apparatus according to the second embodiment of the present invention. FIG. 5 is a schematic diagram showing a recording state of the trace memory 6 constituting the trace data recording apparatus according to the second embodiment of the present invention. The trace data recording apparatus according to the second embodiment is substantially the same as the trace data recording apparatus according to the first embodiment. Therefore, FIG. 4 mainly shows the difference between the two.

  In the n-bit counter 10 shown in FIG. 4, the time until the n-bit counter 10 becomes “counted up” is shorter than the time until the lower m bits of the real-time counter 4 become “counted up”. Set to be slightly shorter. As shown in FIG. 5, when there is a write request from the write cycle determination means 8 (see S08 and S18 in FIG. 3), the trace information writing means 12 sends the bus information and the lower m bits of the real-time counter 4 to the trace memory 6. (See S12) and the n-bit counter 10 starts counting (see S14). The subsequent operation of the trace information writing unit 12 is the same as that of the first embodiment. The entire data structure of the trace memory 6 is as shown in FIG. 5. In the case of bus information, the value of the lower m bits of the real time counter 4 is written. This makes it possible to calculate the elapsed time.

[Third Embodiment]
The trace data recording apparatus according to the third embodiment of the present invention generally enables recording for a time exceeding the bit width of the time stamp counter. In other words, in the trace data recording apparatus according to the first and second embodiments, the range that can be measured by the number of bits included in the counter (real-time counter 4) used for time stamp measurement is limited, and the counter overflows. After that, the elapsed time cannot be calculated.

  Therefore, in the trace data recording apparatus according to the third embodiment of the present invention, the real time monitoring means 18 is provided. FIG. 6 is a part of a trace data recording apparatus according to the third embodiment of the present invention. FIG. 7 is a schematic diagram showing a recording state of the trace memory constituting the trace data recording apparatus according to the third embodiment of the present invention. The trace data recording apparatus according to the third embodiment is substantially the same as the trace data recording apparatus according to the first embodiment. Therefore, FIG. 6 mainly shows the difference between the two.

  As described in the first embodiment, when there is a write request from the write cycle determination unit 8, the trace information writing unit 12 writes the trace data into the trace memory 6 and starts counting by the n-bit counter 10. When the n-bit counter 10 enters the “counted up state”, the value of the real-time counter 4 starts to be written into the trace memory 6. At this time, the real-time counter monitoring means 18 stores the count value at the start of writing in the trace memory 6, and monitors the real-time counter 4 until the value appears again in the real-time counter 4. That is, the real time counter monitoring means 18 monitors the circulation of the real time counter 4.

  Here, when the real-time counter monitoring means 18 detects that the real-time counter 4 has made a round, it notifies the trace information writing means 12 to that effect. When receiving the notification that the real-time counter 4 has made a full turn, the trace information writing means 12 increments the write address to the trace memory 6 and further writes the value of the real-time counter 4 to the trace memory 6.

  As a result of the above operation, in the trace data recorded in the trace memory 6, there may occur a place where the value of the real-time counter 4 is continuously written as shown in FIG. At this time, the number obtained by subtracting “1” from the continuous number of locations where the data of the information identification flag “0” continues indicates the number of times the real-time counter 4 has circulated at that time.

1 is a trace data recording apparatus according to a first embodiment of the present invention. It is a schematic diagram which shows the recording condition of the trace memory which comprises the trace data recording device concerning the 1st Embodiment of this invention. It is a flowchart of operation | movement of the trace information writing means 12 which comprises the trace data recording device based on the 1st Embodiment of this invention. It is a part of trace data recording device concerning a 2nd embodiment of the present invention. It is a schematic diagram which shows the recording condition of the trace memory which comprises the trace data recording device which concerns on the 2nd Embodiment of this invention. It is a part of trace data recording device concerning a 3rd embodiment of the present invention. It is a schematic diagram which shows the recording condition of the trace memory which comprises the trace data recording device which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

2 ... evaluation chip, 2A ... CPU, 4 ... real time counter, 6 ... trace memory, 10 ... n bit counter, 12 ... trace information writing means, 18 ... real time Counter monitoring means.

Claims (3)

CPU status when CPU fetches or reads / writes data, bus information including address bus and data bus, and count value of real-time counter that counts the number of cycles in synchronization with CPU clock from the start of program execution In the trace data recording device that writes to the trace memory during the cycle of
A write cycle determination means for determining a cycle for writing bus information to the trace memory;
An n-bit counter that counts elapsed cycles from the cycle in which the bus information is written to the trace memory;
Controls whether the real-time counter value is written to the trace memory or the bus information and the n-bit counter value, and identifies whether the information recorded at each address of the trace memory is the value from the real-time counter or the bus information Trace information writing means for writing an information identification flag to the trace memory,
The trace information writing means continues to update the value of the real-time counter to the trace memory when the n-bit counter counts up.
If the cycle determination means determines that the cycle is to write the bus information to the trace memory, the trace memory write address is incremented, the bus information and the n-bit counter value are written, the n-bit counter is reset, and the n-bit counter is reset. The trace data recording device is characterized by starting counting. The real-time counter clock and CPU operating clock are asynchronous or have different frequencies.
The time until the n-bit counter is counted up is set to be shorter than the time until the lower m bits of the real-time counter are counted up,
2. The trace data recording apparatus according to claim 1, wherein the trace information writing means writes the bus information and the lower m bits of the real-time counter to the trace memory when writing the bus information. Real-time counter monitoring means for storing the value of the real-time counter immediately after the bus information is written in the trace memory and monitoring the rotation of the real-time counter is further included.
When the real-time counter monitoring means detects that the real-time counter has made a full turn since storing the value of the real-time counter immediately after the bus information is written in the trace memory, it notifies the trace information writing means to that effect,
3. The trace information writing means increments the write address to the trace memory and writes the value of the real-time counter to the trace memory when receiving the notification that the real-time counter has made a round. Trace data recording device.

Images