JP2009217385A - Processor and multiprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor and a multi-processor for acquiring profile information of cache miss when a target program actually runs, for each function. <P>SOLUTION: The processor 11 is provided with: a local memory 23; a clock counter for counting a clock signal based on a clock signal; a function call control part 41 for, when detecting a function call, outputting the counter value of a clock counter, a program counter value and information on the address of a skip destination or a return destination to a local memory 23; and a cache miss control part 42 for, when detecting a cache miss, outputting the counter value of the clock counter, the program counter value and the information on an access address to the local memory 23. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a processor and a multiprocessor, and more particularly to a processor and a multiprocessor having a cache miss profile function.

  Conventionally, a cache memory (hereinafter also simply referred to as a cache) has been used to increase the processing speed of a program operating on a processor. In order to effectively use the cache, after investigating the temporal locality of the program (ie, the data reuse rate and its temporal characteristics) and the spatial locality (ie, the ubiquity of the data storage location) It is essential to reduce the cache miss overhead.

  Conventionally, in order to investigate the occurrence of a cache miss, a cache miss event detector and a cache miss performance measurement register are used. That is, when the cache miss event detector detects a cache miss occurrence event in the processor, a cache miss performance measurement register (hereinafter referred to as a cache miss counter) is incremented to measure the number of occurrences of a cache miss. Can do.

  The number of cache misses held in the cache miss counter can be read by a command described in the target program. Since there is only one cache miss counter, the number of cache misses can be measured by reading the cache miss counter at an arbitrary position in the target program and storing it in another location. For example, when measuring the number of cache misses in each function in the target program, the counter value is read before each function is executed, the counter value is read again after each function is executed, and the difference between the counter values before and after the execution of each function is read. By calculating the number of cache misses in each function. By doing so, it is possible to obtain profile information regarding the cache of the measurement object, for example, each function.

  However, in the method described above, in order to obtain cache profile information, it is necessary to recompile and recompile the target program in advance so as to include code for measuring the number of cache misses. Therefore, the target memory that includes code for measuring the number of cache misses and the target program that does not include code for measuring the number of cache misses will change the memory layout of the code due to compiler optimization. There is a high possibility that a result different from the profile information during actual operation is obtained.

  In addition, in the method of extracting memory access status by software simulation, CPU memory access status information affects the system behavior for the problem that information different from the actual system operation can be obtained. There has been proposed a technique of a CPU memory access analysis device that outputs to the outside (see, for example, Patent Document 1).

  In the technology according to the proposal, the CPU memory access analysis device detects a process change, selects an event identifier and a virtual address output from the CPU, and outputs it as cache miss information when a cache miss hits.

However, with this technology, it is impossible to obtain information on how much and at what timing a cache miss occurs for each function.
JP 2006-285430 A

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a processor and a multiprocessor capable of obtaining, for each function, profile information of cache misses during actual operation of a target program. And

  According to one aspect of the present invention, upon detecting a memory, a clock counter that counts a clock signal based on a clock signal, and a function call, the counter value of the clock counter, the program counter value, and a jump destination or return A function call control unit that outputs the information of the previous address to the memory, and a cache miss that outputs the counter value of the clock counter, the program counter value, and the access address information to the memory when a cache miss is detected. And a processor having a controller.

  According to the processor and multiprocessor of the present invention, it is possible to obtain cache miss profile information for each function during actual operation of the target program.

Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the processor system according to the present embodiment will be described with reference to FIG. FIG. 1 is a configuration diagram showing a configuration of a processor system according to the present embodiment.

  The processor system 1 includes a processor 11 and a main memory 12. The processor 11 is connected to the system bus 14 via a bus interface (hereinafter abbreviated as I / F) 13, and the main memory 12 is also connected to the system bus 14.

The processor 11 includes a core processor 21, an event control unit 22, and a local memory 23 as a temporary storage memory. The local memory 23 is a RAM memory that temporarily stores data.
The core processor 21 includes a decoder 31, an instruction cache 32, a data cache 33, and an interrupt controller 34.
The core processor 21 reads and executes instructions and data stored in the main memory 12 via the system bus 14. The instruction and data read from the main memory 12 are temporarily stored in the instruction cache 32 and the data cache 33, respectively. The decoder 31 reads and decodes an instruction in the instruction cache 32, and the core processor 31 executes the decoded instruction on necessary data read from the data cache 33. The core processor 31 outputs and stores the instruction execution result in a predetermined area of the main memory 12.

  A program executed by the processor 11 is stored in an external storage device (not shown) or the like, and a program read from the external storage device is stored in the main memory 12. The instruction cache 32 and the data cache 33 temporarily store instructions and data read from the main memory 12, and the decoder 31 continuously executes the instructions to execute the program stored in the main memory 12. Processing is executed.

  Further, when a predetermined event occurs during the execution of the program, an interrupt process is executed. The interrupt controller 34 controls the execution of the interrupt process.

  The event control unit 22 is a circuit unit formed by a hardware circuit including a function call control unit 41, a cache miss control unit 42, and a data control unit 43.

  The core processor 21 has a flag setting unit for enabling or disabling the function of the event control unit 22, and enables (ENABLE) or disables the function of the event control unit 33 according to the flag set in the flag setting unit ( DISABLE). Therefore, by enabling the event control unit 33, it is possible to obtain cache miss profile information as described later.

  When the instruction decoded by the decoder 31 is a branch instruction, a jump instruction, or a return instruction, the function call control unit 41 detects the execution of these instructions as a predetermined event. The decoder 31 outputs the decoded instruction code to the function call control unit 41. When the function call control unit 41 detects that the execution of these instructions is a predetermined instruction, the function call control unit 41 calculates the program counter value at the time of detection, the jump destination or return destination address, and the time at that time, that is, the clock counter value. Log data is recorded in the local memory 23 which is a primary storage memory. That is, when the function call control unit 41 detects a function call, the function call control unit 41 obtains the counter value of the clock counter 51, the value of the program counter (hereinafter abbreviated as PC), and the jump destination or return destination address information, The function call control unit to be output to 23 is configured.

  The cache miss control unit 42 detects a cache miss between the instruction cache 32 and the data cache 33 as a predetermined event. That is, when there is a cache miss access to the instruction cache 32 and the data cache 33, the cache miss control unit 42 detects the cache miss as a predetermined event. When the cache miss control unit 42 detects these predetermined events, the program counter value at the time of detection, the accessed address, that is, the access address, and the time at that time, that is, the clock counter value are used as log data for primary storage. Output to the local memory 23 of the memory.

  In the data control unit 43, a threshold for the amount of data stored in the local memory 23 is set. The data control unit 43 monitors the amount of data recorded in the local memory 23 that is a local memory. When the amount of data stored in the local memory 23 exceeds a predetermined threshold value, the data control unit 43 outputs a predetermined interrupt signal to the interrupt controller 34. The interrupt controller 34 is an interrupt control unit that executes a corresponding predetermined interrupt routine and stores log data of the local memory 23 in a predetermined data storage area 12 a of the main memory 12. As described above, the cache miss profile data is automatically stored in the main memory 12. The main memory 12 is a data storage memory for storing cache miss profile data. That is, when the data control unit 43 detects that the amount of data stored in the local memory 23 exceeds a predetermined threshold, the data control unit 43 stores the data stored in the local memory 23 in the main memory 12 that is a data storage memory. It is a control part to transfer.

Next, the configuration of each control unit described above will be described in detail.
FIG. 2 is a block diagram for explaining the configuration of the processor 11 in more detail.

  In the processor 21, in addition to the configuration described in FIG. 1, a cache miss detection unit 35, a PC register 36 that holds a PC value, a jump destination register 37 that holds a jump in an instruction, that is, a jump destination address, A return in the instruction, that is, a return destination register 38 that holds a return destination address is shown.

  When a cache miss occurs in the instruction cache 32 and the data cache 33, the cache miss detector 35 outputs cache miss event information and access address information when a cache miss occurs in the data cache.

  The event control unit 22 includes a counter 49 in addition to the function call control unit 41, the cache miss control unit 42, and the data control unit 43.

  The function call control unit 41 includes an instruction comparison unit 44 and a function information output unit 45. The instruction comparison unit 44 receives the instruction code decoded by the decoder 31 and each instruction code of a branch instruction, jump instruction, or return instruction. The instruction comparison unit 44 compares the decoded instruction code with each instruction code of the branch instruction, jump instruction, or return instruction, and the decoded instruction code is any of the branch instruction, jump instruction, or return instruction. When the instruction code matches, the coincidence signal is output to the function information output unit 45.

  Data of the PC register 36, the jump destination register 37, and the return destination register 38 are input to the function information output unit 45. Further, the function information output unit 45 also receives a clock counter value signal from a clock counter 51 that counts the CLK signal based on a clock (hereinafter abbreviated as CLK) signal.

When a predetermined instruction is detected, the function call control unit 41 obtains a clock counter value, a PC value, a function call when the predetermined instruction is detected, and information on a jump destination or return destination address. And output to the local memory 23 via the counter 49.
The counter 49 counts up by a value corresponding to the data amount of log data output from the function call control unit 41.

  The cache miss control unit 42 includes a cache miss information output unit 46. The cache miss information output unit 46 receives event information and access address information as a cache miss detection signal from the cache miss detection unit 35. Further, the PC value information of the PC counter 36 and the clock counter value signal from the clock counter 51 are input to the cache miss information output unit 46.

  The cache miss control unit 42 stores the clock counter value, the PC value, the cache miss when the cache miss is detected, and the access address information when the cache miss is detected in the local memory 23 via the counter 49. Output.

  The counter 49 counts up by a value corresponding to the amount of log data output from the cache miss control unit 42.

  The data control unit 43 includes a threshold comparison unit 47 and a threshold holding unit 48. The threshold comparison unit 47 compares the predetermined threshold held in the threshold holding unit 48 with the count value of the counter 49 indicating the data amount of the log data stored in the local memory 23, and the count value is equal to or greater than the threshold. Then, a predetermined interrupt signal is output to the interrupt controller 34. As described above, when receiving the predetermined interrupt signal, the interrupt controller 34 executes a data transfer process from the local memory 23 to the main memory 12. The counter 49 is reset when data is transferred.

  The threshold comparison unit 47 may monitor the data amount of the local memory 23 and compare the data amount with the threshold.

  The event control unit 22 is supplied with power Vdd, but is supplied with power Vdd via a switch (hereinafter abbreviated as SW) 52. As described above, the core processor 21 has the flag setting unit 53. When the flag setting unit 53 is set to enable the event control unit 22, the flag setting unit 53 is supplied with a switch signal so that the SW 52 is turned on. The SW 52 controls power supply to the function call control unit 41 and the cache miss control unit 42. The flag setting unit 53 is a function setting unit that sets whether the functions of the function call control unit 41 and the cache miss control unit 42 are valid or invalid. That is, SW 52 and flag setting unit 53 constitute a function setting unit for enabling or disabling the functions of function call control unit 41 and cache miss control unit 42 based on the signal set in flag setting unit 53. .

In the above configuration, when the target program is executed, the processor 11 operates as follows.
When a branch instruction, a jump instruction, or a return instruction is detected during execution of the target program, the function call control unit 41 is a clock counter value, a PC value, a function call when those instructions are detected, Then, information on the jump destination or return destination address is output to the local memory 23 via the counter 49.
For example, the function call control unit 41 outputs these pieces of information in CSV format as follows.

(Clock counter value), (PC value), (function call), (jump destination or return address)
In addition, when a cache miss is detected during execution of the target program, the cache miss control unit 42 is the clock counter value, the PC value, the cache miss when the cache miss is detected, and the cache miss The access address information is output to the local memory 23 via the counter 49.
For example, the cache miss control unit 42 outputs these pieces of information in the CSV format as follows.

(Clock counter value), (PC value), (cache miss), (access address)
Accordingly, in response to the execution of a predetermined instruction and the occurrence of a cache miss, the above-described information is output to the local memory 23 via the counter 49 in, for example, CSV format and recorded as log information. To go.

  Information from the function call control unit 41 and the cache miss control unit 42 is accumulated in the local memory 23. When a predetermined amount of data is accumulated, the information is transferred to the data storage area 12a of the main memory 12 by the interrupt controller 34. Is done.

  Since the log information stored in the data storage area 12a of the main memory 12 includes the information of the jump destination and return address, the function can be specified based on the address. By analyzing, the number of cache misses for each function can be counted.

Next, an analysis example using the cache miss profile data obtained as described above will be described.
1) Correlation of function cache misses
For example, FIG. 3 is a table showing function names and the number of cache misses for each function. The target program includes a plurality of functions. In FIG. 3, “1279797” cache misses occur when the function name “func_a” is executed, and “42607” cache misses occur when the function name “func_b” is executed. It is indicated that “20364” cache misses have occurred during the execution of “func_c”.

  That is, the number of cache misses for each function can be indicated. The name of the function to be executed and the function name of the transition destination can be obtained from the PC value, jump destination or return destination address information, and debug information at the time of the branch instruction, jump instruction, and return instruction. From these address information, the spatial locality can be known. A function with a large number of cache misses has a large miss penalty, and therefore it is considered that reducing the number of cache misses is effective in improving the processing speed of the entire program.

  Therefore, it can be understood that tuning is performed from the function name “func_a” because the overhead of cache miss is greatly reduced by tuning from the function having the most cache misses.

2) Temporal correlation between occurrence of function and cache miss For example, FIG. 4 is a diagram showing table data of a function, a clock counter value, and an access address. FIG. 5 is a scatter diagram of the accessed real addresses over time. The horizontal axis is the time of function call and return, that is, the axis of the clock counter value, and the vertical axis is the axis of the real address of the memory when accessed at the time of function call and return.

  FIG. 5 shows that a cache miss has occurred at the time indicated by the vertical solid line CM. That is, FIG. 5 shows the timing at which a cache miss occurs in time series, so that the temporal locality of the cache miss can be known.

  Since the log data output from the function call control unit 41 and the cache miss control unit 42 includes a clock counter value, as shown in FIG. 5, the so-called branch, jump, return time, cache miss Since the time at the time of occurrence is obtained, the transition of the function can be associated with the occurrence of the cache miss.

  When the occurrence situation of the cache miss in the same time range R1 in FIG. 5 corresponding to the data in the time range R1 shown in FIG. 4 is seen, the functions arranged on the same line of the cache are alternately accessed. Therefore, it can be seen that a cache miss occurs at each access. In particular, when a cache miss similar to that in the time range R1 occurs repeatedly, if each function is efficiently arranged in the memory, it is considered that the cache miss can be significantly reduced.

  FIGS. 6 and 7 are diagrams showing table data of functions, clock counter values, and access addresses when the memory arrangement of functions is changed so as to reduce the occurrence of cache misses as shown in FIG. FIG. 7 is a scatter diagram of the accessed real addresses over time. As can be seen from FIG. 7, the number of cache misses in the range R2 corresponding to the range R1 in FIG. 4 is greatly reduced.

  As described above, according to the processor according to the present embodiment described above, a register such as a conventional cache miss counter is not provided, and a cache miss measurement code is not included in the program. Cache miss profile information during actual operation of the target program can be obtained for each function.

  In particular, since the output log information includes time information, it is possible to specify the location and time at which the cache miss occurred. As a result, when tuning the target program, it is possible to reduce the number of cache misses by optimizing the memory layout of the program.

  Also, log information is temporarily stored in the local memory on the processor, and when it exceeds a certain threshold value, it is transferred to the data storage memory. Therefore, the output log information is always transferred to the data storage memory. Log information can be stored at high speed.

  Note that the processor according to the above-described embodiment can also be applied to a multiprocessor in which a plurality of processors are provided on a semiconductor chip. That is, the above-described function call control unit 41, cache miss control unit 42, data control unit 43, and local memory 23 are provided in each processor on the multiprocessor. FIG. 8 is a diagram illustrating a configuration example of a multiprocessor. As shown in FIG. 8, the multiprocessor 61 includes a plurality of processors 11, and the plurality of processors 11 are connected to each other by a bus 62.

  The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows the structure of the processor system concerning embodiment of this invention. It is a block diagram for demonstrating in detail the structure of the processor concerning embodiment of this invention. It is a figure which shows the table which shows the function name and the cache miss frequency of each function concerning embodiment of this invention. It is a figure which shows the table data of a function, a clock counter value, and an access address concerning embodiment of this invention. It is a scatter diagram in the time passage of the accessed real address concerning an embodiment of the invention. FIG. 6 is a diagram showing table data of a function, a clock counter value, and an access address when the memory arrangement of the function is changed so as to reduce the occurrence of a cache miss as shown in FIG. 5 according to the embodiment of the present invention. is there. FIG. 6 is a scatter diagram over time of an accessed real address when the memory arrangement of a function is changed so as to reduce the occurrence of a cache miss as shown in FIG. 5 according to the embodiment of the present invention. It is a figure which shows the structural example of the multiprocessor concerning embodiment of this invention.

Explanation of symbols

1 processor system, 11 core processor, 12 main memory, 13 bus interface, 14 system bus, 21 core processor, 22 event control unit, 23 local memory, 31 decoder, 32 instruction cache, 33 data cache, 34 interrupt controller, 41 function Call control unit, 42 cache miss control unit, 43 data control unit, 51 clock counter, 52 switch, 53 flag setting unit, 61 multiprocessor, 62 bus

Claims (5)

Memory,
A clock counter that counts the clock signal based on the clock signal;
When a function call is detected, a counter value of the clock counter, a program counter value, and a function call control unit that outputs information on the jump destination or return destination address to the memory,
When a cache miss is detected, a counter value of the clock counter, a program counter value, and a cache miss control unit that outputs information of an access address to the memory;
A processor characterized by comprising:   2. A data control unit for transferring data stored in the memory to a data storage memory when detecting that the amount of data stored in the memory exceeds a predetermined threshold value. The processor described in. Having an interrupt controller,
3. The processor according to claim 1, wherein the transfer of the data stored in the memory is performed by the interrupt control unit.   4. A function setting unit for enabling or disabling functions of the function call control unit and the cache miss control unit based on a set signal, according to any one of claims 1 to 3. The processor described. A multiprocessor having a plurality of processors,
Each processor
Memory,
A clock counter that counts the clock signal based on the clock signal;
When a function call is detected, a counter value of the clock counter, a program counter value, and a function call control unit that outputs information on the jump destination or return destination address to the memory,
When a cache miss is detected, a counter value of the clock counter, a program counter value, and a cache miss control unit that outputs information of an access address to the memory;
A multiprocessor characterized by comprising:

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