JP2010009175A - Program performance estimation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it is impossible to estimate execution time relevant to a section in which a computer stops its operation and does not execute a command in estimation of program performance based on an operation simulation in which high cycle accuracy is not achieved. <P>SOLUTION: An estimation device 80 acquires a record of operations of the occurrence of wait and pseudo timer events during operation of a program, estimates operation time between the pseudo timer events from sections in which the wait does not occur by analyzing command execution, cache hit and bus access on the basis of specification information of SoC, and estimates the time for the occurrence of the wait on the basis of pseudo timer event information of the sections in which the wait occurs. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for estimating the performance of a program executed in various computer architectures.

  The performance of a program executed on a computer is mainly determined by the operation of the program and the specifications of the computer. Since the performance of a program running on a non-existing computer cannot be measured, some estimation means is required to grasp the change in program performance due to the specifications of the new computer.

  As such estimation means, means that use a hardware emulator or a cycle-precision software simulator is generally known. In this case, the specification of the computer can be set in a pseudo manner, the behavior according to the set operation clock of the computer is accurately simulated, and the total number of cycles required to execute the program is calculated.

  However, since a hardware emulator or a cycle-accurate software simulator generally operates at a low speed, there is a drawback that it takes time to estimate the performance of a practical program.

Based on the above background, there is disclosed a technique for calculating the total execution time of all instructions by performing a simulation with a high operation speed only by guaranteeing the order of instructions for CPU operation, not cycle accuracy. (For example, refer to Patent Document 1). The program, data initial value, execution start address, and execution end address are input, execution traces of all instructions of the CPU are performed, and hit rate simulation is performed using information on pipeline installation, cache method, and cache size. A technique is disclosed in which a stall penalty is added to the trace information obtained as a result to determine the number of execution clocks, and an increase in execution time due to a cache miss is estimated. In particular, an increase in execution time caused by an increase in cache miss caused by interrupt processing is taken into consideration and reflected in the estimation.
JP 2000-276381 A

  However, in general, during the operation of a program, the computer may stop operating, and may stop processing instructions being executed. For example, if a request is made to another device connected to the computer during the execution of the program and the processing of the other device is waited for, the computer itself performs a stop process and executes the instruction until some start trigger is generated. There is a case of stopping and waiting.

  In the conventional technique, the performance is estimated based on the execution trace of all instructions by computer simulation, and the execution time of the section in which the computer stops operating and the instruction is not executed during the operation of the program is estimated. I can't. In other words, there is a problem that it is impossible to estimate the performance of the entire program operation.

  The present invention solves the above-described conventional problems, and provides a program performance estimation device that enables performance estimation for a section in which the computer stops operating and enables estimation of performance for the entire operation of the program. Objective.

  In order to solve the above-described conventional problems, the program performance estimation apparatus of the present invention is a program performance estimation apparatus that estimates the operation performance of a program running on a computer, and includes information related to instruction execution and data access related to program operation, A program operation information input unit for acquiring information on occurrence of a wait and event occurrence, and a weight for determining and extracting a section in which a wait occurs and a section in which no wait occurs in the program operation information acquired from the program operation information input unit A generation section extracting unit; a program operation information of a section in which no weight is acquired, obtained from the wait generation section extraction unit; an instruction execution analysis unit for analyzing instruction execution and stall based on SoC specification information; and the wait generation section Program operation information obtained from the extraction unit Based on the SoC specification information, a bus access analysis unit for analyzing a cache hit and a bus access for a data access request, an instruction execution analysis result from the instruction execution analysis unit, and a bus access analysis result from the bus access analysis unit, Obtained event occurrence information from the instruction execution analysis unit and the bus access analysis unit, and obtained from the inter-event estimation unit and the inter-event estimation unit for estimating the operation time between events based on the analysis result and the stall cycle information A wait generation time estimation unit is provided that estimates a time at which a wait has occurred based on an operation time between events and program operation information of a section in which a wait occurred, acquired from the wait generation section extraction unit.

  With the above configuration, it is possible to discriminate between a wait generation interval and a non-wait generation interval, enable performance estimation of the wait generation interval using performance estimation between events based on the SoC specification, and estimate performance for the entire operation of the program. it can.

  According to the program performance estimation apparatus of the present invention, it is possible to estimate the performance of the section in which the computer stops operating, and to estimate the performance of the entire program operation.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of an information processing apparatus including a program performance estimation apparatus according to an embodiment of the present invention. The information processing apparatus 1000 can be used by a user as it is, but may be incorporated in various electric devices. An example of the information processing apparatus 1000 is typically a general-purpose computer such as a PC (Personal Computer). It may be a PDA (Personal Digital Assistance) or a mobile communication terminal such as a mobile phone.

  The information processing apparatus 1000 includes a CPU (Central Processing Unit) 1, a memory device 2, a communication device 34, an input device 40, a display device 45, a timer circuit 51, and an interrupt controller 55. These devices are connected to each other through a bus line 50. Further, the hard disk device 25 and the reading device 32 can be connected to the bus line 50 as necessary. The hard disk device 25, the reading device 32, the input device 40, and the display device 45 are connected to the bus line 50 through the interfaces 26, 35, 41, and 46, respectively.

  The CPU 1 may be composed of a single CPU or a plurality of CPUs. As an example, the information processing apparatus 1000 includes a plurality of CPUs 11, 12, 13,. The memory device 2 includes a ROM (Read Only Memory) 21 and a RAM (Random Access Memory) 22. The ROM 21 stores computer programs and data that define the operation of the CPU 1. The computer program and data can also be stored in the hard disk device 25. The CPU 1 executes processing specified by the computer program while writing the computer program and data stored in the ROM 21 or the hard disk device 25 to the RAM 22 as necessary. The RAM 22 also functions as a medium for temporarily storing data generated as the CPU 1 executes processing. The ROM 21 includes a nonvolatile memory and a storage medium that can be written like a flash ROM and can retain stored contents even when the power is turned off. The RAM 22 includes a volatile memory and a storage medium whose stored contents are not retained when the power is turned off.

  The hard disk device 25 is a device that writes and reads a computer program or data to a built-in hard disk (not shown). The reading device 32 is a device that reads a computer program or data recorded on a recording medium 31 (eg, CD, DVD, memory card, etc.). The communication device 34 is a device that exchanges a computer program or data between the outside and itself through a communication line 33 such as a telephone line, a network line, wireless communication, and infrared communication. The input device 40 is a device for inputting data or the like by a user operation, and is, for example, a keyboard arranged on a PDA, an input button arranged on a mobile phone, or a detachable mouse or keyboard. The display device 45 is a device that displays data, images, and the like on a screen and outputs data and the like by sound, and is, for example, an LCD (Liquid Crystal Display), a cathode ray tube, or a speaker.

  The timer circuit 51 is a device that outputs a timer interrupt signal at a constant cycle. The interrupt controller 55 is a device that relays an interrupt request signal sent from the timer circuit 51, the input device 40, the CPU 1, the communication device 34 as a network device, the hard disk device 25, the reading device 32, and the like to the CPU 1. Priorities are assigned to interrupt requests from each device. The interrupt controller 55 has a function of arbitrating requests according to priority when interrupts are simultaneously generated from a plurality of devices.

  As described above, the information processing apparatus 1000 is configured as a computer. The computer program can be supplied through a program recording medium 31 such as a ROM 21, a hard disk device 25, a flexible disk (not shown), a CD-ROM, or a transmission medium such as an electric communication line 33. For example, a computer program recorded on the program recording medium 31 (CD-ROM) can be read by connecting the reading device 32 to the information processing device 1000. In addition, the read computer program can be stored in the RAM 22 or the hard disk device 25.

  When a computer program is supplied from the ROM 21 as a program recording medium, the CPU 1 can execute processing according to the computer program by mounting the ROM 21 in the information processing apparatus 1000. A computer program supplied through a transmission medium such as the electric communication line 33 is received through the communication device 34 and stored in the RAM 22 or the hard disk device 25, for example. The transmission medium is not limited to a wired transmission medium, and may be a wireless transmission medium. The transmission medium includes not only a communication line but also a relay device that relays the communication line, such as a router.

  The entity of the program performance estimation function is stored in the memory device 2 or the hard disk device 25, and is executed in cooperation with the CPU 1, thereby realizing a program performance estimation device.

  FIG. 2 is a block diagram illustrating a configuration of the program pseudo operation apparatus 70 that outputs a program operation log. The program operation log is output to the program performance estimation device 80, and the program performance estimation device 80 performs performance estimation using the program operation log. The program pseudo-operation device 70 typically includes a simulator or emulator that simulates the operation of hardware of a computer, processor, or device, and a program that operates on the simulator or emulator. The program pseudo-operation device 70 is not particularly required to simulate an operation with cycle accuracy, and may be any device that simulates an instruction to be executed. Furthermore, the program pseudo-operation device 70 may be a computer, a processor, or a device itself that is actual hardware.

  The program pseudo operation device 70 operates the program in a pseudo manner, and outputs information necessary for the program performance estimation device 80 to estimate the operation performance of the program as a log that is an operation record. Note that the program operation log output by the program pseudo-operation device 70 does not necessarily need to be stored in the secondary storage device in the form of a file or the like, and may be in a format that can be passed to the program performance estimation device 80.

  With reference to FIG. 2, the configuration of the program pseudo-operation device 70 will be described.

  The instruction execution detection unit 201 detects the execution of an instruction executed on a processor such as a computer or a CPU when the program is operating. The instruction execution detection unit 201 can detect all instructions to be executed using a function of monitoring execution of instructions provided in a simulator or an emulator, for example. Although it is an instruction transferred to a processor such as a CPU, it is possible to detect an instruction that is not finally executed due to a condition.

  Further, the instruction execution detection unit 201 receives a trigger for detection start and end from the outside, and detects the execution of the instruction in a specified section from the start to the end.

  After detecting the execution of the instruction, the instruction execution detection unit 201 passes a program counter that is an execution address, an execution instruction code, an identifier corresponding to the operation mode of the processor, and the like to the program operation log output unit 206. The instruction execution detection unit 201 can also pass to the program operation log output unit 206 an identifier indicating that the operation log is related to instruction execution and the number of instruction executions in the section from the start to the end. Further, the instruction execution detection unit 201 can pass a program counter which is an instruction execution address to the instruction fetch request detection unit 202.

  The instruction execution detection unit 201 may have a function of changing an output after analyzing an execution instruction code and determining what instruction it is. For example, if the detected instruction is a branch instruction, the instruction execution detection unit 201 outputs an identifier indicating that the instruction is a branch instruction to the program operation log output unit 206 in order to reflect the estimated instruction in the program performance. Is possible. When the detected instruction is an instruction that requests access to an external storage device, such as a load instruction or a store instruction, the instruction execution detection unit 201 outputs an execution instruction code to the data access request detection unit 203. It becomes possible.

  The instruction fetch request detection unit 202 receives a program counter from the instruction execution rear part 201 and detects the occurrence of an instruction fetch request. That is, the instruction fetch request detection unit 202 considers that an instruction fetch request is generated when the program counter exceeds the instruction fetch unit length specified in advance, and records the instruction fetch request to the program operation log output unit 206. Notice.

  The data access request detection unit 203 analyzes the execution instruction code passed from the instruction execution detection unit 201 and notifies the program operation log output unit 206 of the analysis result. The analysis result here is an address for requesting data access, determination of read or write, and requested data size. In FIG. 2, the data access request detection unit 203 The execution instruction code is received from the instruction execution detection unit 201 and analyzed. As another configuration, the data access request detection unit 203 uses a function of monitoring data access, which is a function of a simulator or emulator, to directly detect a data access request and acquire information related to the data access request. Also good.

  The wait generation monitoring unit 204 receives information such as a program counter or an execution instruction code that is an execution address from the instruction execution detection unit 201, and determines whether it is a timing to stop execution of the instruction. If the wait generation monitoring unit 204 determines that it is time to stop, the wait generation monitoring unit 204 notifies the program operation log output unit 206 of information indicating that execution of the instruction has been stopped. Note that the wait generation monitoring unit 204 can determine whether or not the instruction is to stop the execution of the instruction using the analysis result of the execution instruction code. In addition, it is possible to determine that the call is a function call or module execution for waiting for another device or apparatus using the received program counter. This is because the computer or processor stops executing instructions and enters a wait state to execute a specific function or module that is executed when executing a specific instruction or during the operation of a program.

  The pseudo timer recording unit 205 operates a pseudo timer, and notifies the program operation log output unit 206 of time information under the pseudo environment of the program pseudo operation device 70. For example, a timer circuit connected to a computer on which the program pseudo-operation device 70 itself operates can be used. This timer circuit generates an event at a constant time interval in the real world, thereby generating an event at a pseudo time interval in the world on the program pseudo-operation device 70. When receiving the pseudo timer event, the pseudo timer recording unit 205 notifies the program operation log output unit 206 of the occurrence of the pseudo timer event. Further, when a timer event occurs, the time stamp at that time can be notified to the program operation log output unit 206.

  The program operation log output unit 206 receives information from the instruction execution detection unit 201, the instruction fetch request detection unit 202, the data access request detection unit 203, the wait generation monitoring unit 204, and the pseudo timer recording unit 205, and generates a program operation log. . Further, the program operation log output unit 206 outputs the generated program operation log to the program performance estimation device 80. It is assumed that the program operation log has a format in which the order relationship in which the received information is generated can be grasped.

  With the above configuration, the program pseudo-operation device 70 of the present invention uses the information acquired from the wait generation monitoring unit 204 and the pseudo-timer recording unit 205 to obtain information necessary for estimating the execution stop time of an instruction. Can be output as a log. The program performance estimation device 80 that has received this program operation log enables performance estimation not only for the section in which the instruction is executed but also for the section in which the computer stops operating. This makes it possible to estimate the performance for the entire program operation. This section in which the computer is stopped includes a time for requesting processing to another device connected to the computer during execution of the program and waiting for processing of the other device to be completed. Further, it includes a time for the computer itself to stop processing and to stop execution of the instruction and wait until an activation trigger is generated.

  Further, since the program pseudo-operation device 70 does not simulate and operate a program with cycle accuracy, time information in the pseudo environment of the program pseudo-operation device 70 is required. Therefore, the pseudo timer recording unit 205 operates a pseudo timer and notifies the program operation log output unit 206 of the time information under the pseudo environment of the program pseudo operation device 70, so that the pseudo time information is stored in the program operation log. Can be included.

  FIG. 3 is an example of information recorded in the program operation log output from the program pseudo-operation device 70 and input to the program performance estimation device 80. In FIG. 3, one log information is shown in one line, and the information 90 described in the program operation log has five log information (251 to 255) arranged from the top according to the order of occurrence. Each log information includes an identifier and auxiliary information.

  The identifier is information for identifying the type of operation log. If it can be identified, it may be identified using other information included in the auxiliary information. For example, there is no problem even if the information related to the instruction fetch request (252 in FIG. 3) is the information of the instruction fetch request by the access type.

  The auxiliary information requires different information depending on the identifier.

  The log information 251 is an example of information passed from the instruction execution detection unit 201 to the program operation log output unit 206. The program counter value and execution instruction type are written. As the execution instruction type, identification information for specifying an instruction after the execution instruction code is analyzed may be recorded, or the execution instruction code may be recorded without being analyzed.

  The log information 252 is an example of information passed from the instruction fetch request detection unit 202 to the program operation log output unit 206. The address requesting the instruction fetch, the access type indicating the instruction fetch, and the size requested by the instruction fetch are described.

  The log information 253 is an example of information passed from the data access request detection unit 203 to the program operation log output unit 206. The address requesting data access, the access type for determining whether the data access request is read (read access) or write (write access), and the size requested for data access are described. .

  The log information 254 is an example of information passed from the wait occurrence monitoring unit 204 to the program operation log output unit 206. A wait occurrence event occurrence record indicating that a wait to stop execution of an instruction has occurred, and a wait type are recorded. The wait type indicates whether the program has put the computer or processor into the stop mode, or what request is issued to another device or device and is waiting.

  The log information 255 is an example of information passed from the pseudo timer recording unit 205 to the program operation log output unit 206. A pseudo timer event occurrence record indicating that an event from the pseudo timer has occurred, and a time stamp indicating the time when the event from the pseudo timer has occurred are recorded.

  The information 90 recorded in the program operation log shown in FIG. 3 is an example, and there is no problem in the operation of the program performance estimation apparatus 80 even if equivalent information is processed into another format.

  In practice, the program operation log is recorded in a format that can identify the order relationship in which a series of information recorded as program operations has occurred. In the simplest case, the program operation information only needs to be written in the time sequence of the order of occurrence.

  FIG. 4 is a block diagram showing the configuration of the program performance estimation apparatus 80 in the embodiment of the present invention.

  The program performance estimation device 80 includes a program operation log input unit 301, a wait generation interval extraction unit 303, a CPU bus specification input unit, an instruction execution analysis unit 305, a bus access analysis unit 306, a stall cycle management unit 307, a pseudo timer time estimation unit. 308, a normal processing time estimation unit 309, a weight generation time estimation unit 310, and an estimated time presentation unit 311.

  The program operation log input unit 301 receives the program operation log from the program pseudo operation device 70 and outputs the received program operation log to the wait generation interval extraction unit 303.

  The wait generation interval extraction unit 303 determines whether each piece of log information included in the program operation log is a program operation occurring in the wait generation interval. When it is determined that the program operation has occurred in the wait occurrence interval, the wait occurrence interval extraction unit 303 notifies the corresponding log information to the wait occurrence time estimation unit 310. When it is determined that the program operation has occurred in the normal operation section where no wait has occurred, the wait generation section extraction unit 303 notifies the corresponding log information to the instruction execution analysis unit 305 and the bus access analysis unit 306.

  The CPU bus specification input unit 304 reads specifications related to a computer, a processor, or a CPU that is assumed to operate a program to be estimated, various cache architectures, and bus architecture specifications, and reads the information into an instruction execution analysis unit 305, a bus The access analysis unit 306 and the stall cycle management unit 307 are notified. That is, the CPU bus specification input unit 304 reads the SoC specification information to be estimated, extracts information necessary for each processing unit (305, 306, 307), and performs notification.

  The instruction execution analysis unit 305, the bus access analysis unit 306, and the stall cycle management unit 307 operate by acquiring CPU and cache architecture specification information necessary for analysis from the CPU bus specification input unit 304 described above.

  The stall cycle management unit 307 manages and holds CPU related information, cache related stall cycle information, external bus related stall cycle information, and the like as stall cycle management information. The stall cycle management unit 307 notifies the pseudo timer time estimation unit 308 and the normal processing time estimation unit 309 of the number of stalls used for estimation based on the specification acquired from the CPU bus specification input unit 304.

  The instruction execution analysis unit 305 acquires log information from the wait generation interval extraction unit 303 and CPU specification information from the CPU bus specification input unit 304, and analyzes a program operation related to instruction execution. Specifically, the number of instruction executions, the number of branch instruction executions, and the number of stall cycles due to pipeline hazards are calculated. Note that the log information acquired by the instruction execution analysis unit 305 is, for example, the log information 251 in FIG. 3 and obtains information on a program counter value and an execution instruction code. In addition, the instruction execution analysis unit 305 associates the calculated value with the pseudo timer event using the pseudo timer event occurrence record included in the acquired log information, and normal processing time estimation unit 309 and pseudo timer time estimation unit 308. Notify the analysis information.

  The bus access analysis unit 306 acquires log information from the wait generation interval extraction unit 303 and cache specification information from the CPU bus specification input unit 304, and performs an analysis related to instruction fetch and data access. Specifically, the number of cache hits is calculated. The log information acquired by the bus access analysis unit 306 is, for example, the log information 252 and the log information 253 in FIG. Further, the bus access analysis unit 306 associates the calculated value with the pseudo timer event using the pseudo timer event occurrence record included in the acquired log information, and normal processing time estimation unit 309 and pseudo timer time estimation unit 308. Notify the analysis information.

  The pseudo timer time estimation unit 308 acquires analysis information from the instruction execution analysis unit 305 and the bus access analysis unit, acquires information on the number of stalls from the stall cycle management unit 307, and calculates the program operation time of the pseudo timer event interval. . Further, the pseudo timer time estimation unit 308 associates the calculated program operation time with the target pseudo timer event, and notifies the wait generation time estimation unit 310 of it.

  The wait generation time estimation unit 310 estimates an operation time when the computer waits for processing of another device or when the execution of an instruction is stopped and waits until a certain activation trigger is generated.

  The wait generation time estimation unit 310 acquires information on the program operation log determined by the wait generation interval extraction unit 303 as a program operation when a wait occurs. The wait occurrence time estimation unit 310 calculates the number of times a pseudo timer event has occurred from the information of the program operation log.

  Further, the wait generation time estimation unit 310 acquires the operation time calculated by the pseudo timer time estimation unit 308 for each pseudo timer event interval, and the pseudo timer event interval per pseudo timer event interval is calculated based on the operation time. Calculate the operating time. Typically, the average value, median value, or mode value of the operation time of all the pseudo timer event intervals may be determined as the operation time per pseudo timer event interval, and distribution bias is considered. After removing some percentage of the upper and lower samples, the average value or the median value may be determined as the operation time per pseudo timer event interval.

  The wait generation time estimation unit 310 calculates the program operation acquired from the wait generation interval extraction unit 303 by the product of the calculated operation time per pseudo timer event interval and the number of occurrences of the pseudo timer event calculated based on the program operation log. The estimated time presenting unit 311 notifies the estimated time presenting unit 311 of the time as a wait occurrence time. As a result, it is possible to estimate the stop time for the processing section in which the computer is stopped due to the occurrence of waiting.

  The normal processing time estimation unit 309 acquires program operation analysis information related to instruction execution, such as information on the number of executions at the time of instruction, the number of branch instructions, and the number of stalls, from the instruction execution analysis unit 305, and The analysis information related to instruction fetch and data access such as external bus access information is acquired, the entire program operation time of the analysis information is calculated, and the estimated time presentation unit 311 is notified.

  The normal processing time estimation unit 309 performs the same operation as the pseudo timer time estimation unit 308. The difference in operation is that the pseudo timer time estimation unit 308 calculates the operation time between pseudo timer events, whereas the normal processing time estimation unit 309 obtains from the instruction execution analysis unit 305 and the bus access analysis unit 306. The operation time is calculated for the entire analysis information of the program operation. The normal processing time estimation unit 309 calculates the CPU execution time, the time required for cache hits at each level, and the external bus access time for the entire analysis information of the program operation, and the program operates without waiting for the total. It is determined that it is the normal processing time, and the estimated time presenting unit 311 is notified.

  Alternatively, the normal processing time estimation unit 309 can calculate the operation time between designated timer events instead of the entire analysis information of the program operation. For example, the start and end of the section for estimating the operation time is specified by the time stamp of the pseudo timer, the normal processing time is calculated in the same manner as described above, and the estimated time presentation unit 311 is notified. In this case, the pseudo timer time estimation unit 308 calculates the number of occurrences of the pseudo timer event existing in the time stamp interval indicating start and end, and calculates the specified start by the product of the operation time per pseudo timer event interval. The wait generation time in the section from the end to the end is estimated and notified to the estimated time presentation unit 311.

  The estimated time presentation unit 311 adds the normal processing time in which the program acquired from the normal processing time estimation unit 309 is operating and the wait generation time acquired from the wait generation time estimation unit 310 to obtain from the program pseudo-operation device 70. In the entire program operation log, the program operation time including the time during which the computer is stopped due to waiting can be output. This program operation time is an estimated program performance value.

  As described above, the program performance estimation apparatus 80 according to the present invention enables estimation not only for a section in which an instruction is executed but also for a section in which the computer stops operating. Thereby, in the estimation of the program performance based on the operation simulation with no cycle accuracy, the performance of the entire program operation can be estimated.

  FIG. 5 shows a processing flow of the weight generation interval extraction unit 303. The wait generation interval extraction unit 303 receives the program operation log from the program operation log input unit 301, and starts processing by confirming the generation record of the first pseudo timer event.

  The wait generation interval extraction unit 303 checks the program operation log existing in the interval from the recording of the current pseudo timer event to the recording of the next generated pseudo timer event (S321). Confirming the program operation log means confirming the contents of the target log information.

  The wait occurrence interval extraction unit 303 determines whether log information of the wait occurrence event exists in the current pseudo timer event interval (S322).

  When log information of a wait occurrence event exists (Yes in S322), the wait occurrence interval extraction unit 303 determines that the program operation in the current pseudo timer event interval is a program operation when a wait occurs. Then, the corresponding log information is notified to the wait occurrence time estimation unit 310 (S325).

  On the other hand, when there is no record of the wait occurrence event (No in S322), the wait occurrence interval extraction unit 303 determines whether there is log information of another program operation in the interval of the current pseudo timer event ( S323). It is to be noted that log information such as a program counter value, instruction fetch, and data access is determined. When log information of other program operations exists (Yes in S323), the wait generation interval extraction unit 303 notifies the instruction execution analysis unit 305 and the bus access analysis unit 306 of the log information of the current pseudo timer event interval. (S324).

  If there is no log information of other program operations (No in S323), the wait generation interval extraction unit 303 determines that the program operation in the current pseudo timer event interval is a program operation when a wait occurs. To do. Then, the corresponding log information is notified to the wait occurrence time estimation unit 310 (S325).

  Regarding the log information of the program operation that has occurred between the beginning of the program operation log and the recording of the first pseudo timer event, the wait generation time estimation unit 310 is in a normal operation section in which no wait has occurred. to decide. Then, the log information of the program operation in this section may be notified to the instruction execution analysis unit 305 and the bus access analysis unit 306. Further, with respect to the log information of the program operation that has occurred from the last pseudo timer event recording to the end of the program operation log, the wait generation time estimation unit 310 determines that the normal operation section in which no wait has occurred. To do. Then, information on the program operation log in this section may be passed to the instruction execution analysis unit 305 and the bus access analysis unit 306.

  FIG. 6 shows an example of information read by the CPU bus specification input unit 304. Reference numeral 401 in FIG. 6 collectively describes information on the specifications related to the CPU. Among them, the clock frequency (402), the execution parallelism (403), the branch prediction method (404), and the presence / absence of a bypass circuit (405) are included. Information etc. are included.

  The clock frequency 402 is a value indicating how much a clock, which is the minimum unit of operation of the CPU, is supplied per unit time. Typically, the value of the CPU clock frequency is based on the unit of MHz or GHz. It is written.

  The execution parallelism 403 can indicate how much the CPU is assumed to be able to execute instructions in parallel. For example, the execution count of instructions per clock may be averaged. Accordingly, information on whether or not it can be executed in parallel may be written. When writing information about the degree of execution parallelism according to an instruction, it is only necessary to describe information that can determine what instruction can be executed in parallel based on the execution instruction code.

  The branch prediction method 404 indicates information related to the branch prediction function provided in the CPU, and indicates the presence / absence of the branch prediction function or the type of the branch prediction method. The bypass circuit presence / absence 405 describes information on the presence / absence of a bypass circuit that bypasses and sends data to the preceding stage when a CPU pipeline hazard occurs.

  FIG. 7 shows an example of information read by the CPU bus specification input unit 304. Reference numeral 451 in FIG. 7 collectively describes cache architecture specification information, including presence / absence (452), method (453), number of ways (454), number of blocks (455), and line size (456). , Information about the replacement algorithm (457), dirty bit management (458), and the like.

  A cache is a small-capacity and high-speed storage medium that is interposed between an external device that is a storage medium, and a plurality of stages can be mounted. For this reason, it is possible to read information on a plurality of stages of cache architecture specifications according to the cache configuration assumed in estimating the program performance. Further, assuming a cache configuration of a plurality of stages, not only the cache architecture specification of level 1 but also the information of the cache architecture specification can be similarly read for the number of stages of level 2, level 3, or more.

  Information indicating whether or not to use the cache of the level is written in the cache use / non-use 452.

  The cache method 453 is information indicating whether it is an integrated (unified) cache that handles both instruction fetch and data access or a separate (Harvard) cache that handles instruction fetch and data access separately. It is written.

  The number of ways 454, the number of blocks 455, and the line size 456 are parameters that determine the total capacity of the cache. A reference size for determining whether to hit or miss the cache is a line size 456, and is typically written in units of bytes. The number of blocks 455 is a value corresponding to the total number of line sizes per way, where one line size is 1 block. The number of ways 454 indicates the number of caches of line size × number of blocks that can determine in parallel whether to hit or miss the cache.

  The replacement algorithm 457 indicates which replacement algorithm such as LRU or random replacement is used. The dirty bit management 458 indicates in which unit the dirty bit is managed in the cache line when writing to the cache line occurs.

  Further, the CPU bus specification input unit 304 can read information not only about the CPU specification and the cache specification, but also about the type of the connected bus and the bus specification such as the bus width or burst length.

  FIG. 8 shows an example of stall cycle management information managed by the stall cycle management unit 307. Reference numeral 471 in FIG. 8 collectively describes the stall cycle management information, which includes CPU related information, cache related stall cycle information, external bus related stall cycle information, and the like.

  The stall cycle management unit 307 acquires the value of the clock frequency 402 from the CPU bus specification input unit 304 and manages it as the clock frequency 472. CPI 473 indicates the number of cycles in which the CPU operates for one instruction. Although a constant value may be given in advance, the stall cycle management unit 307 can change the stall management information notified to the pseudo timer time estimation unit 308 and the normal processing time estimation unit 309 according to conditions. For example, the stall cycle management unit 307 manages the CPI value according to two types of CPUs, CPU-A and CPU-B. The stall cycle management unit 307 selects a CPI value according to the CPU type indicated by the CPU specification execution parallelism 403 read by the CPU bus specification input unit 304, and sends it to the pseudo timer time estimation unit 308 and the normal processing time estimation unit 309. It is possible to notify.

  Further, regarding other stall cycle management information, the stall cycle management unit 307 can change the stall cycle management information according to the specification conditions acquired from the CPU bus specification input unit 304. Since the CPU is generally executed in a pipeline, when a branch instruction is executed and a jump is made to other than the subsequent address, the instruction at the subsequent address that has been loaded in the pipeline until then is wasted. Therefore, the branch penalty 474 is added as the number of stalls. The stall cycle management unit 307 also manages a branch penalty for each type of branch penalty 474 when there is no branch prediction function or when there is a branch prediction function. When the branch prediction method information is acquired from the CPU specification information of the CPU bus specification input unit 304, the branch penalty information is notified to the pseudo timer time estimation unit 308 and the normal processing time estimation unit 309 accordingly.

  The stall cycle management unit 307 also manages the number of stalls in the register contention stall 475 according to the presence or absence of the CPU bypass circuit. In accordance with the bypass circuit presence / absence information 405 acquired from the CPU bus specification input unit 304, the stall number information is notified to the pseudo timer time estimation unit 308 and the normal processing time estimation unit 309.

  The stall cycle management unit 307 also manages cache-related stall information. In the reference clock frequency 477, a frequency value indicating which cycle base the cache-related stall cycle number is written is managed. A cache-related CPU-related clock frequency 472 may be used.

  The stall cycle management unit 307 can manage the number of stalls at the time of a cache hit according to the level of the cache, such as the stall 478 at the time of level 1 cache hit or the stall 479 at the time of level 2 cache hit. It is also possible to manage as the number of cache levels increases.

  Also, stall information at the time of level 1 cache hit can be managed according to the access conditions. For example, the stall information may be managed separately for the case of read access and the case of write access.

  The stall cycle management unit 307 further manages stall information related to the external bus. The reference clock frequency 480 is managed as a frequency value indicating on which cycle basis the number of stall cycles related to the external bus is written. Like the stall 481 of the device 1 or the stall 482 of the device 2, the stall information related to the external bus manages the stall information of the external device connected to the computer.

  The stall cycle management unit 307 can manage stall information according to conditions for each device. For example, if the cache line size is changed, the transfer size changes, and the number of stall cycles changes accordingly. Also, if the bus width or burst length is changed, the transfer size changes at one time, and the number of stall cycles changes accordingly. Therefore, various stall information can be managed according to the stall cycle cache specification or the bus specification, and information on the appropriate number of stalls can be notified to the pseudo timer time estimation unit 308 and the normal processing time estimation unit 309.

  FIG. 9 shows a processing flow of the instruction execution analysis unit 305.

  The instruction execution analysis unit 305 acquires information on the execution instruction code from the wait generation interval extraction unit 303 (S501), and acquires CPU specification information from the CPU bus specification input unit 304 (S502).

  The instruction execution analysis unit 305 selects the execution instruction code of the first instruction in the order of execution (S503).

  The instruction execution analysis unit 305 analyzes the current execution instruction code and the previously executed execution instruction code, and determines whether the instruction is a designated instruction (S504). This determination is made when the CPU specification information acquired in step S502 includes information on the instruction execution parallelism, and there is information that can determine what instruction can be executed in parallel based on the execution instruction code. Is possible.

  If the instruction cannot be executed in parallel with the previously executed instruction (No in S504), the instruction execution analysis unit 305 determines that the number of cycles necessary to execute the instruction is consumed. The instruction execution analysis unit 305 adds the value of the number of instruction executions to be managed (S505), and proceeds to step S506.

  If the instruction can be executed in parallel with the previously executed instruction (Yes in S504), the instruction execution analysis unit 305 analyzes the current execution instruction code and determines whether the instruction is a branch instruction (S506). As a result, if it is determined that the current instruction is a branch instruction (Yes in S506), the instruction execution analysis unit 305 adds the value of the number of branch instructions to be managed (S507), and proceeds to step S508.

  If it is determined that the current instruction is not a branch instruction (No in S506), the instruction execution analysis unit 305 analyzes the current execution instruction code and a stall occurs based on the previously executed instruction and data dependency It is determined whether or not to perform (S508). As a result, if it is determined that a stall occurs (Yes in S508), the instruction execution analysis unit 305 adds the value of the number of stalls to be managed (S509), and proceeds to step S510.

  If it is determined that a stall does not occur (No in S508), the instruction execution analysis unit 305 determines whether the current instruction is the last execution instruction code (S510). When it is determined that it is not the last execution instruction code (No in S510), the execution instruction code to be executed next is targeted (S511), and the process returns to Step S504 and is repeated. If it is the last execution instruction code (Yes in S510), the instruction execution analysis unit 305 notifies the normal time estimation unit 302 and the pseudo timer time estimation unit 308 of the calculated instruction execution count, branch instruction count, and stall count. (S512).

  FIG. 10 shows a processing flow of the bus access analysis unit 306.

  The bus access analysis unit 306 acquires information related to instruction fetch and data access from the wait generation interval extraction unit 303 (S531), and acquires cache specification information from the CPU bus specification input unit 304 (S532). The bus access analysis unit 306 searches the acquired cache specification information for cache specification information that is designated as used in order from the lowest level cache, and acquires the minimum level of cache specification information that is designated as used. (S533).

  The wait generation interval extraction unit 303 targets the operation log information related to all instruction fetches and the operation log information related to data access acquired in S531 (S534). Next, it is determined whether the cache method described in the cache specification information acquired in S533 is a unified (unified) cache or a separated (Harvard) cache (S535).

  When the cache method is the integrated type (Yes in S535), if the operation log information related to instruction fetch and data access targeted in S534 is separated, the order relation is merged (S536). Thereafter, a cache simulation is performed based on the acquired cache specification information, the number of cache hits is calculated (S537), and the process proceeds to step S540. The cache specification information includes the number of cache ways, the number of blocks, the line size, a replacement algorithm, dirty bit management, and the like.

  If the cache method is not the integrated type (No in S535), if the operation log information related to instruction fetch and data access targeted in S534 is merged, the instruction fetch and data access are separated (S538). Here, the separation is performed in a format that does not impair the order relationship. Thereafter, cache simulation is performed based on the cache specification information of the instruction cache and the data cache, the number of cache hits is calculated (S539), and the process proceeds to step S540.

  The bus access analysis unit 306 searches for next level cache specification information designated as used and determines whether it exists (S540). If the next cache specification information exists (Yes in S540), the cache usage information is acquired (S541). Thereafter, the access that has been missed by the cache simulation in step S534 or S539 is targeted (S542), and the process proceeds to step S535.

  If the next cache specification information does not exist (No in S540), the bus access analysis unit 306 performs cache simulation, the number of cache hits of each level cache, and finally cache misses and exits to the external bus. The access information is notified to the normal processing time estimation unit 309 and the pseudo timer time estimation unit 308 (S543).

  FIG. 11 shows a processing flow of the pseudo timer time estimation unit 308.

  The pseudo timer time estimation unit 308 obtains program operation analysis information related to instruction execution from the instruction execution analysis unit 305, and obtains instruction fetch and data access analysis information from the bus access analysis unit (S601). Note that the analysis information relating to instruction execution includes information on the number of executions at the time of instruction, the number of branch instructions, the number of stalls, and the like. The analysis information related to instruction fetch and data access includes the number of cache hits and external bus access information. This analysis information includes information regarding the recording of the pseudo timer event output from the instruction execution analysis unit 305 and the bus access analysis unit 306.

  The pseudo timer time estimation unit 308 acquires stall cycle management information from the stall cycle management unit 307 (S602).

  The pseudo timer time estimation unit 308 selects the first record among the pseudo timer event records included in the analysis information acquired from the instruction execution analysis unit 305 and the bus access analysis unit 306, and starts processing (S603). Typically, pseudo timer events are recorded and analysis information is processed in time series. However, if it is managed which analysis information between pseudo timer events is processed and analysis information between all pseudo timer events is targeted, it is not necessary to process in time series.

  Next, the pseudo timer time estimation unit 308 detects a pseudo timer event that occurs next from the record of the currently selected pseudo timer event, and targets analysis information of a section up to the pseudo timer event ( S604).

  The pseudo timer time estimation unit 308 calculates the CPU execution time out of the program operation time based on the analysis information acquired from the instruction execution analysis unit 305 and the stall cycle management information acquired from the stall cycle management unit 307 (S605). . Note that the analysis information acquired from the instruction execution analysis unit 305 includes information on the number of instruction executions, the number of branch instructions, the number of stalls, and the like. The stall cycle management information includes CPU clock frequency, CPI value, branch penalty, register contention stall information, and the like. Typically, the instruction execution time is calculated by accumulating the instruction execution count and the CPI value and dividing the result by the clock frequency. In addition, the time due to the branch penalty is calculated by adding up the number of branch instructions and the number of cycles of the branch penalty and dividing by the clock frequency. Further, the number of stalls and the number of register contention stalls are integrated and divided by the clock frequency to calculate the pipeline stall time. By summing these, the CPU execution time of the target section can be calculated.

  Based on the analysis information acquired from the bus access analysis unit 306 and the stall cycle management information acquired from the stall cycle management unit 307, the pseudo timer time estimation unit 308 calculates the cache hit time of each level in the program operation time. (S606). The analysis information acquired from the bus access analysis unit 306 is the number of cache hits at each level. Further, the stall cycle management information acquired from the stall cycle management unit 307 includes information on a reference clock frequency and a stall at the time of a cache hit. Typically, the number of cache hits at each level and the number of stall cycles at the time of the cache hit at each level are integrated and divided by the reference clock frequency to calculate the time required for the cache hit at each level in the target section.

  The pseudo timer time estimation unit 308 calculates the access time of each device based on the analysis information acquired from the bus access analysis unit 306 and the stall cycle management information acquired from the stall cycle management unit 307 (S607). Note that the analysis information acquired from the bus access analysis unit 306 is external bus access information. The stall cycle management information acquired from the stall cycle management unit 307 includes a reference clock frequency and device stall information. Typically, as an external bus access information, it is determined which address each access request is an access request to, and which device is accessed according to the address space where each device is located. To do. Next, the stall cycle management information of the device to be accessed is referred to, and the number of stall cycles related to the access request is determined. The pseudo timer time estimation unit 308 determines which device is an access to all external bus accesses included in the currently analyzed analysis information. The pseudo timer time estimation unit 308 calculates the external bus access time of the target section by dividing the sum by the reference clock frequency using the total number of stall cycles of the device to be accessed as the number of cycles required for external bus access.

  The pseudo timer time estimation unit 308 calculates the operation time by adding the CPU execution time calculated in step S605, the time required for each level of cache hit calculated in step S606, and the external bus access time calculated in step S606. . Thereafter, the pseudo timer time estimation unit 308 associates the calculated operation time with, for example, a time stamp and notifies the wait generation time estimation unit 310 so that the pseudo timer event can be uniquely identified as a record of the currently targeted pseudo timer event (S609). ).

  As described above, the program performance estimation apparatus according to the present invention makes it possible to estimate not only a section in which an instruction is being executed but also a section in which the computer has stopped operating. Thereby, in the estimation of the program performance based on the operation simulation with no cycle accuracy, the performance of the entire program operation can be estimated.

  The above description is merely an example of the present invention in all respects, and is not intended to limit the scope thereof. It goes without saying that various improvements and modifications can be made without departing from the scope of the present invention.

  The program performance estimation apparatus according to the present invention has a function of estimating a section in which the computer stops operating, and is useful as an information processing apparatus. Further, it is useful as a development tool for embedded devices such as information devices, AV devices, communication devices, and home appliances.

The figure which shows the structure of the information processing apparatus provided with the program performance estimation apparatus in embodiment of this invention The block diagram which shows the structure of the program pseudo-operation apparatus in embodiment of this invention The figure which shows an example of the information described in the program operation log in embodiment of this invention The block diagram which shows the structure of the program performance estimation apparatus in embodiment of this invention The flowchart which shows an example of the operation | movement procedure of the weight generation | occurrence | production area extraction part in embodiment of this invention The figure which shows an example of the CPU specification information which the CPU bus specification input part in embodiment of this invention reads Explanatory drawing which shows an example of the cache specification information which the CPU bus specification input part in embodiment of this invention reads The figure which shows an example of the stall cycle management information which the stall cycle management part in embodiment of this invention manages The flowchart which shows an example of the operation | movement procedure of the instruction execution analysis part in embodiment of this invention The flowchart which shows an example of the operation | movement procedure of the bus access analysis part in embodiment of this invention The flowchart which shows an example of the operation | movement procedure of the pseudo timer time estimation part in embodiment of this invention

Explanation of symbols

1, 11, 12, 13 CPU
2 Memory device 10 Program performance estimation device 21 ROM
22 RAM
Reference Signs List 25 hard disk device 26, 35, 41, 46 interface 31 recording medium 32 reading device 33 electric communication line 34 communication device 40 input device 45 display device 50 bus line 51 timer circuit 55 interrupt controller 70 program simulation operation device 80 program performance estimation device 201 Instruction execution detection unit 202 Instruction fetch request detection unit 203 Data access request detection unit 204 Wait generation monitoring unit 205 Pseudo timer recording unit 206 Program operation log output unit 301 Program operation log input unit 303 Wait generation period extraction unit 304 CPU / bus specification input Section 305 Instruction execution analysis section 306 Bus access analysis section 307 Stall cycle management section 308 Pseudo timer time estimation section 309 Normal processing time estimation section 310 Wait Occurrence time estimation part 311 Estimated time presentation part

Claims (4)

A program performance estimation device for estimating the performance of a program running on a computer,
Information on instruction execution and data access related to program operation, program operation information input unit for acquiring information on occurrence of wait and event occurrence,
Of the program operation information acquired from the program operation information input unit, a weight generation interval extraction unit that determines and extracts an interval in which a weight is generated and an interval in which no weight is generated;
An instruction execution analysis unit for analyzing instruction execution and stall based on program operation information of a section in which no weight is acquired, obtained from the wait generation section extraction unit, and SoC specification information;
A bus access analysis unit for analyzing a cache hit and a bus access for a data access request based on the program operation information acquired from the wait generation section extraction unit and the SoC specification information;
An instruction execution analysis result is acquired from the instruction execution analysis unit and a bus access analysis result is acquired from the bus access analysis unit, event occurrence information is acquired from the instruction execution analysis unit and the bus access analysis unit, and the analysis result and stall An inter-event estimator that estimates the operating time between events based on cycle information;
A wait generation time estimation unit for estimating a time at which a weight is generated based on an operation time between events acquired from the inter-event estimation unit and a program operation information of a section in which a weight is acquired from the wait generation interval extraction unit; An apparatus for estimating program performance. A program performance estimation method for estimating the performance of a program running on a computer,
Program operation information input step for obtaining information on instruction execution and data access related to program operation, information on occurrence of wait and event occurrence,
Of the program operation information acquired from the program operation information input unit, a weight generation interval extraction step for discriminating and extracting an interval in which a weight is generated and an interval in which no weight is generated;
An instruction execution analysis step for analyzing instruction execution and stall based on program operation information in a section where no weight is acquired, obtained from the wait generation section extraction unit, and SoC specification information;
A bus access analyzing step of analyzing a cache hit and a bus access for a data access request based on the program operation information acquired from the wait generation interval extracting unit and the SoC specification information; an instruction execution analysis result from the instruction execution analyzing unit; An event that acquires a bus access analysis result from the bus access analysis unit, acquires event occurrence information from the instruction execution analysis unit and the bus access analysis unit, and estimates an operation time between events based on the analysis result and stall cycle information An interim estimation step;
A wait generation time estimation step for estimating a time at which a wait occurs based on the operation time between events acquired from the inter-event estimation unit and the program operation information of the interval in which the wait acquired from the wait generation interval extraction unit is generated. A program performance estimation method characterized by comprising: A program for estimating the performance of a program running on a computer,
Program operation information input step for obtaining information on instruction execution and data access related to program operation, information on occurrence of wait and event occurrence,
Of the program operation information acquired from the program operation information input unit, a weight generation interval extraction step for discriminating and extracting an interval in which a weight is generated and an interval in which no weight is generated;
An instruction execution analysis step for analyzing instruction execution and stall based on program operation information in a section where no weight is acquired, obtained from the wait generation section extraction unit, and SoC specification information;
A bus access analyzing step of analyzing a cache hit and a bus access for a data access request based on the program operation information acquired from the wait generation interval extracting unit and the SoC specification information; an instruction execution analysis result from the instruction execution analyzing unit; An event that acquires a bus access analysis result from the bus access analysis unit, acquires event occurrence information from the instruction execution analysis unit and the bus access analysis unit, and estimates an operation time between events based on the analysis result and stall cycle information An interim estimation step;
A wait generation time estimation step for estimating a time at which a wait occurs based on the operation time between events acquired from the inter-event estimation unit and the program operation information of the interval in which the wait acquired from the wait generation interval extraction unit is generated. A program for estimating program performance, comprising: A medium in which a program performance estimation program for estimating the performance of a program running on a computer is recorded,
Program operation information input step for obtaining information on instruction execution and data access related to program operation, information on occurrence of wait and event occurrence,
Of the program operation information acquired from the program operation information input unit, a weight generation interval extraction step for discriminating and extracting an interval in which a weight is generated and an interval in which no weight is generated;
An instruction execution analysis step for analyzing instruction execution and stall based on program operation information in a section where no weight is acquired, obtained from the wait generation section extraction unit, and SoC specification information;
A bus access analyzing step of analyzing a cache hit and a bus access for a data access request based on the program operation information acquired from the wait generation interval extracting unit and the SoC specification information; an instruction execution analysis result from the instruction execution analyzing unit; An event that acquires a bus access analysis result from the bus access analysis unit, acquires event occurrence information from the instruction execution analysis unit and the bus access analysis unit, and estimates an operation time between events based on the analysis result and stall cycle information An interim estimation step;
A wait generation time estimation step for estimating a time at which a wait occurs based on the operation time between events acquired from the inter-event estimation unit and the program operation information of the interval in which the wait acquired from the wait generation interval extraction unit is generated. A recording medium on which a program for estimating program performance is recorded.

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