JP2010128681A - Timestamp acquisition circuit and timestamp acquisition method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the capacity of a trace memory cannot be increased, and that the circuit scale of a chip to be traced is increased. <P>SOLUTION: The timestamp acquisition circuit includes: a time stamp counter; an OVF flag; an OVF counter; and a trace memory write control circuit. The time stamp counter counts a fixed time interval according to a predetermined clock. The OVF flag records overflow of the time stamp counter. The OVF counter counts the number of times that the time stamp counter overflows. When one trace data are collected, and the OVF flag is turned on, a trace memory write control circuit writes the one trace data, the count value of the time stamp counter and the count value of the OVF counter in a trace memory. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a time stamp acquisition circuit and a time stamp acquisition method.

  An emulator or a debugging system is used for microcomputer program development and debugging. The emulator and the debugging system can collect trace data from the microcomputer, and the program developer can analyze the collected trace data and work efficiently.

  In recent years, the amount of trace information required for emulators and debug systems continues to increase. When performing data tracing, it is required to collect not only access address values and access data values, but also access instruction execution program counter values (Program Counter values: PC values). As for the program execution trace, a branch trace has been widely adopted recently. When branch tracing is performed, collection of branch source / branch destination PC values at the time of branch instruction execution is required. As can be seen from the branch trace, there are programs having a high branch frequency and a high branch frequency, and it is not uncommon to trace the program execution status for several days in debugging the program. Therefore, in the branch trace, the number of branches is often enormous, and in this case, the amount of trace information is enlarged. Furthermore, with the advent of multi-core chips in recent years, it is necessary to collect trace data for the number of CPUs.

  Generally, a time stamp indicating the time when the trace data is collected is stored in the trace memory together with the trace data. In order to effectively use the trace memory, a technique for reducing the amount of time stamp data is known. The invention of “Trace Data Recording Device” described in Japanese Patent Application Laid-Open No. 2007-241431 (see Patent Document 1) uses an n-bit counter that counts with a bit number smaller than that of the real-time counter. The n-bit counter counts the interval at which the trace target bus information is written to the trace memory, and the bus information and the count value of the n-bit counter are stored in the trace memory in association with each other. However, when the n-bit counter reaches full count, the count value of the real-time counter is stored in the trace memory. Since the count value of the n-bit counter has a smaller number of bits than the count value of the real-time counter, the amount of data stored in the trace memory is reduced as a whole.

JP 2007-241431 A

  When the amount of trace information becomes enormous, a large amount of trace memory is required. However, the memory capacity that is built into the evaluation chip cannot withstand the actual use of program debugging. Therefore, in reality, it is indispensable to provide a large scale memory outside the evaluation chip. If the trace memory is provided outside the chip, the capacity of the trace memory can be changed for each microcomputer to be emulated and for each product specification of the emulator and the debug system. In the “trace data recording apparatus” described in the above-mentioned known document, the CPU and the trace memory are mounted on the same chip. Therefore, there is a problem that it is difficult to increase the capacity of the trace memory.

  In particular, a debug chip having an emulation function built into a microcomputer product is required to reduce the circuit scale as much as possible and to reduce the chip cost. The smaller the number of bits of the built-in time stamp counter and the smaller the circuit scale, the better in terms of chip cost. However, in the technique described in the above-mentioned known document, there is a problem that the cost is increased because a real-time counter having a very large circuit scale is mounted in addition to the n-bit counter.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  The time stamp acquisition circuit according to the first aspect of the present invention includes a time stamp counter (36), an overflow flag (34), an overflow counter (71), and a trace memory write control circuit (74). The time stamp counter (36) counts constant time intervals according to a predetermined clock. The overflow flag (34) records that the time stamp counter (36) has overflowed. The overflow counter (71) counts the number of times the time stamp counter (36) has overflowed. When one trace data is collected and the overflow flag (34) is turned on, the trace memory write control circuit (74) sets one trace data and the count value of the time stamp counter (36). The count value of the overflow counter (71) is written into the trace memory (80).

  The time stamp acquisition method according to the second aspect of the present invention includes counting the time interval, recording, counting the number of times, and writing. In counting, a predetermined time interval is counted by a time stamp counter (36) to which a predetermined clock is given. In recording, the overflow flag (34) records that the time stamp counter (36) has overflowed. In counting the number of times, the overflow counter (71) counts the number of times the time stamp counter (36) has overflowed. In writing, when one trace data is collected and the overflow flag (34) is on, the one trace data, the count value of the time stamp counter (36), and the overflow counter (71 ) Is written to the trace memory (80).

  These time stamp acquisition circuits and time stamp acquisition methods can measure a considerably long time by combining the count value of the time stamp counter (36) and the count value of the overflow counter (71). Further, by providing a time stamp counter (36) inside the chip to be traced and providing an overflow counter (72) outside the chip, the circuit scale of the chip to be traced is suppressed and the cost is reduced. be able to. Furthermore, since the trace memory (80) can also be provided outside the chip to be traced, the capacity of the trace memory (80) can be increased.

  According to the present invention, the capacity of the trace memory can be increased. In addition, the circuit scale of the debug chip or evaluation chip to be traced can be reduced.

  FIG. 1 is a block diagram illustrating one of the best modes for carrying out the present invention. In FIG. 1, the time stamp acquisition circuit includes a time stamp counter control circuit 30 and an overflow counter control circuit 70, collects trace data from a multi-core processor, adds a time stamp to the trace data, and generates a trace memory. 80 is written. The time stamp counter control circuit 30 can be mounted on the same chip as the processor, and measures a time interval by a time stamp counter 36 that performs a counting operation according to a predetermined clock. The overflow counter control circuit 70 can be mounted outside the processor chip, and supplements the time measurement by the time stamp counter 36 by an overflow counter 71 that counts the number of times the time stamp counter 36 outputs a carry signal. Similarly to the overflow counter control circuit 70, the trace memory 80 can be mounted outside the processor chip.

  As shown in FIG. 1, the time stamp acquisition circuit according to the present embodiment can collect trace data from a multi-core processor. This multi-core processor has a first processor 13 including a first CPU core 11 and a second processor 14 including a second CPU core 12. The first processor 13 and the second processor 14 output a trace target instruction execution detection signal and trace data when the first CPU core 11 and the second CPU core 12 incorporated therein execute the trace target instruction. . The time stamp counter control circuit 30 inputs these trace target instruction execution detection signals and trace data.

  As illustrated, the time stamp counter control circuit 30 includes a trace message generation circuit 35, a time stamp counter 36, and a trace message buffer 37. In the figure, the time stamp counter 36 is initialized when it receives a reset signal (RES) from the trace message generation circuit 35, and starts counting from zero. The time stamp counter 36 performs a count operation at a constant time interval in synchronization with a predetermined clock, and the time stamp count value is sent to the trace message generation circuit 35. The time stamp counter 36 counts the full count and outputs a carry signal when it overflows. The trace message generation circuit 35 inputs this carry signal. Then, the overflow counter control circuit 70 also inputs this carry signal.

  The trace message generation circuit 35 controls an OVF (Overflow) flag 34. 2A and 2B are explanatory diagrams of a method for controlling the OVF flag 34 by the trace message generation circuit 35. FIG. As shown in FIG. 2A, the trace message generation circuit 35 monitors the carry signal output from the time stamp counter 36 (step S10). When the carry signal is received, the OVF flag 34 is set (S12). The OVF flag 34 is turned on. When the second and subsequent carry signals are received, the ON state is maintained as it is. That is, once the carry signal becomes active, the OVF flag 34 is turned on. On the other hand, as shown in FIG. 2B, the trace message generation circuit 35 determines whether or not the generation process of the trace message to be written in the trace message buffer 37 has ended (S14), and if it has ended, the OVF flag 34 is cleared. (S16). The OVF flag 34 is turned off.

  The trace message generation circuit 35 generates a trace message. The trace message generation circuit 35 shapes the traced data into a predetermined format for each event to be traced (for example, execution PC value, direct branch, indirect branch, RAM access). The formatted data is called a trace message.

  FIG. 2C is an operation explanatory diagram of the trace message generation circuit 35 that writes the trace data sent from the first processor 13 and the second processor 14 to the trace message buffer. In FIG. 2C, the trace message generation circuit 35 monitors the trace target instruction execution detection signal sent from the first processor 13 and the second processor 14 (S20). When the trace target instruction execution detection signal is received, the trace message generation circuit 35 generates a trace message, and requests the count value of the overflow counter 71 as necessary (S22). The trace message includes the trace data received from the first processor 13 or the second processor 14, the time stamp count value received from the time stamp counter 36, and the value of the OVF flag 34. Then, in this embodiment, since a multi-core processor is targeted, a processor identifier indicating the trace data from which processor is further included. The trace message generation circuit 35 writes the generated trace message in the trace message buffer 37 (S24).

  FIG. 2D is an explanatory diagram of an overflow count value requesting method performed by the trace message generation circuit 35 to the overflow counter control circuit 70. The trace message generation circuit 35 performs count value request processing of the overflow counter 71 when generating a trace message. The trace message generation circuit 35 refers to the OVF flag 34 and determines whether the OVF flag 34 is on or off (S26). When the OVF flag 34 is on, the trace message generation circuit 35 outputs a count value request signal of the overflow counter 71 (S28). On the other hand, when the OVF flag 34 is off, the trace message generation circuit 35 does not output the count value request signal of the overflow counter 71.

  Accordingly, when the OVF flag 34 is on, the trace message generation circuit 35 writes the generated trace message in the trace message buffer 37 (S24) and outputs a count value request signal of the overflow counter 71 (S28). As a result, the trace message and the count value of the overflow counter 71 are associated with each other and written to the trace message buffer 37 and the OVF count value buffer 73, respectively. On the other hand, when the OVF flag 34 is OFF, as a result, only writing to the trace message buffer 37 is performed (S24).

  The trace message buffer 37 is a FIFO (First In First Out) buffer. The trace message buffer 37 enters the trace messages generated by the trace message generation circuit 35 in the order in which they are generated, and outputs the head trace message divided by bus width in synchronization with the output clock. Each piece of divided data is output with a status signal indicating whether it is the first piece of divided data, the last piece of divided data, or halfway divided data.

  In FIG. 1, the overflow counter control circuit 70 includes an OVF counter 71, an OVF count value generation circuit 72, an OVF count value buffer 73, and a trace memory write control circuit 74. The OVF counter 71 is initialized when it receives a reset signal (RES) from the trace message generation circuit 35, and starts counting from zero. The OVF counter 71 counts the number of carry signals output from the time stamp counter 36, and counts up each time the carry signal becomes active.

  When the OVF count value request signal from the trace message generation circuit 35 becomes active, the OVF count value generation circuit 72 reads the count value of the OVF counter 71 and enters the count value in the OVF count value buffer 73. When the OVF count value request signal from the trace message generation circuit 35 is not active, writing to the OVF count value buffer 73 is not performed.

  The OVF count value buffer 73 is a FIFO (First In First Out) buffer. The count values generated by the OVF count value generation circuit 72 are entered in the OVF count value buffer 73 in the order of generation.

  The trace memory write control circuit 74 receives a trace message output from the trace message buffer 37 and receives a count value output from the OVF count value buffer 73. Then, writing to the trace memory 80 is performed. 3 and 4 are explanatory diagrams of the operation of the trace memory write control circuit 74. FIG. FIG. 3 shows a specific example of the data structure in the two buffers 37 and 73 and the trace memory 80. Referring to the example of FIG. 3, the trace message buffer 37 has six entries, and the OVF count value buffer 73 has two entries. Referring to the six entries in the trace message buffer 37, it can be seen that when the trace data in the fourth trace message is collected, the time stamp counter 36 overflows and the first carry signal is output. It can also be seen that when the trace data in the sixth trace message is collected, the time stamp counter 36 overflows and the second carry signal is output.

  The write operation of the trace memory write control circuit 74 will be described in detail based on the specific example of FIG. 3 and the flowchart of FIG. First, the trace memory write control circuit 74 reads the first trace message from the trace message buffer 37. Then, by referring to the overflow flag in the trace message, it is determined whether it is on or off (S40). As shown in FIG. 3, since the overflow flag in the first trace message is off, the trace memory write control circuit 74 writes the first trace message in the trace memory 80 (S43). The write address to the trace memory 80 is incremented (S44). Similarly, the trace memory write control circuit 74 writes the second trace message and the third trace message in the trace memory 80 (S43).

  Subsequently, the trace memory write control circuit 74 reads the fourth trace message from the trace message buffer 37. Then, by referring to the overflow flag in the fourth trace message, it is determined whether it is on or off (S40). Since the overflow flag in the fourth trace message is on, the trace memory write control circuit 74 reads the first OVF count value from the OVF count value buffer. Then, the first OVF count value is written in the trace memory 80 (S41). The write address to the trace memory 80 is incremented (S42). Further, the trace memory write control circuit 74 writes the fourth trace message in the trace memory 80 (S43). The write address to the trace memory 80 is incremented (S44).

  Next, the trace memory write control circuit 74 reads the fifth trace message from the trace message buffer 37. Then, by referring to the overflow flag in the trace message, it is determined whether it is on or off (S40). Since the overflow flag in the fifth trace message is off, the trace memory write control circuit 74 writes the fifth trace message in the trace memory 80 (S43). The write address to the trace memory 80 is incremented (S44).

  Then, the trace memory write control circuit 74 reads the last sixth trace message from the trace message buffer 37. Then, by referring to the overflow flag in the sixth trace message, it is determined whether it is on or off (S40). Since the overflow flag in the sixth trace message is on, the trace memory write control circuit 74 reads the last second OVF count value from the OVF count value buffer. Then, the second OVF count value is written in the trace memory 80 (S41). The write address to the trace memory 80 is incremented (S42). Further, the trace memory write control circuit 74 writes the sixth trace message in the trace memory 80 (S43). The write address to the trace memory 80 is incremented (S44).

  With the above writing operation, the contents of the trace memory 80 become as shown in FIG. As shown in the figure, when the overflow flag in the trace message read from the trace message buffer 37 is on, the trace memory 80 stores the OVF count value and the trace message as a set. On the other hand, when the overflow flag in the trace message read from the trace message buffer 37 is OFF, only the trace message is stored in the trace memory 80.

An overall operation example of the time stamp acquisition circuit in this embodiment will be briefly described.
Step 1. The time stamp counter 36 and the OVF counter 71 are initialized.
Step 2. The first processor 13 or the second processor 14 executes a user program. At the same time, the time stamp counter 36 and the OVF counter 71 start counting up.
Step 3. When the first processor 13 detects the execution of the trace target instruction in the first CPU core 11, the trace target instruction execution detection signal and the trace data are output to the trace message generation circuit 35.
Step 4. Similarly, when the second processor 14 detects the execution of the trace target instruction by the second CPU core 12, the trace target instruction execution detection signal and the trace data are output to the trace message generation circuit 35.
Step 5. The trace message generation circuit 35 sets the OVF flag 34 once the carry signal of the time stamp counter 36 becomes active before receiving the trace target instruction execution detection signal from the first processor 13 or the second processor 14. The state of the set OVF flag 34 is retained until a trace message is generated after receiving the trace target instruction execution detection signal.
Step 6. When the trace message generation circuit 35 receives the trace target instruction execution detection signal from the first processor 13 and the second processor 14, the trace message generation circuit 35 reads the count value from the time stamp counter 36. At this time, if the OVF flag 34 is set, an OVF count value request signal is output to the OVF count value generation circuit 72.
Step 7. The trace message generation circuit 35 includes trace data from the first processor 13 and the second processor 14 (the processor in the present embodiment is multi-core, and therefore includes information indicating which processor the data is from), and the time stamp count value. , A trace message is generated from the value of the OVF flag 34 and entered in the trace message buffer 37.
Step 8. When receiving the OVF count value request signal, the OVF count value generation circuit 72 enters the count value of the OVF counter 71 in the OVF count value buffer 73.
Step 9. The trace message generation circuit 35 activates the reset signal (RES) and clears the time stamp counter 36 and the OVF counter 71 to zero.
Step 10. The trace message buffer 37 outputs the trace messages to the trace memory write control circuit 74 sequentially from the top.
Step 11. Each time the first processor 13 and the second processor 14 detect execution of the instruction to be traced, the above step 3. ~ Step 9. Execute.
Step 12. The trace memory write control circuit 74 receives the trace message output from the trace message buffer 37. If the overflow flag in the trace message is off, the trace message is written to the trace memory 80 and the write address to the trace memory 80 is incremented.
Step 13. If the overflow flag in the trace message is ON, the trace memory write control circuit 74 first sets the first OVF count value of the OVF count value buffer 73 to the trace memory 80 before writing the trace message to the trace memory 80. After writing and incrementing the address, a trace message is written, and the address of the trace memory 80 is further incremented.

The following effects can be given as effects in the present embodiment.
[1] In this embodiment, it is not necessary to provide the trace memory 80 on the same chip as the processor. Therefore, since the capacity of the trace memory 80 can be sufficiently increased, it is possible to obtain a large amount of trace data necessary for program development / debugging of the multi-core chip.
[2] In this embodiment, since only one relatively small time stamp counter is provided on the same chip as the processor, it is possible to suppress an increase in the bus width of the output bus. Therefore, the cost of the debug chip and the evaluation chip can be reduced. Further, the circuit scale of the time stamp counter can be considerably reduced as compared with the circuit scale of the real-time counter as shown in FIG. Therefore, there is an effect that the circuit scale of the debug chip and the evaluation chip can be considerably reduced.
[3] In this embodiment, the trace message and the OVF count value are separately held in different FIFOs, but these are written in association with each other. Therefore, there is an effect that it is possible to easily specify between which of the trace messages sequentially output via the trace message buffer (FIFO) 37 the overflow of the time stamp counter 36 has occurred.

  FIG. 5 is a block diagram illustrating the configuration of the first embodiment. Example 1 is an example in which the time stamp acquisition circuit according to the above-described embodiment is incorporated in the debug chip 41 and the emulator main body 50. In the figure, a socket 21 is mounted on a user target system 20 on which a microcomputer for program development is mounted. The debug chip 41 is responsible for all the functions of the microcomputer to be developed by the program, and has a time stamp control circuit 30 having the above-described functions mounted therein. The debug chip 41 is electrically connected to the user target system 20 via the socket 21. Further, the debug chip 41 is electrically connected to an emulation control circuit 51 that is a component of the emulator main body 50 via the emulation probe 22. The emulation control circuit 51 has an overflow counter control circuit 70 having the above-described functions. The emulation probe 22 plays a role of a cable for transmitting a signal.

  The emulator main body 50 includes an emulation control circuit 51, a trace memory 80, and a host I / F 52. These are mounted on separate chips. The emulator main body 50 is connected to the host PC 60 by a USB cable or the like. In the host PC 60, a debugger program is executed. A debugger program that accepts user operations can communicate with the emulator main body 50 via the host I / F 52.

  Collection of trace data can be started by an instruction from the host PC 60 in which the debugger program is executed. Further, the trace message stored in the trace memory 80 can be read from the emulator main body 50 to the host PC 60 in response to a request from the host PC 60. In addition, the host PC 60 can set the setting register of the emulation control circuit 51 via the host I / F 52, and can set the setting register of the debug chip 41 via the emulation control circuit 51. It can be carried out. A rectangular circuit block 40 surrounded by a dotted line generally corresponds to the configuration diagram of FIG. This is shown for easy understanding of the correspondence.

  FIG. 6 is a block diagram illustrating the configuration of the second embodiment. Example 2 is an example in which the time stamp acquisition circuit according to the above-described embodiment is all incorporated in the emulator main body 55 provided with an evaluation chip. In FIG. 6, the emulator main body 55 includes a peripheral evaluation chip 56, a CPU evaluation chip 43, an emulation control circuit 51, a trace memory 80, and a host I / F 52. These are mounted on separate chips. The CPU evaluation chip 43 is responsible for all functions of the microcomputer to be developed by the program, and has a time stamp control circuit 30 having the above-described functions mounted therein. The CPU evaluation chip 43 is electrically connected to the user target system 20 via the peripheral evaluation chip 56, the emulation probe 22, and the socket 21. Further, the emulator main body 55 is also electrically connected to the emulation control circuit 51. The emulation control circuit 51 has an overflow counter control circuit 70 having the above-described functions.

  The emulator main body 55 is connected to the host PC 60 by a USB cable or the like. In the host PC 60, a debugger program is executed. A debugger program that accepts user operations can communicate with the emulator main body 55 via the host I / F 52. Collection of trace data can be started by an instruction from the host PC 60 in which the debugger program is executed. Further, the trace message stored in the trace memory 80 can be read from the emulator main body 55 to the host PC 60 in response to a request from the host PC 60. In addition, the host PC 60 can set the setting register of the emulation control circuit 51 via the host I / F 52, and the setting register of the CPU evaluation chip 43 can be set via the emulation control circuit 51. Settings can be made. Note that a rectangular circuit block 42 surrounded by a dotted line generally corresponds to the configuration diagram of FIG. This correspondence is illustrated for easy understanding.

The block block diagram explaining one of the best forms for implementing this invention A flowchart for explaining a method of setting the OVF flag 34 A flowchart for explaining a method of clearing the OVF flag 34 Flowchart for explaining a write operation by the trace message generation circuit 35 Flowchart explaining method for requesting overflow count value Data structure diagram for explaining the operation of the trace memory write control circuit 74 Flowchart for explaining the operation of the trace memory write control circuit 74 Block diagram for explaining the configuration of the first embodiment Block diagram for explaining the configuration of the second embodiment

Explanation of symbols

11, 12 CPU cores 13 and 14 Processor 20 User target system 21 Socket 22 Emulation probe 30 Time stamp counter control circuit 34 OVF flag 35 Trace message generation circuit 36 Time stamp counter 37 Trace message buffer 40, 42 Circuit block 41 Debug chip 43 CPU Evaluation chip 50, 55 Emulator main body 51 Emulation control circuit 52 Host I / F
56 Peripheral evaluation chip 60 Host PC
70 Overflow counter control circuit 71 OVF counter 72 OVF count value generation circuit 73 OVF count value buffer 74 Trace memory write control circuit 80 Trace memory

Claims (10)

A time stamp counter that counts a certain time interval according to a predetermined clock; and
An overflow flag for recording that the time stamp counter has overflowed;
An overflow counter that counts the number of times the time stamp counter overflows;
When the one trace data is collected and the overflow flag is on, the one trace data, the count value of the time stamp counter, and the count value of the overflow counter are written to the trace memory. A time stamp acquisition circuit comprising a trace memory write control circuit. A trace message generation circuit that generates a trace message including the trace data, a count value of the time stamp counter, and a value of the overflow flag when the trace data is collected;
A first buffer for storing the one trace message;
A second buffer for storing a count value of the overflow counter when the overflow flag is on when the one trace data is collected;
Trace memory write control circuit
If the value of the overflow flag in the one trace message read from the first buffer is off, the one trace message is written to the trace memory,
If the value of the overflow flag in the one trace message read from the first buffer is on, the one trace message and the count value of the overflow counter stored in the second buffer The time stamp acquisition circuit according to claim 1. The first buffer and the second buffer are:
It consists of FIFO (First In First Out) memory,
The trace message generation circuit includes:
When the one trace message is generated, the one trace message is written into the first buffer, and when the value of the overflow flag in the one trace message is ON, the count value of the overflow counter is set. The time stamp acquisition circuit according to claim 2, wherein a control signal for requesting writing to the second buffer is output. Provide the time stamp counter inside the chip to be traced,
The time stamp acquisition circuit according to claim 3, wherein the overflow counter is provided outside the chip. The chip is
The time stamp acquisition circuit according to claim 4, wherein the time stamp acquisition circuit is a debug chip or a CPU evaluation chip. Counting a certain time interval by a time stamp counter provided with a predetermined clock;
Recording in the overflow flag that the time stamp counter has overflowed;
Counting the number of times the time stamp counter overflowed by an overflow counter;
When the one trace data is collected and the overflow flag is on, the one trace data, the count value of the time stamp counter, and the count value of the overflow counter are written to the trace memory. A time stamp acquisition method. Generating one trace message including the one trace data and a count value of the time stamp counter when the one trace data is collected;
Storing the one trace message in a first buffer;
When the one trace data is collected and the overflow flag is on,
In addition to the one trace message, indicating that the count value of the overflow counter should be written to the trace memory;
Storing the count value of the overflow counter in a second buffer;
The writing is
Reading the one trace message from the first buffer;
Writing the one trace message to the trace memory if the indication to write is not made for the one trace message;
If the indication to write is displayed for the one trace message, the count value of the overflow counter is read from the second buffer, and the count value of the one trace message and the overflow counter is read. The time stamp acquisition method according to claim 6, further comprising: writing a value into the trace memory. The display is
Storing the one trace message further including the value of the overflow flag in the first buffer;
The writing is
When the value of the overflow flag in the one trace message is off, the case where the indication to write is not made,
The time stamp acquisition method according to claim 7, further comprising: when the overflow flag value in the one trace message is turned on, when indicating that the writing should be performed. The first buffer and the second buffer are composed of FIFO memories,
Storing the one trace message comprises:
Storing trace messages in order in the first buffer;
Storing the count value of the overflow counter,
The time stamp acquisition method according to claim 8, further comprising storing the count values in order in the second buffer. Providing the time stamp counter inside the chip to be traced;
The time stamp acquisition method according to claim 9, further comprising: providing the overflow counter outside the chip.

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