CN111367742A - Method, device, terminal and computer readable storage medium for debugging MVP processor - Google Patents
Method, device, terminal and computer readable storage medium for debugging MVP processor Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
Abstract
The invention relates to the field of multithread processing, and provides a method, a device, a terminal and a computer readable storage medium for debugging an MVP processor, so as to debug a single thread or multiple threads of the MVP processor. The method comprises the following steps: the debugging host suspends a target debugging thread through a hardware debugging module, wherein the target debugging thread comprises any one of a hardware single thread or a multi-thread of the MVP processor; enabling the suspended target debugging thread to enter a debuggable state by the hardware debugging module; and debugging the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the corresponding functional register of the target debugging program entering the debuggable state. The technical scheme provided by the invention realizes the debugging of the MVP processor by debugging the thread.
Description
Technical Field
The present invention relates to the field of multithread processing, and in particular, to a method, an apparatus, a terminal, and a computer-readable storage medium for debugging an MVP processor.
Background
In a large-scale and complex software development cycle, in order to guarantee the reliability, flexibility and robustness of a software system, the software is not debugged. Debugging is the process of testing by manual or compiler method before putting the program into actual operation, and correcting grammar error and logic error. This is an essential step in ensuring the correctness of the computer information system. The dynamic behavior of a program (or a process, a process comprising at least one thread) is typically analyzed using debugging functionality provided by the program language or a specialized debugging tool.
A multi-threaded Virtual Pipeline (MVP) processor is a comprehensive processor based on parallel operations from architecture to design, combines the advantages of a GPU and a conventional CPU, and aims to provide the highest efficiency performance. The basic unit of MVP is 4 threads, and a plurality of MVP processors can form a group of multi-core and multi-thread processors with strong computing capability. For a single-core MVP processor, debugging it is essentially a single thread (thread) or multiple threads.
Since the MVP processor is soon available, no debugging solution is available in the industry.
Disclosure of Invention
The invention provides a method, a device, a terminal and a computer readable storage medium for debugging an MVP processor, which are used for realizing the debugging of a single thread or multiple threads of the MVP processor.
In one aspect, the present invention provides a method for debugging an MVP processor, including:
the debugging host suspends a target debugging thread through a hardware debugging module, wherein the target debugging thread comprises any one of a hardware single thread or a multi-thread of the MVP processor;
the hardware debugging module enables the suspended target debugging thread to enter a debuggable state;
and debugging the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the functional register corresponding to the target debugging program entering the debuggable state.
In another aspect, the present invention provides a device for debugging an MVP processor, including:
the debugging host is used for suspending a target debugging thread through a hardware debugging module, wherein the target debugging thread comprises any one of a hardware single thread or a multi-thread of the MVP processor;
a hardware debugging module, configured to enable the suspended target debugging thread to enter a debuggable state;
and the thread debugging module is used for debugging the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the functional register corresponding to the target debugging program entering the debuggable state.
In a third aspect, the present invention provides a terminal, which includes a memory, a processor and a computer program stored in the memory and operable on the processor, and when the processor executes the computer program, the steps of the method according to the above technical solution are implemented.
In a fourth aspect, the invention provides a computer-readable storage medium, in which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the method according to the above-mentioned solution.
According to the technical scheme of the invention, the debugging host suspends the target debugging thread and enters the debuggable state through the hardware debugging module, and the target debugging thread entering the debuggable state is debugged according to the setting of the hardware debugging module on the corresponding functional register of the target debugging program entering the debuggable state, so that the debugging of the MVP processor is realized through the debugging of the thread.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for debugging an MVP processor according to an embodiment of the present invention;
FIG. 2 is a flowchart of a target debugging thread being suspended by a hardware debugging module by a debugging host according to an embodiment of the present invention;
fig. 3 is a flowchart for debugging a target debugging thread entering a debuggable state according to setting of a functional register corresponding to a target debugging program entering the debuggable state by a hardware debugging module according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating debugging a target debugging thread entering a debuggable state according to setting of a functional register corresponding to a target debugging program entering the debuggable state by a hardware debugging module according to another embodiment of the present invention;
FIG. 5 is a flowchart illustrating debugging a target debugging thread entering a debuggable state according to setting of a functional register corresponding to a target debugging program entering the debuggable state by a hardware debugging module according to another embodiment of the present invention;
fig. 6 is a schematic structural diagram of an apparatus for debugging an MVP processor according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In this specification, adjectives such as first and second may only be used to distinguish one element or action from another, without necessarily requiring or implying any actual such relationship or order. References to an element or component or step (etc.) should not be construed as limited to only one of the element, component, or step, but rather to one or more of the element, component, or step, etc., where the context permits.
In the present specification, the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The invention provides a method for debugging an MVP processor, which mainly comprises steps S101 to S103 as shown in figure 1, and is described in detail as follows:
step S101: and the debugging host suspends a target debugging thread through the hardware debugging module, wherein the target debugging thread comprises any one of hardware single thread or multi-thread of the MVP processor.
In the embodiment of the present invention, the debug Host (Host) may be implemented by a Host computer independent from the kernel of the MVP processor, or by any thread of the MVP processor, and therefore, in the following description, when referring to the debug Host or Host, it refers to any thread of the Host computer or MVP processor independent from the MVP processor. Obviously, when the Host is acted by any thread of the MVP processor, when debugging of the MVP processor is executed, an additional upper computer is not needed. When the debugging host is filled with an upper computer independent of the MVP processor, the debugging host can access a hardware debugging module (namely a hardware Debug module) through JTAG (Joint Test Action Group) logic; when the debugging host is filled by any thread of the MVP processor, the thread can directly access the hardware debugging module through an internal communication mechanism of the MVP processor. As for the target debugging thread, that is, the hardware thread to be debugged of the MVP, the target debugging thread includes a hardware single thread of the MVP processor, any one thread of multiple threads, or all hardware threads of the MVP processor, where the hardware threads include threads requiring hardware acceleration in the image engine, the DSP and/or the general image processor, and so on.
As an embodiment of the present invention, the suspending of the target debugging thread by the debugging host through the hardware debugging module can be implemented by steps S201 to S203 as illustrated in fig. 2:
step S201: and the debugging host sends a thread debugging command to the hardware debugging module, wherein the thread debugging command comprises the ID of the target debugging thread.
In the embodiment of the invention, the hardware debugging module is a bridge connecting the MVP kernel module and the debugging host, and the thread control unit in the hardware debugging module is used for controlling and managing the hardware thread to be operated and being operated. Current MVP processors configure 4 hardware threads, each having a parameter or number, i.e., a thread ID, that uniquely identifies the thread. When a debugging person needs to debug a certain hardware thread, namely a target debugging thread, the debugging person designates the target debugging thread, and a debugging host sends a thread debugging command to a hardware debugging module, wherein the thread debugging command comprises the ID of the target debugging thread designated by the debugging person through the debugging host. It should be noted that when it is unknown on which hardware thread the application runs, it means that hardware multithreading or all hardware threads of the MVP processor need to be debugged, and at this time, a debugger will specify, through the debugging host, the IDs of the hardware multithreading or all hardware threads that need to be debugged.
Step S202: and the hardware debugging module sends an interrupt signal corresponding to the ID of the target debugging thread to the MVP kernel module.
For an MVP processor, each thread has not only an ID uniquely corresponding to it, but also includes an interrupt signal corresponding to this ID. Therefore, when the hardware debugging module receives the ID of the target debugging thread sent by the debugging host, the hardware debugging module sends an interrupt signal corresponding to the ID of the target debugging thread to the MVP kernel module.
Step S203: and the MVP kernel module enables the target debugging thread to enter a suspension mode according to the interrupt signal corresponding to the ID of the target debugging thread.
The target debugging thread enters a suspend mode (HALT mode), namely the MVP kernel module stops the target debugging thread and directly or indirectly informs the hardware debugging module that the target debugging thread enters a suspend (HALT) state. It should be noted that, while or before the MVP kernel module makes the target debugging thread enter the suspended mode, the MVP kernel module needs to protect the field, that is, the related information of the thread running before the target debugging thread is suspended is saved, specifically, the state or value of some called environment register is saved, these context registers include a Program Counter (PC) register whose value is the PC value of the address of the next instruction in memory to be accessed, a memory address pointer register for holding a pointer indicating the memory address of the context in which the currently running thread is to be stored, and a thread status register for holding status information relating to the currently running thread, etc., the state or values of these registers may be saved in the MVP processor specific on-chip SRAM. The MVP kernel module protects the site, and one purpose is that after debugging of the target debugging thread is completed, the hardware debugging module can restore the site and rerun the thread running before the target debugging thread is suspended.
Step S102: the hardware debug module causes the suspended target debug thread to enter a debuggable state.
The MVP processor is configured with a variety of functional registers, one bit for each hardware thread. Since the MVP processor has 4 hardware threads, 4 bits of the function register correspond to 4 hardware threads. In an embodiment of the present invention, the hardware debugging module may cause the suspended target debugging thread to enter the debuggable state by setting a function register corresponding to the suspended target debugging thread to a value corresponding to the debuggable state by the hardware debugging module, for example, for one suspended target debugging thread, the function register corresponding to the target debugging thread may be set to "1", and for two or more suspended target debugging threads, the function registers corresponding to the two or more target debugging threads may be set to "1", so that the suspended target debugging thread or threads enter the debuggable state, that is, the target debugging thread or threads can be debuggable at present.
Step S103: and debugging the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the corresponding functional register of the target debugging program entering the debuggable state.
As an embodiment of the present invention, according to the setting of the hardware debug module on the function register corresponding to the target debug program entering the debuggable state, the debugging of the target debug thread entering the debuggable state can be implemented by steps S301 to S304 as illustrated in fig. 3, which is described as follows:
step S301: and converting the debugging operation into a debugging operation instruction and storing the debugging operation instruction in the hardware debugging module.
In the embodiment of the present invention, the debugging operations include, but are not limited to, the following:
1. checking the value of a variable, for example, checking the contents of a general register, a specific register or a memory of the MVP processor, so that a debugger can analyze the reason for the program error;
2. suspending the operation of some or all programs and handing control to debugging personnel through an interactive user interface;
3. running a certain routine defined by a debugging person;
4. the state of the debugged thread is recorded, that is, the operation condition of the debugged thread at a certain time is saved in a certain external storage device for analysis.
In an embodiment of the present invention, converting the debug operation into the debug operation instruction may be performed by a debugger on the debug host.
Step S302: the MVP kernel module reads the debugging operation instruction from the hardware debugging module to execute, and returns the execution result to the hardware debugging module.
In the embodiment of the present invention, the hardware debugging module may make the MVP kernel module enter a mode of executing a debugging operation instruction. After the MVP kernel module enters the mode of executing the debugging operation instruction, the MVP kernel module can read the debugging operation instruction stored in the hardware debugging module from the hardware debugging module to execute the debugging operation instruction, and return the execution result to the hardware debugging module.
Step S303: and setting the command execution register to a value corresponding to the end of the execution of the debugging operation instruction by the hardware debugging module.
After receiving the execution result returned by the MVP kernel module, the hardware debug module learns that the execution of the debug operation instruction corresponding to the debug operation is finished, and then sets the command execution register to a value corresponding to the execution of the debug operation instruction, for example, set to "1". And the hardware debugging module uploads the set value of the command execution register to the debugging host so as to inform the debugging host of the end of the execution of the debugging operation instruction corresponding to the debugging operation.
Step S304: and the debugging host reads the execution result of the debugging operation instruction from the hardware debugging module according to the value of the command execution register.
And after the debugging host learns that the debugging operation instruction corresponding to the debugging operation is executed according to the value of the command execution register, reading a result of the execution of the debugging operation instruction from the hardware debugging module, and providing the result for a debugging person to analyze.
As another embodiment of the present invention, according to the setting of the hardware debug module on the function register corresponding to the target debugger entering the debuggable state, the debugging of the target debug thread entering the debuggable state can be implemented by steps S401 to S403 as illustrated in fig. 4, which is described as follows:
step S401: and the hardware debugging module sets a breakpoint register corresponding to the target debugging thread which enters the debuggable state.
In the embodiment of the present invention, each target debugging thread corresponds to a Breakpoint (BP) register or a Match Point (Match Point, MP) register, and the breakpoint for debugging the target debugging thread can be set by setting the BP register or MP register corresponding to the target debugging thread.
Step S402: and the hardware debugging module enables the target debugging thread in the debuggable state to enter a breakpoint debugging mode from the debuggable state.
As described above, the BP register or MP register corresponding to the target debugging thread is set to set the breakpoint for debugging of the target debugging thread. If debugging of the target debugging thread is required, the value of the BP register of the target debugging thread may be set to a certain value of a Program Counter (PC). When the MVP kernel hits a BP register, a program stops at a code indicated by the value of the PC, a target debugging thread is suspended, and a breakpoint debugging mode is entered from a debuggable state; the operating system transfers the acquired control right to a debugging tool, and the debugging tool executes specific debugging work; after the debugging tool finishes the debugging work, the debugging tool writes back the original instruction at the breakpoint to the original position of the target debugging thread so as to execute the original instruction; the setting of the MP register is similar, except that the set value is the address of some data to be viewed during debugging. It should be noted that protection is required for the field before the interrupt instruction replaces the instruction at the instruction sequence interrupt point of the suspended target debugging thread. The purpose of protecting the field is as described above, that is, the debugging tool can restore its previous running state before completing debugging and returning the control right to the target debugging thread, otherwise, the running environment of the target debugging thread is damaged.
Step S403: after the target debugging thread entering the breakpoint debugging mode completes breakpoint debugging, the hardware debugging module enables the target debugging thread of the breakpoint debugging mode to be suspended again and enter a debuggable state.
In this step, the hardware debugging module suspends the target debugging thread of the breakpoint debugging mode again and enters the debuggable state, which can be realized similarly to the steps S101 and S102 illustrated in fig. 1. After the target debugging thread is suspended again and enters a debuggable state, the debugging host may perform debugging operations on the target debugging thread, such as checking the value of a variable, suspending execution of some or all threads, executing some routine predefined by a debugging person, generating a record of the running condition of the target debugging thread, and so on.
As another embodiment of the present invention, according to the setting of the hardware debug module on the function register corresponding to the target debugger entering the debuggable state, the debugging of the target debug thread entering the debuggable state can be implemented by steps S501 to S503 as illustrated in fig. 5, which is described as follows:
step S501: and the hardware debugging module sets a single step debugging register corresponding to the target debugging thread entering the debuggable state.
In the embodiment of the present invention, the value set by the step debugging register determines the mode for debugging the target debugging thread, for example, if the value set by the step debugging register of a certain target debugging thread is "1", the target debugging thread enters the step debugging mode.
Step S502: and the hardware debugging module enables the target debugging thread in the debuggable state to enter a single step debugging mode.
Step S503: after the target debugging thread entering the single step debugging mode completes the single step debugging, the hardware debugging module enables the target debugging thread of the single step debugging mode to be suspended again and enter a debuggable state.
Similar to step S403 in the foregoing example, after the target debugging thread entering the step debugging mode completes the step debugging, the hardware debugging module suspends the target debugging thread in the step debugging mode again and enters a debuggable state (similar to the implementation through step S101 and step S102 in the example of fig. 1), and the debugging host may perform debugging operations on the target debugging thread, including checking the value of a variable, suspending the execution of some or all threads, executing a certain routine predefined by a debugging person, and generating a record of the running condition of the target debugging thread, and so on.
As can be seen from the method for debugging the MVP processor illustrated in fig. 1, the debugging host suspends the target debugging thread and enters the debuggable state through the hardware debugging module, and debugs the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the functional register corresponding to the target debugging program entering the debuggable state, thereby implementing the debugging of the MVP processor through the debugging of the thread.
Referring to fig. 6, a device for debugging an MVP processor according to an embodiment of the present invention includes a debugging host 601, a hardware debugging module 602, and a thread debugging module 603, which are detailed as follows:
the debugging host 601 is configured to suspend a target debugging thread through a hardware debugging module, where the target debugging thread includes any one of a hardware single thread or a multi-thread of the MVP processor;
a hardware debug module 602, configured to enable the suspended target debug thread to enter a debuggable state;
the thread debugging module 603 is configured to debug the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the functional register corresponding to the target debugging program entering the debuggable state.
Optionally, the debugging host illustrated in fig. 6 is further configured to send a thread debugging command to the hardware debugging module, where the thread debugging command includes an ID of the target debugging thread; the hardware debugging module is also used for sending an interrupt signal corresponding to the ID of the target debugging thread to the MVP kernel module; and the MVP kernel module is used for suspending the target debugging thread according to the interrupt signal.
Optionally, hardware debug module 602 of the example of fig. 6 is further configured to set a function register corresponding to the suspended target debug thread to a value corresponding to a debuggable state.
Optionally, the thread debugging module 603 illustrated in fig. 6 is further configured to convert the debugging operation into a debugging operation instruction and store the debugging operation instruction in the hardware debugging module 602; the MVP kernel module is configured to read a debug operation instruction from the hardware debug module 602, execute the debug operation instruction, and return an execution result to the hardware debug module 602; the hardware debugging module 602 is further configured to set the command execution register to a value corresponding to the end of the execution of the debugging operation instruction; the debug host 601 is also configured to read a result of the execution of the debug operation instruction from the hardware debug module 602 according to the value of the command execution register.
Optionally, the hardware debugging module 602 in the example in fig. 6 is further configured to set a breakpoint register corresponding to a target debugging thread that enters a debuggable state; the hardware debugging module 602 is further configured to enable a target debugging thread in a debuggable state to enter a breakpoint debugging mode from the debuggable state; after the target debugging thread entering the breakpoint debugging mode completes breakpoint debugging, the hardware debugging module 602 is further configured to suspend the target debugging thread entering the breakpoint debugging mode again and enter a debuggable state.
Optionally, the hardware debugging module 602 in the example of fig. 6 is further configured to set a single step debugging register corresponding to the target debugging thread entering the debuggable state; the hardware debugging module 602 is further configured to enable the target debugging thread in the debuggable state to enter a single step debugging mode; after the target debugging thread entering the single step debugging mode completes the single step debugging, the hardware debugging module 602 is further configured to suspend the target debugging thread entering the single step debugging mode again and enter a debuggable state.
It can be seen from the above description of the technical solution that the debugging host suspends and enters the debuggable state through the hardware debugging module, and debugs the target debugging thread entering the debuggable state according to the setting of the hardware debugging module to the corresponding function register of the target debugging program entering the debuggable state, thereby implementing the debugging of the MVP processor through the debugging of the thread.
Fig. 7 is a schematic structural diagram of a terminal according to an embodiment of the present invention. As shown in fig. 7, the terminal 7 of this embodiment mainly includes: a processor 70, a memory 71, and a computer program 72 stored in the memory 71 and operable on the processor 70, such as a program of a method of debugging an MVP processor. The processor 70, when executing the computer program 72, implements the steps in the above-described method embodiment of debugging an MVP processor, such as steps S101 to S103 shown in fig. 1. Alternatively, the processor 70, when executing the computer program 72, implements the functions of the modules/units in the above-described device embodiments, such as the functions of the debugging host 601, the hardware debugging module 602, and the thread debugging module 603 shown in fig. 6.
Illustratively, the computer program 72 of the method of debugging an MVP processor mainly includes: the debugging host suspends a target debugging thread through a hardware debugging module, wherein the target debugging thread comprises any one of a hardware single thread or a multi-thread of the MVP processor; enabling the suspended target debugging thread to enter a debuggable state by the hardware debugging module; and debugging the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the corresponding functional register of the target debugging program entering the debuggable state. The computer program 72 may be divided into one or more modules/units, which are stored in the memory 71 and executed by the processor 70 to accomplish the present invention. One or more of the modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 72 in the terminal 7. For example, the computer program 72 may be divided into functions of a debugging host 601, a hardware debugging module 602, and a thread debugging module 603 (modules in the virtual device), and the specific functions of each module are as follows: the debugging host 601 is configured to suspend a target debugging thread through a hardware debugging module, where the target debugging thread includes any one of a hardware single thread or a multi-thread of the MVP processor; a hardware debug module 602, configured to enable the suspended target debug thread to enter a debuggable state; the thread debugging module 603 is configured to debug the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the functional register corresponding to the target debugging program entering the debuggable state.
The terminal 7 may include, but is not limited to, a processor 70, a memory 71. Those skilled in the art will appreciate that fig. 7 is merely an example of a terminal 7 and does not constitute a limitation of terminal 7 and may include more or fewer components than shown, or some components may be combined, or different components, e.g., a computing device may also include an input-output device, a network access device, a bus, etc.
The Processor 70 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an application specific integrated circuit (Appljcatjon specjfc jted cjujujt, ASJC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The storage 71 may be an internal storage unit of the terminal 7, such as a hard disk or a memory of the terminal 7. The memory 71 may also be an external storage device of the terminal 7, such as a plug-in hard disk provided on the terminal 7, a Smart Memory Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory 71 may also include both an internal storage unit of the terminal 7 and an external storage device. The memory 71 is used for storing computer programs and other programs and data required by the terminal. The memory 71 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned functions may be distributed as required to different functional units and modules, that is, the internal structure of the apparatus may be divided into different functional units or modules to implement all or part of the functions described above. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the above-mentioned apparatus may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal and method may be implemented in other ways. For example, the above-described device/terminal embodiments are merely illustrative, and for example, a module or a unit may be divided into only one logical function, and may be implemented in other ways, for example, multiple units or components may be combined or integrated into another device, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a non-transitory computer readable storage medium. Based on such understanding, all or part of the processes in the method according to the embodiments of the present invention may also be implemented by instructing related hardware through a computer program, where the computer program of the method for debugging an MVP processor may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the embodiments of the method may be implemented, that is, the debugging host suspends a target debugging thread through a hardware debugging module, where the target debugging thread includes any one of a hardware single thread or a hardware multi-thread of the MVP processor; enabling the suspended target debugging thread to enter a debuggable state by the hardware debugging module; and debugging the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the corresponding functional register of the target debugging program entering the debuggable state. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The non-transitory computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the non-transitory computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, non-transitory computer readable media does not include electrical carrier signals and telecommunications signals as subject to legislation and patent practice. The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method of debugging an MVP processor, the method comprising:
the debugging host suspends a target debugging thread through a hardware debugging module, wherein the target debugging thread comprises any one of a hardware single thread or a multi-thread of the MVP processor;
the hardware debugging module enables the suspended target debugging thread to enter a debuggable state;
and debugging the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the functional register corresponding to the target debugging program entering the debuggable state.
2. The method of debugging an MVP processor of claim 1, wherein the debugging host suspending a target debugging thread through a hardware debugging module, comprising:
the debugging host sends a thread debugging command to the hardware debugging module, wherein the thread debugging command comprises the ID of the target debugging thread;
the hardware debugging module sends an interrupt signal corresponding to the ID of the target debugging thread to an MVP kernel module;
and the MVP kernel module enables the target debugging thread to enter a suspended mode according to the interrupt signal.
3. The method of debugging an MVP processor of claim 1, wherein the hardware debugging module causing the suspended target debugging thread to enter a debuggable state comprises:
and the hardware debugging module sets the functional register corresponding to the suspended target debugging thread to be a value corresponding to the debuggable state.
4. The method according to any one of claims 1 to 3, wherein the debugging the target debugging thread entering the debuggable state according to the setting of the corresponding function register of the target debugging program entering the debuggable state by the hardware debugging module comprises:
converting the debugging operation into a debugging operation instruction and storing the debugging operation instruction in the hardware debugging module;
the MVP kernel module reads the debugging operation instruction from the hardware debugging module for execution and returns the execution result to the hardware debugging module;
the hardware debugging module sets the command execution register to be a value corresponding to the end of the execution of the debugging operation instruction;
and the debugging host reads the execution result of the debugging operation instruction from the hardware debugging module according to the value of the command execution register.
5. The method according to any one of claims 1 to 3, wherein the debugging the target debugging thread entering the debuggable state according to the setting of the corresponding function register of the target debugging program entering the debuggable state by the hardware debugging module comprises:
the hardware debugging module sets a breakpoint register corresponding to the target debugging thread which enters the debuggable state;
the hardware debugging module enables the target debugging thread in the debuggable state to enter a breakpoint debugging mode from the debuggable state;
and after the target debugging thread entering the breakpoint debugging mode finishes breakpoint debugging, the hardware debugging module enables the target debugging thread entering the breakpoint debugging mode to be suspended again and enter a debuggable state.
6. The method according to any one of claims 1 to 3, wherein the debugging the target debugging thread entering the debuggable state according to the setting of the corresponding function register of the target debugging program entering the debuggable state by the hardware debugging module comprises:
the hardware debugging module sets a single step debugging register corresponding to the target debugging thread entering a debuggable state;
enabling the target debugging thread in the debuggable state to enter a single-step debugging mode by the hardware debugging module;
after the target debugging thread entering the single step debugging mode finishes the single step debugging, the hardware debugging module enables the target debugging thread entering the single step debugging mode to be suspended again and enter a debuggable state.
7. An apparatus for debugging an MVP processor, the apparatus comprising:
the debugging host is used for suspending a target debugging thread through a hardware debugging module, wherein the target debugging thread comprises any one of a hardware single thread or a multi-thread of the MVP processor;
a hardware debugging module, configured to enable the suspended target debugging thread to enter a debuggable state;
and the thread debugging module is used for debugging the target debugging thread entering the debuggable state according to the setting of the hardware debugging module on the functional register corresponding to the target debugging program entering the debuggable state.
8. The apparatus for debugging an MVP processor of claim 7, wherein the debugging host is further configured to send a thread debugging command to the hardware debugging module, the thread debugging command comprising an ID of the target debugging thread;
the hardware debugging module is also used for sending an interrupt signal corresponding to the ID of the target debugging thread to an MVP kernel module;
and the MVP kernel module is used for suspending the target debugging thread according to the interrupt signal.
9. A terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 6.
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