CN105550118A - Debugging system and debugging method - Google Patents
Debugging system and debugging method Download PDFInfo
- Publication number
- CN105550118A CN105550118A CN201610057410.9A CN201610057410A CN105550118A CN 105550118 A CN105550118 A CN 105550118A CN 201610057410 A CN201610057410 A CN 201610057410A CN 105550118 A CN105550118 A CN 105550118A
- Authority
- CN
- China
- Prior art keywords
- bus controller
- debug
- breakpoint
- program
- command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3656—Software debugging using additional hardware using a specific debug interface
Abstract
The invention provides a debugging system and a debugging method. The debugging system comprises an on-chip bus controller and at least one external bus controller, wherein the on-chip bus controller is connected with an embedded system processor unit; a debugging module is embedded in the on-chip bus controller; the external bus controller is connected with the on-chip bus controller; the external bus controller is used for transmitting a debugging command input by a debugging device to the on-chip bus controller, or transmitting a debugging result output by the on-chip bus controller to the debugging device; and the debugging module embedded in the on-chip bus controller is used for analyzing the debugging command after receiving the debugging command input by any one external bus controller, and executing a corresponding debugging action according to the analyzed debugging command, so that a special emulator does not need to be configured, and moreover, the debugging system can be connected to the internet by the universal external bus controller to conveniently achieve remote debugging.
Description
Technical field
The present invention relates to embedded systems debugging technical field, more particularly, relate to a kind of debug system and adjustment method.
Background technology
In prior art, the editor of embedded program, compiling, link process all complete on computing machine (or workstation), we are referred to as host (Host) usually, and the final operation of program carries out having on the embedded device of very large difference with host, we are referred to as target machine (Target) usually.Wherein, target machine with the essential difference of host is: one, hardware environment is different, and namely CPU (CentralProcessingUnit, processor) type is different; Two, software environment is different, host has the application software support of ripe operating system, and target machine is generally bare machine or the embedded system needing debugging.Based on this, debugging is requisite link in embedded systemic software development process.
The debug system of existing embedded system is normally undertaken by emulator and specific debug bus, such as ARM series processors is debugged with the ARM emulator being connected computing machine by JTAG/SWD bus, and MIPS series processors is debugged with the MIPS emulator being connected computing machine by EJTAG bus.But, because each processor architecture needs the special debug bus of configuration and emulator, therefore, awkward problem can be brought.Further, it can not realize remote debugging.
Summary of the invention
In view of this, the invention provides a kind of debug system and adjustment method, need to configure special debug bus and emulator to solve each processor architecture in prior art and cause the inconvenience used and the problem that can not realize remote debugging.
For achieving the above object, the invention provides following technical scheme:
A kind of debug system, comprises the on-chip bus controller being embedded with debugging module and at least one external bus controller be connected with described on-chip bus controller;
External bus controller described in each is connected with a commissioning device, different described external bus controllers is by different communication modes and described commissioning device communication, described external bus controller is used for the debug command that described commissioning device inputs to transfer to described on-chip bus controller, and the debug results that described on-chip bus controller exports is transferred to described commissioning device;
Described on-chip bus controller is connected with the processor unit of embedded system, the embedded debugging module of described on-chip bus controller is used for resolving described debug command after the debug command receiving arbitrary described external bus controller input, and performs corresponding debug action according to the debug command after described parsing.
Preferably, described debugging module comprises communication control unit, debug command resolution unit and debugging performance element;
Described debug command for receiving the debug command of described external bus controller input, and is transferred to described debug command resolution unit by described communication control unit, and debug results is transferred to described external bus controller;
Described debug command resolution unit is used for resolving described debug command according to preset format, and the debug command after resolving is transferred to described debugging performance element;
Described debugging performance element triggers corresponding debug function module according to the debug command after described parsing and performs corresponding debugging operations.
Preferably, the debug function module in described debugging performance element comprises physical address space module for reading and writing, hardware program breakpoint processing module, hardware data breakpoint processing module, program halt processing module and program circuit tracing module;
Described physical address space module for reading and writing is used for the read-write motion that the physical address space read write command after according to parsing triggers on-chip bus controller, and by described communication control unit, the read-write result of on-chip bus controller is transferred to described external bus controller;
Described hardware program breakpoint processing module is used for the hardware program breakpoint setup order save routine breakpoint address after according to parsing, and when described processor unit reads the instruction of described breakpoint address, the presumptive instruction at described breakpoint address place is replaced with special instruction, so that described processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Described hardware program breakpoint processing module is also for deleting corresponding program breakpoint address according to the hardware program breakpoint clear command after parsing;
Described hardware data breakpoint processing module is used for the hardware data breakpoint setup order after according to parsing and preserves data breakpoint address, and send specific interruption when described processor unit reads or writes described breakpoint address to described processor unit, so that described processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Described hardware data breakpoint processing module is also for deleting corresponding data breakpoint address according to the hardware data breakpoint clear command after parsing;
Described program halt processing module is used for the program halt order after according to parsing and sends specific interruption to described processor unit, so that described processor unit is directed to specific debugged program, and other debug command of wait out of service at once;
Described program circuit tracing module is used for the program circuit tracer command monitoring after according to parsing and preserves the address of the instruction stream that described processor unit reads, and transfer to described external bus controller after being compressed, so that described commissioning device obtains the instruction stream of tracked program.
Preferably, described on-chip bus controller is connected by input/output bus on sheet with described external bus controller, carries out the transmission of data between described on-chip bus controller and described external bus controller in the mode of two-way byte stream.
Preferably, described on-chip bus controller is connected with described processor unit by the proprietary debugging interface of described processor unit.
Preferably, described external bus controller is connected with described commissioning device by UART serial ports, SPI serial ports, USB interface or Ethernet interface.
A kind of adjustment method, be applied to the debug system as above described in any one, described adjustment method comprises:
The embedded debugging module of on-chip bus controller is resolved the debug command received;
The embedded debugging module of described on-chip bus controller performs corresponding debug action according to the debug command after described parsing.
Preferably, described on-chip bus controller also comprises before resolving the debug command received:
The embedded debugging module of described on-chip bus controller receives the debug command of commissioning device input by external bus controller.
Preferably, perform corresponding debug action according to the debug command after described parsing after also comprise:
Debug results is transferred to described commissioning device by described external bus controller by the embedded debugging module of described on-chip bus controller.
Preferably, perform corresponding debug action according to the debug command after described parsing to comprise:
Trigger described on-chip bus controller according to the physical address space read write command after parsing and carry out read-write motion, and the read-write result of described on-chip bus controller is transferred to described external bus controller;
According to the hardware program breakpoint setup order save routine breakpoint address after parsing, and when described processor unit reads the instruction of described breakpoint address, the presumptive instruction at described breakpoint address place is replaced with special instruction, so that described processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Data breakpoint address is preserved according to the hardware data breakpoint setup order after resolving, and send specific interruption when described processor unit reads or writes described breakpoint address to described processor unit, so that described processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Corresponding program breakpoint address is deleted according to the hardware program breakpoint clear command after resolving;
Corresponding data breakpoint address is deleted according to the hardware data breakpoint clear command after resolving;
Specific interruption is sent to described processor unit according to the program halt order after resolving, so that described processor unit is directed to specific debugged program, other debug command of wait out of service at once;
According to the program circuit tracer command monitoring after parsing and the address of preserving the instruction stream that described processor unit reads, and transfer to described external bus controller by after the address compression of described instruction stream, so that described commissioning device obtains the instruction stream of tracked program.
Compared with prior art, technical scheme provided by the present invention has the following advantages:
Debug system provided by the present invention and adjustment method, embedded debugging module on the on-chip bus controller be connected with the processor unit of embedded system, thus by the debugging module that on-chip bus controller is embedded, software in described embedded system can be debugged, and then no longer need to configure special emulator, and, remote debugging can also be realized by universal external bus controller connecting Internet, make embedded systems debugging convenient.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
The structural representation of a kind of debug system that Fig. 1 provides for the embodiment of the present invention;
The structural representation of a kind of debugging module that Fig. 2 provides for the embodiment of the present invention;
The process flow diagram of a kind of adjustment method that Fig. 3 provides for the embodiment of the present invention;
The process flow diagram of the another kind of adjustment method that Fig. 4 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment provides a kind of debug system, be applied to the debugging of the embedded software on system level chip, wherein embedded software is the program curing be solidificated in system level chip, the such as control program etc. of air-conditioning master control microcontroller, as shown in Figure 1, the debug system in the present embodiment comprises the on-chip bus controller 1 being embedded with debugging module and at least one external bus controller 2 be connected with on-chip bus controller 1.
Wherein, the processor unit of on-chip bus controller 1 and embedded system and processor 3 are connected.Particularly, on-chip bus controller 1 is by SOC (system on a chip) bus 5 and the processor on chip, RAM/ROM such as volatile memory is connected with nonvolatile memory and other functional module, be connected with at least one external bus controller 2 with input/output bus bridge 6 by input/output bus, that is, on-chip bus controller 1 is the main control equipment of system bus and input/output bus in internal sheets, based on this, in the present embodiment on on-chip bus controller 1 embedded debugging module, itself and general external bus controller 2 is made to constitute the debug system be embedded on system-level of a unification easy to use.
Particularly, the debugging module that the on-chip bus controller 1 in the present embodiment is embedded for receive arbitrary external bus controller 2 input debug command after debug command is resolved, and according to resolve after debug command perform corresponding debug action.
Each external bus controller 2 can be connected with a commissioning device 4, different external bus controllers 2 can by different communication modes and commissioning device 4 communication, this external bus controller 2 transfers to on-chip bus controller 1 for the debug command inputted by commissioning device 4, or the debug results that on-chip bus controller 1 exports is transferred to commissioning device 4.Wherein, different with the implementation of input/output bus according to SOC (system on a chip) bus, on-chip bus controller 1 is also different from the communication modes of external bus controller 2, such as, in a kind of situation, on-chip bus controller 1 needs to adopt the mode of inquiry to access external bus controller 2, receives the debug command that external bus controller 2 inputs.
In addition, external bus controller 2 can pass through UART (UniversalAsynchronousReceiver/Transmitter, asynchronous serial communication interface) serial ports, SPI (SerialPeripheralInterface, Serial Peripheral Interface (SPI)) interface, USB (UniversalSerialBus, USB (universal serial bus)) interface or Ethernet interface be connected with commissioning device 4, that is, an external bus controller 2 in the present embodiment can be connected with a commissioning device 4 by UART serial ports, an external bus controller 2 can be connected with a commissioning device 4 by SPI serial ports, an external bus controller 2 can pass through Ethernet interface accessing Internet, long-range connection is carried out with the commissioning device 4 of an accessing Internet.
In the present embodiment, on-chip bus controller 1 and external bus controller 2 carry out the transmission of data with the form of two-way byte stream.On-chip bus controller 1 is just debugged after the debug command receiving external bus controller 2 input, user can need or development Experience according to test, manually selected or input debug command by the man machine operation interface of commissioning device 4, or commissioning device 4 periodically can send debug command to on-chip bus controller 1 according to the selftest module of its inside.
It should be noted that further, as shown in Figure 2, the embedded debugging module of on-chip bus controller 1 comprises communication control unit 10, debug command resolution unit 11 and debugging performance element 12, wherein, communication control unit 10 is two-way byte stream communication controller, for receiving the debug command that external bus controller 2 inputs, and debug command is transferred to debug command resolution unit 11, or debug results is transferred to external bus controller 2; Debug command after resolving for resolving debug command according to preset format, and is transferred to debugging performance element 12 by debug command resolution unit 11; Debugging performance element 12 triggers corresponding debug function module and performs corresponding debug action; The interface that debugging performance element 12 is connected with processor 3 comprises the proprietary debugging interface 03 of system bus interface 01, NMI interrupt signal interface 02 and processor such as jtag interface.
In the present embodiment, debug function module in debugging performance element 12 comprises physical address space module for reading and writing, hardware program breakpoint processing module, hardware data breakpoint processing module, program halt processing module and program circuit tracing module, certainly, debugging performance element also can comprise other debug function modules, the present invention is not limited to this, and deviser can design the debug function of debugging performance element and revise as required.
Wherein, physical address space module for reading and writing is used for the physical address space read write command triggering on-chip bus controller 1 after according to parsing and carries out read-write motion, and by communication control unit 10, the read-write result of on-chip bus controller 1 is transferred to external bus controller 2;
Hardware program breakpoint processing module is used for the hardware program breakpoint setup order save routine breakpoint address after according to parsing, and when reading the instruction of this breakpoint address when described processor 3 moves to this breakpoint address, the presumptive instruction at breakpoint address place is replaced with special instruction, so that described processor unit 3 is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Described hardware program breakpoint processing module is also for deleting corresponding program breakpoint address according to the hardware program breakpoint clear command after parsing;
Hardware data breakpoint processing module is used for the hardware data breakpoint command after according to parsing and preserves or the breakpoint address that clears data, and send specific interruption when described processor 3 reads or writes described breakpoint address to processor unit 3, so that processor 3 is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Described hardware data breakpoint processing module is also for deleting corresponding data breakpoint address according to the hardware data breakpoint clear command after parsing;
Program halt processing module is used for the program halt order after according to parsing and sends specific interruption to described processor unit 3, so that described processor 3 is directed to specific debugged program, and other debug command of wait out of service at once;
Program circuit tracing module is used for the address of the instruction stream of the program circuit tracer command monitoring after according to parsing and the reading of specimens preserving device unit 3, and transfers to external bus controller 2 after being compressed, so that commissioning device 4 obtains the instruction stream of tracked program.
Particularly, after the on-chip bus controller 1 of embedded debugging module receives the physical address space read write command that commissioning device 4 inputted by external bus controller 2, debug command resolution unit can be resolved physical address space read write command, then the physical address space module for reading and writing debugged in performance element 12 can trigger on-chip bus controller 1 according to the physical address space read write command after parsing and carry out read-write motion, physical address space module for reading and writing can monitor the read-write motion of on-chip bus controller 1, and read-write result is sent to external bus controller 2 by on-chip bus controller 1 again with the form of byte stream, commissioning device 4 is transferred to make external bus controller 2, be convenient to user or commissioning device 4 and carry out next step debugging according to Output rusults.
After the on-chip bus controller 1 of embedded debugging module receives the hardware program breakpoint setup order that commissioning device 4 inputted by external bus controller 2, debug command resolution unit 11 can be resolved the order of hardware program breakpoint setup, then the hardware program breakpoint processing module of debugging in performance element 12 can preserve the address of the breakpoint in the order of hardware program breakpoint setup, what then hardware program breakpoint processing module can monitor processor 3 reads designated command, when the address of reading designated command of processor 3 is these breakpoint address, hardware program breakpoint processing module can adopt break-poing instruction or other self-trapping instruction or jump instruction to replace the presumptive instruction at breakpoint address place, when performing this breakpoint to make processor 3, processor 3 is directed to specific debugged program by break-poing instruction or other self-trapping instruction or jump instruction, normally run to make program stopped and wait for other debug command.
Processor 3 performs instruction according to preset order, after inserting break-poing instruction in the execution instruction at processor 3, processor 3 can interrupt performing present procedure, then perform the debugged program of break-poing instruction guiding, now processor 3 can stop normal operation to enter debugging mode, and user or commissioning device 4 can be debugged the situation of internal memory of such as checking, the state of register by other debug command to embedded system and check the operations such as source code.
After debugging, user or commissioning device 4 can send hardware program breakpoint clear command to on-chip bus controller 1, after on-chip bus controller 1 receives hardware program breakpoint clear command, debug command resolution unit 11 can be resolved hardware program breakpoint clear command, hardware program breakpoint processing module in debugging performance element 12 can remove corresponding program breakpoint address, and stop this program breakpoint address of monitoring, namely hardware program breakpoint processing module can stop at the presumptive instruction of replacing breakpoint place when processor 3 reads this program breakpoint address, processor 3 is made to perform instruction according to former order.
Equally, after on-chip bus controller 1 receives the order of hardware data breakpoint setup, debug command resolution unit 11 can be resolved the order of hardware data breakpoint setup, then the hardware data breakpoint processing module of debugging in performance element 12 can preserve the data breakpoint address in the order of hardware data breakpoint setup, then hardware data breakpoint processing module root can monitor the order that reads and writes data of processor 3, when the address of the order that reads and writes data of processor 3 is these data breakpoint addresses, hardware data breakpoint processing module can send specific interruption such as non-maskable interruption NMI, specific debugged program is directed into make processor 3, stop normally running and waiting for other debug command.After debugging, processor 3 can exit and interrupts and exit debugged program, and is interrupted from present procedure and brings into operation.
For the processor 3 having instruction buffer, because instruction buffer may save the presumptive instruction at breakpoint place, hardware program breakpoint setup and removing may be invalid, based on this, cleaning instruction buffer function can be increased in debugged program, when processor 3 present procedure interrupt run, the instruction buffer of removing breakpoint address is assisted by debugged program, equally, when receiving removing Hardware Breakpoint order, the instruction buffer of removing breakpoint address is also assisted by debugged program.
For the processor 3 not having instruction buffer, after on-chip bus controller 1 receives the order of program circuit tracking, debug command resolution unit 11 can resolve program circuit tracer command, and the instruction flow of the tracking of acquisition can be sent to external bus controller 2 according to the address of reading instruction of the program circuit tracer command monitoring after resolving and specimens preserving device by the program circuit tracing module in debugging performance element 12 after simple compression.
After on-chip bus controller 1 receives program halt order, debug command resolution unit 11 can be resolved program halt order, then debug program halt processing module in performance element 12 to send a specific interruption as not maskable interrupts NMI according to the program halt order after resolving to processor 3 and shield other and interrupt, make processor 3 present procedure out of service, and processor 3 is directed to specific debugged program, make processor 3 enter debugging mode and wait for that other debug command that user or commissioning device 4 input is debugged.
Debugged program in the present embodiment is the debugged program of the solidification of on-chip bus controller 1 inside, the embedded debugging module of on-chip bus controller 1 can remap interrupt vector and debugged program address space, processor 3 is directed to the solidification debugged program of itself inline.
In addition, on-chip bus controller 1 in the present embodiment can also send specific debug bus waveform, with specific debugging interface and the jtag interface communication of processor 3, to realize the functions such as program halt, hardware single step, program circuit tracking, when there is data buffering or instruction buffer etc., making to realize these functions in this way can be more accurate.
The debug system that the present embodiment provides, embedded debugging module on the on-chip bus controller be connected with the processor of embedded system, thus can be debugged the software in described embedded system by on-chip bus controller, and then no longer need to configure special emulator, and, remote debugging can also be realized by universal external bus controller connecting Internet, make embedded systems debugging convenient.
Embodiments of the invention additionally provide a kind of adjustment method, are applied to the debug system that above-described embodiment provides, and as shown in Figure 3, this adjustment method comprises:
S301: the debugging module of on-chip bus controller is resolved the debug command received;
S302: the debugging module of on-chip bus controller performs corresponding debug action according to the debug command after parsing.
Further, as shown in Figure 4, this adjustment method can comprise:
S401: on-chip bus controller receives the debug command of commissioning device input by external bus controller;
S402: the embedded debugging module of on-chip bus controller is resolved the debug command received;
S403: the embedded debugging module of on-chip bus controller performs corresponding debug action according to the debug command after resolving;
S304: debug results is transferred to described commissioning device by described external bus controller by on-chip bus controller.
Wherein, perform corresponding debug action according to the debug command after described parsing to comprise:
Carry out read-write motion according to the physical address space read write command triggering on-chip bus controller after resolving, and the read-write result of on-chip bus controller is transferred to external bus controller;
According to the hardware program breakpoint setup order save routine breakpoint address after parsing, and when reading the instruction of this breakpoint address when described processor unit moves to this breakpoint address, the presumptive instruction at breakpoint address place is replaced with special instruction, so that described processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Data breakpoint address is preserved according to the hardware data breakpoint setup order after resolving, and send specific interruption when described processor unit reads or writes described breakpoint address to processor unit, so that processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Delete corresponding program breakpoint address according to the hardware program breakpoint clear command after resolving, also namely stop at the presumptive instruction of replacing described breakpoint address place when described processor unit moves to described breakpoint address;
Delete corresponding data breakpoint address according to the hardware data breakpoint clear command after resolving, also namely stop at when described processor unit reads described breakpoint address and produce specific interruption;
Specific interruption is sent to described processor unit according to the program halt order after resolving, so that described processor unit is directed to specific debugged program, other debug command of wait out of service at once;
According to the address of the instruction stream that the program circuit tracer command monitoring after parsing and specimens preserving device unit are read, and transfer to external bus controller after being compressed, so that commissioning device obtains the instruction stream of tracked program.
Particularly, after on-chip bus controller receives the physical address space read write command that commissioning device inputted by external bus controller, debug command resolution unit can be resolved physical address space read write command, then the physical address space module for reading and writing debugged in performance element can trigger on-chip bus controller according to the physical address space read write command after parsing and carry out read-write motion, physical address space module for reading and writing can monitor the read-write motion of on-chip bus controller, and read-write result is sent to external bus controller with the form of byte stream, commissioning device is transferred to make external bus controller, be convenient to user or commissioning device and carry out next step debugging according to Output rusults.
When on-chip bus controller receive that commissioning device inputted by external bus controller hardware program breakpoint command is set after, debug command resolution unit can be resolved arranging hardware program breakpoint command, then the breakpoint processing module of debugging in performance element can preserve the address of the breakpoint arranged in hardware program breakpoint command, what then breakpoint processing module can monitor processor reads designated command, when the address of reading designated command of processor is this breakpoint address, breakpoint processing module can adopt break-poing instruction or other self-trapping instruction or jump instruction to replace the presumptive instruction at breakpoint place, when performing this breakpoint to make processor, processor is directed to specific debugged program by break-poing instruction or other self-trapping instruction or jump instruction, normally run to make program stopped and wait for other debug command.
After debugging, user or commissioning device can send to the embedded debugging module of on-chip bus controller removes breakpoint command, after the embedded debugging module of on-chip bus controller receives removing breakpoint command, debug command resolution unit can be resolved removing breakpoint command, breakpoint processing module in debugging performance element can remove the address of breakpoint, and stop this breakpoint address of monitoring, make processor perform instruction according to former order.
Equally, after on-chip bus controller receives and arranges hardware data breakpoint command, debug command resolution unit can be resolved arranging hardware data breakpoint command, then the breakpoint processing module of debugging in performance element can preserve the address of the breakpoint arranged in hardware data breakpoint command, then breakpoint processing module is according to the order reading or writing data arranging hardware data breakpoint command monitoring processor after parsing, when processor reads or writes this breakpoint address, breakpoint processing module can send specific interruption such as non-maskable interruption NMI, so that processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command.After debugging, processor can exit interruption, brings into operation from present procedure interruptions.
After on-chip bus controller receives program halt order, debug command resolution unit can be resolved program halt order, then debug program halt processing module in performance element to send a specific interruption as not maskable interrupts NMI according to the program halt order after resolving to processor and shield other and interrupt, make processor present procedure out of service, and processor is directed to specific debugged program, make processor enter debugging mode and wait for that the debug command of user or commissioning device input is debugged.
The adjustment method that the present embodiment provides, the on-chip bus controller be connected with the processor unit of embedded system adds debug function, thus can by on-chip bus controller and the universal external be attached thereto bus controller as UART, SPI, Ethernet, USB etc. to as described in embedded system or software debug, and then no longer need to configure special emulator, and, if the direct or indirect accessing Internet of universal external bus controller, can also realize remote debugging easily.。
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.For device disclosed in embodiment, because it corresponds to the method disclosed in Example, so description is fairly simple, relevant part illustrates see method part.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a debug system, is characterized in that, comprises the on-chip bus controller being embedded with debugging module and at least one external bus controller be connected with described on-chip bus controller;
External bus controller described in each is connected with a commissioning device, different described external bus controllers is by different communication modes and described commissioning device communication, described external bus controller is used for the debug command that described commissioning device inputs to transfer to described on-chip bus controller, and the debug results that described on-chip bus controller exports is transferred to described commissioning device;
Described on-chip bus controller is connected with the processor unit of embedded system, the embedded debugging module of described on-chip bus controller is used for resolving described debug command after the debug command receiving arbitrary described external bus controller input, and performs corresponding debug action according to the debug command after described parsing.
2. debug system according to claim 1, is characterized in that, described debugging module comprises communication control unit, debug command resolution unit and debugging performance element;
Described debug command for receiving the debug command of described external bus controller input, and is transferred to described debug command resolution unit by described communication control unit, and debug results is transferred to described external bus controller;
Described debug command resolution unit is used for resolving described debug command according to preset format, and the debug command after resolving is transferred to described debugging performance element;
Described debugging performance element triggers corresponding debug function module according to the debug command after described parsing and performs corresponding debugging operations.
3. debug system according to claim 2, it is characterized in that, the debug function module in described debugging performance element comprises physical address space module for reading and writing, hardware program breakpoint processing module, hardware data breakpoint processing module, program halt processing module and program circuit tracing module;
Described physical address space module for reading and writing is used for the read-write motion that the physical address space read write command after according to parsing triggers on-chip bus controller, and by described communication control unit, the read-write result of on-chip bus controller is transferred to described external bus controller;
Described hardware program breakpoint processing module is used for the hardware program breakpoint setup order save routine breakpoint address after according to parsing, and when described processor unit reads the instruction of described breakpoint address, the presumptive instruction at described breakpoint address place is replaced with special instruction, so that described processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Described hardware program breakpoint processing module is also for deleting corresponding program breakpoint address according to the hardware program breakpoint clear command after parsing;
Described hardware data breakpoint processing module is used for the hardware data breakpoint setup order after according to parsing and preserves data breakpoint address, and send specific interruption when described processor unit reads or writes described breakpoint address to described processor unit, so that described processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Described hardware data breakpoint processing module is also for deleting corresponding data breakpoint address according to the hardware data breakpoint clear command after parsing;
Described program halt processing module is used for the program halt order after according to parsing and sends specific interruption to described processor unit, so that described processor unit is directed to specific debugged program, and other debug command of wait out of service at once;
Described program circuit tracing module is used for the program circuit tracer command monitoring after according to parsing and preserves the address of the instruction stream that described processor unit reads, and transfer to described external bus controller after being compressed, so that described commissioning device obtains the instruction stream of tracked program.
4. debug system according to claim 1, it is characterized in that, described on-chip bus controller is connected by input/output bus on sheet with described external bus controller, carries out the transmission of data between described on-chip bus controller and described external bus controller in the mode of two-way byte stream.
5. debug system according to claim 1, is characterized in that, described on-chip bus controller is connected with described processor unit with proprietary debugging interface by the system bus interface of described processor unit, NMI interrupt signal interface simultaneously.
6. debug system according to claim 1, is characterized in that, described external bus controller is connected with described commissioning device by UART serial ports, SPI serial ports, USB interface or Ethernet interface.
7. an adjustment method, is characterized in that, is applied to the debug system described in any one of claim 1 ~ 6, and described adjustment method comprises:
The embedded debugging module of on-chip bus controller is resolved the debug command received;
The embedded debugging module of described on-chip bus controller performs corresponding debug action according to the debug command after described parsing.
8. adjustment method according to claim 7, is characterized in that, described on-chip bus controller also comprises before resolving the debug command received:
The embedded debugging module of described on-chip bus controller receives the debug command of commissioning device input by external bus controller.
9. adjustment method according to claim 8, is characterized in that, also comprises after performing corresponding debug action according to the debug command after described parsing:
Debug results is transferred to described commissioning device by described external bus controller by the embedded debugging module of described on-chip bus controller.
10. adjustment method according to claim 9, is characterized in that, performs corresponding debug action comprise according to the debug command after described parsing:
Trigger described on-chip bus controller according to the physical address space read write command after parsing and carry out read-write motion, and the read-write result of described on-chip bus controller is transferred to described external bus controller;
According to the hardware program breakpoint setup order save routine breakpoint address after parsing, and when described processor unit reads the instruction of described breakpoint address, the presumptive instruction at described breakpoint address place is replaced with special instruction, so that described processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Data breakpoint address is preserved according to the hardware data breakpoint setup order after resolving, and send specific interruption when described processor unit reads or writes described breakpoint address to described processor unit, so that described processor unit is directed to specific debugged program, at once stop normally running and waiting for other debug command;
Corresponding program breakpoint address is deleted according to the hardware program breakpoint clear command after resolving;
Corresponding data breakpoint address is deleted according to the hardware data breakpoint clear command after resolving;
Specific interruption is sent to described processor unit according to the program halt order after resolving, so that described processor unit is directed to specific debugged program, other debug command of wait out of service at once;
According to the program circuit tracer command monitoring after parsing and the address of preserving the instruction stream that described processor unit reads, and transfer to described external bus controller by after the address compression of described instruction stream, so that described commissioning device obtains the instruction stream of tracked program.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610057410.9A CN105550118B (en) | 2016-01-27 | 2016-01-27 | Debugging system and adjustment method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610057410.9A CN105550118B (en) | 2016-01-27 | 2016-01-27 | Debugging system and adjustment method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105550118A true CN105550118A (en) | 2016-05-04 |
| CN105550118B CN105550118B (en) | 2018-01-30 |
Family
ID=55829312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610057410.9A Active CN105550118B (en) | 2016-01-27 | 2016-01-27 | Debugging system and adjustment method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105550118B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106201649A (en) * | 2016-06-29 | 2016-12-07 | 武汉电信器件有限公司 | Virtual machine for optical module monitoring |
| CN107450512A (en) * | 2017-07-24 | 2017-12-08 | 核动力运行研究所 | A kind of system and method for the access of nuclear power station DCS controller states |
| CN108361918A (en) * | 2018-03-20 | 2018-08-03 | 奥克斯空调股份有限公司 | Debugging air conditioner device, method and air conditioner |
| CN109857642A (en) * | 2018-12-30 | 2019-06-07 | 贝壳技术有限公司 | A kind of the block type adjustment method and debugging tool of UI automatized script |
| CN111176997A (en) * | 2019-12-25 | 2020-05-19 | 珠海格力电器股份有限公司 | Generalized parameter management system and parameter management method |
| CN112565036A (en) * | 2020-11-24 | 2021-03-26 | 炬芯科技股份有限公司 | Data transmission method, device, storage medium and communication system |
| CN113454607A (en) * | 2019-03-21 | 2021-09-28 | 杭州飞步科技有限公司 | Debugging method and device and system on chip |
| CN113590470A (en) * | 2021-06-30 | 2021-11-02 | 龙芯中科(成都)技术有限公司 | Software debugging method and device, electronic equipment and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1779653A (en) * | 2004-11-26 | 2006-05-31 | 上海芯华微电子有限公司 | Debugging device for on-chip system |
| CN101042815A (en) * | 2007-01-19 | 2007-09-26 | 华南理工大学 | Single chip computer teaching experimental device based on on-line programmable logic device |
| CN102129408A (en) * | 2011-04-14 | 2011-07-20 | 电子科技大学 | Record playback technology-based embedded software debugging device and method |
| CN102968364A (en) * | 2012-11-16 | 2013-03-13 | 中国航天科技集团公司第九研究院第七七一研究所 | Universal debugging interface-based SoC (System on Chip) hardware debugger |
| CN104834587A (en) * | 2014-02-11 | 2015-08-12 | 珠海格力电器股份有限公司 | RS-485 bus slave computer online debugging method and system |
| CN205375453U (en) * | 2016-01-27 | 2016-07-06 | 珠海格力电器股份有限公司 | Debug system |
-
2016
- 2016-01-27 CN CN201610057410.9A patent/CN105550118B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1779653A (en) * | 2004-11-26 | 2006-05-31 | 上海芯华微电子有限公司 | Debugging device for on-chip system |
| CN101042815A (en) * | 2007-01-19 | 2007-09-26 | 华南理工大学 | Single chip computer teaching experimental device based on on-line programmable logic device |
| CN102129408A (en) * | 2011-04-14 | 2011-07-20 | 电子科技大学 | Record playback technology-based embedded software debugging device and method |
| CN102968364A (en) * | 2012-11-16 | 2013-03-13 | 中国航天科技集团公司第九研究院第七七一研究所 | Universal debugging interface-based SoC (System on Chip) hardware debugger |
| CN104834587A (en) * | 2014-02-11 | 2015-08-12 | 珠海格力电器股份有限公司 | RS-485 bus slave computer online debugging method and system |
| CN205375453U (en) * | 2016-01-27 | 2016-07-06 | 珠海格力电器股份有限公司 | Debug system |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106201649A (en) * | 2016-06-29 | 2016-12-07 | 武汉电信器件有限公司 | Virtual machine for optical module monitoring |
| CN106201649B (en) * | 2016-06-29 | 2019-05-03 | 武汉电信器件有限公司 | Virtual machine for optical module monitoring |
| CN107450512A (en) * | 2017-07-24 | 2017-12-08 | 核动力运行研究所 | A kind of system and method for the access of nuclear power station DCS controller states |
| CN108361918A (en) * | 2018-03-20 | 2018-08-03 | 奥克斯空调股份有限公司 | Debugging air conditioner device, method and air conditioner |
| CN109857642A (en) * | 2018-12-30 | 2019-06-07 | 贝壳技术有限公司 | A kind of the block type adjustment method and debugging tool of UI automatized script |
| CN113454607A (en) * | 2019-03-21 | 2021-09-28 | 杭州飞步科技有限公司 | Debugging method and device and system on chip |
| CN113454607B (en) * | 2019-03-21 | 2023-08-22 | 杭州飞步科技有限公司 | Debugging method, device and system-on-chip |
| CN111176997A (en) * | 2019-12-25 | 2020-05-19 | 珠海格力电器股份有限公司 | Generalized parameter management system and parameter management method |
| CN112565036A (en) * | 2020-11-24 | 2021-03-26 | 炬芯科技股份有限公司 | Data transmission method, device, storage medium and communication system |
| CN112565036B (en) * | 2020-11-24 | 2022-08-30 | 炬芯科技股份有限公司 | Data transmission method, device, storage medium and communication system |
| CN113590470A (en) * | 2021-06-30 | 2021-11-02 | 龙芯中科(成都)技术有限公司 | Software debugging method and device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105550118B (en) | 2018-01-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105550118A (en) | Debugging system and debugging method | |
| CN109800159B (en) | Program debugging method, program debugging device, terminal device, and storage medium | |
| EP1754156B1 (en) | Data processing system with trace co-processor | |
| Mera et al. | DICE: Automatic emulation of DMA input channels for dynamic firmware analysis | |
| US9852038B2 (en) | Debugging system and debugging method of multi-core processor | |
| CN101154183B (en) | Microcontroller built-in type on-line simulation debugging system | |
| US6598178B1 (en) | Peripheral breakpoint signaler | |
| KR101519845B1 (en) | Method For Anti-Debugging | |
| KR20180057687A (en) | Debugging method, multi-core processor, and debugging equipment | |
| CN101084485A (en) | Apparatus and method for improving emulation speed of high-level languages in on-chip emulation systems | |
| CN102508753A (en) | IP (Internet protocol) core verification system | |
| Li et al. | μAFL: non-intrusive feedback-driven fuzzing for microcontroller firmware | |
| CN101482848A (en) | Dynamic debugging method and system in embedded software running state | |
| CN105740139B (en) | A kind of debugging embedded software method based on virtual environment | |
| CN111367742A (en) | Method, device, terminal and computer readable storage medium for debugging MVP processor | |
| CN205375453U (en) | Debug system | |
| CN100474266C (en) | Debugging system used for digital signal processor and debug method thereof | |
| US5903719A (en) | Emulator apparatus and emulation method for efficiently analyzing program faults | |
| CN114265786A (en) | Automatic testing method and device, computer equipment and readable storage medium | |
| Gui et al. | Firmnano: Toward iot firmware fuzzing through augmented virtual execution | |
| CN112015649A (en) | Method for debugging main computation core by using on-chip co-computation core | |
| KR20050063023A (en) | Embedded system debugger based on jtag interface and the method | |
| Hu et al. | Applications of on-chip trace on debugging embedded processor | |
| Li et al. | Research of “Stub” remote debugging technique | |
| Shilaskar et al. | Post Silicon Validation for I2C (SMBUS) Peripheral |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |