CN101042815A - Single chip computer teaching experimental device based on on-line programmable logic device - Google Patents
Single chip computer teaching experimental device based on on-line programmable logic device Download PDFInfo
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Abstract
This invention discloses one single machine teaching experiment device based on online programmable logic parts, which comprises micro controller, keyboard display module, digital analogue I/O unit, programmable logic part ispLST, memory unit, load operation control unit and modulation environment host, wherein, micro controller is connected to each function modules through bus and double I/O terminals and the teaching experiment device and modulation environment host adopt series interface for connection.
Description
Technical field
The present invention relates to a kind of single chip computer teaching, relate in particular to a kind of multi-functional embedded scm experiment device for teaching based on programmed logic device able to programme; Be specifically related to a kind of have one-chip machine simulation, ispLSI programming and the integrated Single Chip Microcomputer (SCM) system functional module elements commonly used and the teaching experiment system of various communication interfaces.
Background technology
Microcontroller MCU grows up on single-chip computing machine (the domestic single-chip microcomputer that is commonly called as) ideal basis, be with microprocessor and peripheral circuit thereof, Peripheral Interfaces etc. are integrated to be produced in the same chip, need not other auxiliary circuit supports and can independently finish computing, amplify, the integrated circuit of work such as processing, has excellent peripheral interface control function, be easy to constitute various industry controls, adaptive control, systems such as data acquisition, and digitizing, intelligent, electromechanical integrated product of new generation such as multifunction, and can be in large-scale TT﹠C system and the main frame concurrent working, improve system speed.
8 MCU and 32 two big pillars that MCU is the MCU industry, because 8 MCU systems have high cost performance, 8 MCU will be the mainstream models of MCU system applies in foreseeable period in future, still have huge development space at present.Recent statistics data representation in 2006, the delivering amount of 8 MCU continues held stationary, and the summation of comparing 16 and 32 is also many, and it accounts for more than 60% of total amount.
The typical chip of tool is the MCU chip of the various models of compatibility standard MCS-51 order set among 8 MCU, therefore MCS-51 principle and using also becomes the MCU of the school classical content of imparting knowledge to students, study MCU can not talk about stratagems on paper, and traditional for a long time MCU education experiment developing instrument just becomes the barrier that numerous teachers and students, beginner and slip-stick artist learn to develop always.It is breakboard construction that study MCU at first will have experimental subjects.And the making of a regular breakboard construction of finishing, at first need the design from schematic diagram, the buying (retail is hard to buy and is expensive) of element, design and tailor-made the setting about of PCB, so just expend certain man power and material, secondly the developing instrument that will use in debug process is exactly an emulator, the emulator price of specialty is all more than 1500, and the result that obtains of emulation and have certain deviation toward contact in the result of the goal systems operation of reality.In addition, emulator can not the memory write chip, must buy programmable device and come the memory write chip, these instruments not only spend greatly, relation between the various developing instruments all is difficult to put in order for the student of first study MCU, because class hour is limited, many students are until this End-of-Course is also failed on top of relation between these instruments and using method.Be exactly that traditional MCU education experiment developing instrument often will plug artificial head more again, plug cpu chip, memory write chip, not only process is loaded down with trivial details, and damage developing instrument easily, goal systems and integrated circuit (IC) chip.
Learn according to my MCU many years'teaching experience with the situation that exchanges between going together, in the teaching and experiment of MCU, teachers and students wish to have a kind of simple, quick, true incorporate MCU embedded developping system that also is fit to education experiment, do not need emulator, do not need this class instrument of programmable device yet, whole education experiment process is oversimplified, and makes the student can concentrate one's energy to concentrate on crucial points.
Summary of the invention
The objective of the invention is in order to overcome the shortcoming of prior art, provide a kind of MCU learning board, brassboard, development board, programmable device, emulator, at the incorporate experiment device for teaching of system debug.This device has programmable gate array circuit ispLSI learning board function concurrently.
Purpose of the present invention is achieved through the following technical solutions:
Based on the single chip computer teaching experimental provision of online programmable logical device, comprise microcontroller MCU1, keyboard display module 2, hard serial ports 3, soft serial ports 4, Ethernet interface 5, USB/I
2C/SPI interface 6, digital analog I/O unit 7, in-system programmable logical device ispLSI 8, calendar clock unit 9, memory cell 10, loading operation control module 11 and power module 12 constitute; Described keyboard display module 2 connects P1.3 and the INT0 port of microcontroller MCU1, and described hard serial ports 3 connects RXD and the TXD port of microcontroller MCU1, and described soft serial ports 4 connects P4.0 and the INT1 port of microcontroller MCU1, Ethernet interface 5, USB/I
2C/SPI interface 6, digital analog I/O unit 7, calendar clock unit 9 are connected the system bus of microcontroller MCU1 with memory cell 10, described programmable logic device (PLD) ispLSI 8 finishes the logic control in the system and simplifies peripheral circuit in the single-chip microcomputer, described loading operation control module 11 connects EA and the RST port of microcontroller MCU1, described microcontroller chip inside is provided with watchdog routine, also embedded the programming software of programmable logic device (PLD) ispLSI 8, realized online programming and study the programmable gate array circuit.
It is MCU SM5964 that microcontroller 1 of the present invention adopts model, it is the High Speed Microcontroller chip with 80C51 order set compatibility, have the SM5964 of 44 pin PLCC encapsulation specification and the 80C52 of standard and compare, increased P4.0～P4.3 totally 4 two-way I/O ports.There are the FLASH program storage of 64KB and the RAM data-carrier store of 1KB in described microcontroller MCUSM5964 inside, the FLASH program storage has watchdog routine of the present invention, watchdog routine takies the FLASH storer less than 32KB, because the FLASH storer of SM5964 inside has the ISP function, so watchdog routine also can be passed through serial ports, port, the upgrading of USB mouth.When the EA pin of microcontroller MCU SM5964 when being high, start the watchdog routine of inner FLASH storer, watchdog routine is finished following task at least: the 1) register of the inside of initialization SM5964; 2) soft serial ports is set and receives interruption; 3) receive command packet and the parsing that the debugging enironment main frame is sent; 4) carry out the corresponding command, return execution result and give the debugging enironment main frame.5) receive command packet, parsing, the execution of sending, return execution result to communication interface by various communication interfaces; 6) watchdog routine among the upgrading MCU SM5964; 7) user program among the renewal external memory storage SRAM62C256; 8) program of online programming ispLSI device; 9) initialization of network chip (NIC), and disposed the ICP/IP protocol stack of simplifying.
Adopt soft serial ports connected mode between keyboard display module 2 of the present invention and the microcontroller MCU SM5964 1, described display is eight sections charactron dynamic displays of position common cathode, keyboard is a ranks matrix form nonencoded keyboard, 4 * 4 matrixes, 16 key boards are respectively numeral [0]～[9], [], [+], [function], [affirmation], [cancellation], [statistics].Keyboard display module 2 can be used as the man-machine interface of MCU multifunction teaching test device, finish the input and the output of information, can be used for being provided with real-time calendar clock, operational factor is set, imports startup password, job number and the amount of consumption as " dining room/supermarket charging terminal " keyboard, display is used to indicate key information, statistical value etc.
Embedded the programming software of programmable logic device (PLD) ispLSI 8 in the FLASH program storage of microcontroller MCU SM5964 1 inside among the present invention, realized online programming ispLSI.Described loading operation control module 11 is made up of basic rest-set flip-flop and NAND gate circuit, by the EA port of basic rest-set flip-flop control SM5964, realizes the switching of watchdog routine and user program.
The communication interface and the mode of the comprehensive debugging instrument among the present invention can be selected: serial ports, Modem, TCP and UDP.Serial mode is represented Solarnumen Comdebug, and string slogan, baud rate need be set; Modem represents the Modem debugging acid, except that string slogan, baud rate are set, also the called phone number will be set.Back dual mode is the network debugging acid, and far-end IP address and port numbers need be set.
With respect to prior art, the invention has the beneficial effects as follows:
(1) experiment device for teaching is a core with the MCU SM5964 of 80C52 kernel, peripheral expansion present functional module, communication interface and complicated programmable logic device (PLD) ispLSI commonly used in the single chip computer teaching experiment.Can realize that artificial debugging, chip programming, education experiment and program loading are integrated, the application software of debugging leaves among the SRAM, writing speed is fast, erasable number of times is unlimited, function with ROM emulation and CPU emulation, wherein CPU emulation have single step, stride, at full speed, debug function such as breakpoint, read-write DATA/CODE/XDATA/SFR, emulation CPU is exactly goal systems CPU, need not plug, can effectively reduce the experiment device for teaching failure rate.The present invention has realized online program design and function debugging in the embedded development mode.
(2) adopt online programmable logical device ispLSI in the experiment device for teaching, untapped I/O pin is all drawn among the ispLSI.Use ispLSI not only to simplify circuit design, reduce cost, can also learn brassboard as programmable logic device (PLD).
Description of drawings
Fig. 1 is the schematic appearance of single chip computer teaching experimental provision of the present invention;
Fig. 2 is the composition frame chart of single chip computer teaching experimental provision of the present invention;
Fig. 3 is CPU, loading operation control and the ispLSI unit schematic diagram of single chip computer teaching experimental provision;
Fig. 4 is storer principle, the calendar clock unit schematic diagram of single chip computer teaching experimental provision of the present invention;
Fig. 5 is the hard serial ports of single chip computer teaching experimental provision of the present invention, soft serial ports schematic diagram;
Fig. 6 uses the single chip computer teaching experimental provision to download HEX, BIN and JEDEC document flowchart.
Embodiment
The invention will be further described in conjunction with Figure of description below by embodiment, but the scope of protection of present invention is not limited to the scope of embodiment statement.
As shown in Figure 2, single chip computer teaching device of the present invention is by microcontroller MCU SM5964 1, keyboard display module 2, hard serial ports 3, soft serial ports 4, Ethernet interface 5, USB/I
2C/SPI interface 6, digital analog I/O unit 7, programmable logic device (PLD) ispLSI 8, calendar clock unit 9, memory cell 10, loading operation control module 11 and power module 12 constitute, keyboard display module 2 connected modes are connected to P1.3 and the INT0 port of microcontroller MCU SM5964 1, its level is a Transistor-Transistor Logic level, described display is 8 common cathodes, eight hop count sign indicating number dynamic displays, keyboard is a ranks matrix form nonencoded keyboard, 4 * 4 matrixes, 16 key boards; Hard serial ports 3 connects RXD, the TXD port of microcontroller MCU SM5964 1, and soft serial ports 4 connects P4.0 and the INT1 port of microcontroller MCU SM5964 1; Soft serial ports 4 and hard communicating to connect of serial ports 3 can be realized the CPU artificial debugging, possess whole hardware debug functions that Keil C51 (the C lingware of 51 series monolithics and compatible thereof develops software) is provided.Ethernet interface 5, USB interface 6, digital analog I/O unit 7, calendar clock unit 9 are connected the system bus of microcontroller MCU SM5964 1 with memory cell 10; Programmable logic device (PLD) ispLSI 8 finishes logic control in the system and simplifies peripheral circuit in the single-chip microcomputer; Load EA and RST port that operation control module 11 connects microcontroller MCUSM5964 1, watchdog routine is contained in described microcontroller chip inside, also embedded the programming software of programmable logic device (PLD) ispLSI 8, realized online programming and study the programmable gate array circuit.Power module 12 provides power supply for each module of single chip computer teaching device.
Fig. 3 is microcontroller MCU of the present invention, loads and move control and ispLSI unit schematic diagram that U3 is CPU among the figure, and model is MCU SM5964, but realization of the present invention is not limited thereto the selection of kind of model.U6 is ispLSI, and model is ispLSI 1032, but realization of the present invention is not limited thereto the selection of kind of model.Experiment device for teaching has two kinds of mode of operations: LOAD pattern and RUN pattern, realize by loading operation control module 11.
If click [LOAD] key, U7 the 8th pin is changed to high level, connect the EA pin of SM5964, U7 the 6th pin produces high reset signal simultaneously, experiment device for teaching switches to the LOAD pattern, under the LOAD pattern, the watchdog routine in the experiment device for teaching operation SM5964 in-chip FLASH, watchdog routine has two functions at least after finishing initialization: 1) HEX file and the BIN file that the debugging enironment main frame descended to pass write SRAM 62C256; 2) or the JEDEC file that the debugging enironment main frame descended to pass write ispLSI1032.
If click [RUN] key, U7 the 8th pin is changed to low level, connects the EA pin of SM5964, and U7 the 6th pin produces high reset signal simultaneously, and experiment device for teaching switches to the RUN pattern, under the RUN pattern, and the program among the experiment device for teaching operation SRAM 62C256.
It is as follows that the JEDEC file writes principles illustrated: under the LOAD pattern, U7 the 11st pin is changed to low level, two-way electronic analog swtich 74HC4066 connects, U1:SM5964 is connected to SCLK, MODE, SDI and the SDO pin of ispLSI1032 by P4.0～P4.3 correspondence, the ispEN of ispLSI1032 is a low level, all I/O mouths of ispLSI1032 are high-impedance state, allow chip ispLSI1032 is programmed.MODE is a mode control signal, and SCLK is the serial clock input, and it imports the shift register of data for acceptance in the sheet and the sequential logical circuit of control programming operation provides clock signal.SDI is serial data and command input end, and SDO is the serial data output terminal.Embed the programming software of ispLSI in the SM5964 in-chip FLASH.
Fig. 4 is memory cell of the present invention and calendar clock unit schematic diagram, as shown in Figure 4, U9:62C256 is a 32KB SRAM storer, the memory headroom address is 0000H～7FFFH, PSEN and RD with after connect U9 the 27th pin OE control end, the 62C256 reservoir designs is that von Neumann connects, and is used to deposit the user program of needs debugging or the Mon51.HEX of Keil C51.DS12C887 is a calendar clock chip, and time reference is provided, and AT24C256 is for having I
2The serial EEPROM nonvolatile memory of 32 * 8Kb of C bus interface provides the data recording space.
As shown in Figure 1, the single chip computer teaching experimental provision based on the online programmable logical device provided by the invention is connected with debugging enironment main frame 13, and connecting communication interface can be soft serial ports, hard serial ports, USB mouth or port.Fig. 5 is the schematic diagram of the hard serial ports of the present invention, soft serial ports, and under CPU artificial debugging mode, debugging enironment main frame 13 must be connected to the soft serial ports of experiment device for teaching, and the soft serial ports of device uses the external interrupt INT1 Monitoring Data input of MCU.Under ROM artificial debugging mode, it is one of any that debugging enironment main frame 13 can be connected to the soft serial ports of experiment device for teaching, hard serial ports, USB mouth or port, and the user's download program that cooperates debugging enironment main frame of the present invention to be installed can realize the ROM artificial debugging.Fig. 6 is that the present invention downloads HEX, BIN and JEDEC document flowchart.Click [LOAD] button, device starts the internal control program.Software ComView sends order in the debugging enironment main frame, and command word=0x11 indicates down to pass the HEX file; Command word=0x12 indicates down to pass the BIN file; Command word=0x13 indicates down to pass the JEDEC file; Command word=0x14 indicates to read the program BIN code among the SRAM62256; Command word=0x15 indicates to read the JEDEC code among the ispLSI.
Embodiment 1-CPU artificial debugging mode:
1, in Fig. 1, press [LOAD] button, experiment device for teaching resets, and starts watchdog routine in MCUSM5964 1 in-chip FLASH simultaneously.At this moment the surface of experiment device for teaching is that the red led of (1) [LOAD] button top is bright; (2) 8 of keyboard display module 28 sections light-emitting diode displays show " 8. " with " a lantern adorned with a revolving circle of paper horses " form.
2, start 13 installed software ComView of debugging enironment main frame of the present invention, select to communicate to connect mode and baud rate, select MONINT1.Hex, MONINT1.Hex is the watchdog routine of CPU simulation model, and the address space that takies is less than 5KB.The file of selecting is downloaded to 0000H address in the storer 10 (SRAM62C256), press [RUN] button then, the experiment device for teaching MONINT1.Hex emulation watchdog routine in the storer 10 (SRAM 62C256) that brings into operation.
3, start the Windows environment compilation tool of Keil C51, set up engineering, and revise start vector, CSEG AT 0C_STARTUP:LJMP STARTUP 1 is changed into CSEG AT 4000H; Is the expression user program deposited from 4000H? C_STARTUP:LJMP STARTUP1
4, BL51, the Debug to Keil C51 does simple setting, and the effect of finishing this modification and setting makes user program to start from 4000H, so far is provided with all and finishes.Under this environment, can realize source files of program (comprising C file or A51 file) newly-built, open and editting function.After source files of program is finished, select the function of the Start/Stop Debug Session under the Debug menu, can start CPU emulation, the single step that CPU emulation has, stride, at full speed, debug functioies such as breakpoint, read-write DATA/CODE/XDATA/SFR.
Embodiment 2-ROM artificial debugging mode (the JEDEC file downloading mode that contains ispLSI):
1, as Fig. 1, press [LOAD] button, experiment device for teaching resets and starts watchdog routine in microprocessor MCU SM5964 1 in-chip FLASH simultaneously, and at this moment the surface of experiment device for teaching is that the red led of (1) [LOAD] button top is bright; (2) 8 of keyboard display module 28 sections light-emitting diode displays show " 8. " with " a lantern adorned with a revolving circle of paper horses " form.
2, start 13 installed software ComView of debugging enironment main frame of the present invention, selection communicates to connect mode and baud rate, downloaded files (being the user program file) is wanted in selection, can be Intel HEX file, Bin file and JEDEC file, download successfully back (can realize functions such as " download ", " reading ", " verification " here), as Fig. 1, press [RUN] button, the green indicating lamp of [RUN] button top is bright, and the expression experiment device for teaching resets and starts user program in the storer 10 (SRAM 62C256) simultaneously.Because advantages such as user program is actually and is written in the storer 10 (SRAM 62C256), and it is fast that it has writing speed, and erasable number of times is unlimited.The Bin document down loading method is in full accord with Intel HEX document down loading method.This ROM artificial debugging user can only come the correctness of determining program operation by the outside acousto-optic feature of experiment device for teaching as display, hummer, button, serial data pilot lamp.It does not possess the debug function such as single step, breakpoint of Debug.
JEDEC file down operation method is also identical, but the JEDEC file is write the file of ispLSI and write ispLSI behind the embedded software format transformation in will the SM5964 in experiment device for teaching.Many Software tools are all supported the exploitation of ispLSI, as: ispEXPERT, Synario software, they can support design, compiling and the logic simulation of ispLSI device, can carry out schematic diagram input, ABEL-HDL, the input of VHDL hardware description language, and functional simulation is provided, can check simulation result with report form or waveform viewer.Hybrid design input mode allows to adopt simultaneously schematic diagram, higher level lanquage, truth table and state machine input mode in the design of same device.The logical design flow process comprises the following steps: design input, design realization, device programming, design verification etc.
Single chip computer teaching experimental development instrument will use emulator, brassboard at least at present.The sheet of writing a program is also wanted the configure generic programmable device.Emulator is connected to computer by communication port, the cpu chip position that the artificial head of emulator is inserted into brassboard constitutes a development environment, after artificial debugging is finished, artificial head is extracted by brassboard, change cpu chip, need the program storage in cpu chip to write the program that praises behind the artificial debugging before this.If find that The actual running results is inconsistent with the artificial debugging result, also will repeat above process.Thus, single chip computer teaching experimental development instrument has following shortcoming at present: 1) use parts many, cost height, performance history complexity; 2) the frequent plug of cpu chip and emulator artificial head on the brassboard, the fault of one-tenth bad connection; 3) The actual running results is inconsistent with the artificial debugging result, can't determine it is emulator, be brassboard, or user software causes; 4) no matter inner still outside at cpu chip program storage is, and it is all limited to write indegree, and writing speed is slow; 5) present brassboard is not all supported programmable logic device (PLD), and programmable logic device (PLD) is the important devices of often using in the Single Chip Microcomputer (SCM) system, uses programmable logic device (PLD) can significantly reduce system peripherals logic gate chip.At above-mentioned defective, the present invention programmes emulation, experiment (study), download integrated, has significantly reduced the parts in the hardware and software development environment; No element plug in the performance history, artificial debugging is with the actual motion indistinction, and often the user program of debugging is written among the SRAM, and it is unlimited to write indegree; Device has disposed online programmable logical device ispLSI, makes the student can develop programmable logic device (PLD) simultaneously.Device has the characteristics of " plate is used more ".
Single chip computer teaching experimental provision among the present invention is integrated various Peripheral Interfaces, but by communication of Ethernet interface learning network and ICP/IP protocol; Can learn the read-write operation of single-chip microcomputer by USB interface to USB flash disk; Pass through I
2C interface can be learnt single-chip microcomputer to I
2The operation of C bus device; Can learn the operation of single-chip microcomputer by the SPI interface to the spi bus device; Can learn the acquisition controlling of single-chip microcomputer by digital analog I/O unit to outside analog digital information; Can learn the read-write driving of single-chip microcomputer by the calendar clock unit to calendar clock; The man-machine interface function software that can learn single-chip microcomputer by keyboard display module writes; Can learn data transmission communication between single-chip microcomputer and other computer systems by hard serial ports.
Claims (8)
1,, it is characterized in that comprising microcontroller MCU (1), keyboard display module (2), hard serial ports (3), soft serial ports (4), Ethernet interface (5), USB/I based on the single chip computer teaching experimental provision of online programmable logical device
2C/SPI interface (6), digital analog I/O unit (7), in-system programmable logical device ispLSI (8), calendar clock unit (9), memory cell (10) and loading operation control module (11); Described keyboard display module (2) connects P1.3 and the INT0 port of microcontroller MCU (1), described hard serial ports (3) connects RXD and the TXD port of microcontroller MCU (1), described soft serial ports (4) connects P4.0 and the INT1 port of microcontroller MCU (1), Ethernet interface (5), USB interface (6), digital analog I/O unit (7), calendar clock unit (9) is connected the system bus of microcontroller MCU (1) with memory cell (10), described programmable logic device (PLD) ispLSI (8) finishes the logic control in the system and simplifies peripheral circuit in the single-chip microcomputer, described loading operation control module (11) connects EA and the RST port of microcontroller MCU (1), described microcontroller chip inside is provided with watchdog routine, also embedded the programming software of programmable logic device (PLD) ispLSI (8), realized online programming and study the programmable gate array circuit.
2, the single chip computer teaching experimental provision based on the online programmable logical device according to claim 1 is characterized in that can adopting hard serial ports (3), soft serial ports (4), Ethernet interface (5) or USB/I between described single chip computer teaching device and the debugging enironment main frame (13)
2C/SPI interface (6) connects, when adopting soft serial ports (4) to connect transmission information, because soft serial ports (4) uses the method simulation UART sequential of the I/O mouth of microcontroller MCU (1) with software, so do not take the hard serial port resource of MCU; Simulating developer software, user program download tool software and communication port comprehensive debugging tool software are installed on the described debugging enironment main frame (13).
3, the single chip computer teaching experimental provision based on the online programmable logical device according to claim 1, it is characterized in that described experiment device for teaching also comprises power module (12) and hummer, run indicator, communication pilot lamp, relay and relay on-off pilot lamp, described power module (12) is given all unit and interface power supply.
4, the single chip computer teaching experimental provision based on the online programmable logical device according to claim 1, it is characterized in that adopting between described keyboard display module (2) and the microcontroller MCU (1) the soft serial ports of another one to be connected, its level is a Transistor-Transistor Logic level, described display is eight sections charactron dynamic displays of 8 common cathodes, keyboard is a ranks matrix form nonencoded keyboard, 4 * 4 matrixes, 16 key boards.
5, the single chip computer teaching experimental provision based on the online programmable logical device according to claim 1, the model that it is characterized in that described microcontroller MCU (1) is the SM5964 chip of 44 pin PLCC encapsulation, chip has the P4 port, chip internal has the FLASH storer of 64KB, write watchdog routine of the present invention, disposed the SRAM storer of 32KB in chip exterior, the SRAM reservoir designs is that von Neumann connects, promptly can be used for depositing the user program of needs debugging, also can be used as the data-carrier store store data.
6, the single chip computer teaching experimental provision based on the online programmable logical device according to claim 1, it is characterized in that described loading moves control module (11) and is made up of basic rest-set flip-flop and NAND gate circuit, by basic rest-set flip-flop control EA port, and the generation reset signal, realize the switching of watchdog routine and user program.
7, the single chip computer teaching experimental provision based on the online programmable logical device according to claim 1 is characterized in that described memory cell (10) comprises the random data storer of parallel interface and the nonvolatile memory of serial line interface.
8, the single chip computer teaching experimental provision based on the online programmable logical device according to claim 2 is characterized in that the communication interface mode of described communication port comprehensive debugging instrument can be selected serial ports, Modem, TCP or UDP.
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| US5418720A (en) * | 1993-06-09 | 1995-05-23 | Chrysler Corporation | Symbol width measurement system |
| CN2555547Y (en) * | 2002-08-08 | 2003-06-11 | 南京经济学院 | Opening mono chip processor tester |
| CN1889149A (en) * | 2005-06-30 | 2007-01-03 | 上海市延安中学 | Apparatus for one-chip machine experiment platform |
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