CN111431973A - UART-based program online downloading system and method for practical teaching of computer system - Google Patents
UART-based program online downloading system and method for practical teaching of computer system Download PDFInfo
- Publication number
- CN111431973A CN111431973A CN202010152599.6A CN202010152599A CN111431973A CN 111431973 A CN111431973 A CN 111431973A CN 202010152599 A CN202010152599 A CN 202010152599A CN 111431973 A CN111431973 A CN 111431973A
- Authority
- CN
- China
- Prior art keywords
- program
- downloading
- uart
- data
- file
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/34—Network arrangements or protocols for supporting network services or applications involving the movement of software or configuration parameters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/42—Syntactic analysis
- G06F8/427—Parsing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/447—Target code generation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Stored Programmes (AREA)
Abstract
The invention discloses a program online downloading system and a method for practical teaching of a computer system based on UART, which convert the machine code of the program into ASCII character stream in the form of txt text suitable for UART downloading; acquiring information of the ASCII character stream, and controlling the downloading process of the ASCII character stream according to the information; respectively writing programs and data in the ASCII character stream into a program ROM and a data RAM of a CPU through a UART; after the downloading is finished, setting a downloading finishing signal, and returning a message of successful downloading to the serial port debugging assistant through the UART. The invention converts the program machine code into the downloadable ASCII character stream so as to realize program downloading by using a third-party serial port debugging assistant and improve the usability; the system and the method for automatically designing the CPU based on the FPGA realize the online downloading of the program, and greatly improve the efficiency of practical teaching experiments of the computer system; compared with the program downloading scheme based on the JTAG, the system and the method of the invention only need to slightly modify the memory interface during transplantation, are simpler and easier to use and have stronger transportability.
Description
Technical Field
The invention is suitable for assembly program experiments of computer system practice teaching series courses, belongs to the technical field of computer teaching experimental instruments, and particularly relates to a program online downloading system and method for computer system practice teaching based on UART.
Background
At present, practice teaching experiment systems and methods of computer systems are mainly divided into two types: one type of the simulation system simulates and simulates a real hardware experiment platform by means of computer software, and the other type of the simulation system enables experiment participants to go to a laboratory to perform experiments by using the real hardware experiment platform. Compared with software simulation, the real hardware experiment platform has the advantages of timely feedback, true experience and excellent effect. Particularly, the FPGA has advantages of reconfigurable, high flexibility, etc., and thus has a completely new way in practical teaching of computer systems in recent years.
In view of the advantages of the FPGA, a series of practical teaching courses of the computer system are developed on a hardware experiment platform based on the FPGA, such as a digital circuit course experiment, a course design of a computer composition principle, a course experiment of a microcomputer interface technology, and the like. Wherein, part of course experiments or course design requires experiment participants to carry out assembly program design on a CPU realized based on FPGA. When an experiment participant uses assembly language programming, no matter whether the CPU design is modified or not, the assembly program and the whole CPU design are required to be integrated, realized and generated in the IDE, the whole process consumes a lot of time and the experiment efficiency is low. Therefore, it is urgently needed to solve the problem that the program cannot be downloaded online in the experiment teaching course of the computer system.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a program online downloading system and method for computer system practice teaching based on UART, which can convert a user program machine code into an ASCII character stream with a specific format, and download the ASCII character stream into a program ROM and a data RAM of a CPU (Central processing Unit) through a program downloading IP (Internet protocol) core in a serial port debugging assistant to realize the online downloading of a program.
In order to achieve the purpose, the invention provides a program online downloading system facing computer system practice teaching based on UART, which comprises five components of an assembler, a COE translator, a UARTCoe tool, a serial port debugging assistant and a hardware experiment platform.
The assembler assembles the asm assembler written by the user into an executable file according to the instruction set architecture of the CPU.
The COE translator reads and parses the executable file, extracts the code and data segments in the executable file, and converts them to the. COE file. The coe file is a file designed by Xilinx corporation and having a specific format for initializing a Block RAM memory.
The UARTCoe tool reads and parses the. coe file, generating an ASCII character stream, forming a txt file with a specific format suitable for download.
The serial port debugging tool is any third-party tool supporting hexadecimal coding to download ASCII character streams.
The hardware experiment platform adopts a low-power-consumption FPGA development board card taking Xilinx Artix-7 series FPGA as a main chip, and also comprises a storage chip and basic peripheral components such as a UART (universal asynchronous receiver/transmitter), a dial switch, L ED (electronic device) and the like.
The program online downloading method for practical teaching of the computer system based on UART comprises the following steps:
(1) a user uses a corresponding assembler to assemble the compiled asm assembler into an executable file according to the instruction set architecture of the CPU;
(2) the COE translator translates the executable file into machine code conforming to the. COE file format;
(3) the UARTCoe tool counts the number of bytes of the. coe machine code and converts the machine code into an ASCII character stream in txt text form suitable for UART download;
(4) the serial port debugging assistant reads the ASCII character stream in hexadecimal coding and downloads the ASCII character stream to a CPU (central processing unit) on a hardware experiment platform through a UART (universal asynchronous receiver/transmitter) interface;
(5) the program downloading IP core analyzes the ASCII character stream, writes a code segment in the ASCII character stream into a program ROM of the CPU, and writes a data segment in the ASCII character stream into a data RAM of the CPU;
(6) after the program is downloaded, the program downloading IP core sets the program downloading completion signal to be valid, and returns a message of successful program downloading to a user in the serial port debugging assistant through the UART serial communication interface;
(7) the user resets the CPU through the reset button, and the downloaded program starts to run.
The hardware experiment platform adopts a low-power-consumption FPGA development board card which takes Xilinx Artix-7 series FPGA as a main chip, and further comprises a storage chip, a UART (universal asynchronous receiver/transmitter), a dial switch, L ED (electronic device) and other basic peripheral components.
The assembler and the serial port debugging assistant are designed and realized by a user or a third party person; the assembler reads an instruction set format table of the CPU, analyzes and translates each assembly instruction of the assembly program to generate a binary machine code, and writes the machine code into a file according to the format of an executable file to form the executable file; the serial port debugging assistant calls a system library function to open a UART serial port according to serial port parameters set by a user, calls the system library function, sends input data of the user to a lower computer through the UART serial port, calls the system library function, receives information of the lower computer through the UART serial port, and displays the information on a software interface.
And (2) the COE translator analyzes each format field of the executable file according to the format of the executable file generated in the step (1), extracts the program segment code data and the data segment code data of the program from the executable file, and writes the extracted program segment code data and data segment code program into a specific address of the COE file according to the characteristics of the CPU and the format of the COE file.
The UARTCoe tool analyzes the coe file according to the format of the coe file generated in the step (2), counts the number of bytes of the coe file, and forms a data packet header; the UARTCoe tool reads the contents of the. coe file, forms the payload of the packet, and finally writes the formed packet into the.txt file.
In the step (5), the program downloading IP core is integrated into the whole circuit in the form of a packaged IP core, and the Block RAM memory with the data width of 16 bits and 32 bits can be supported through configuration; the IP core comprises a protocol analysis module, a data analysis module, a Block RAM interface module, a controller module and a data sending module; the protocol analysis module analyzes the UART serial communication protocol and extracts effective data in the UART serial transmission signal; the data analysis module analyzes the ASCII character stream extracted by the protocol analysis module and extracts control information and data content from the ASCII character stream; the Block RAM interface module writes data contents in the ASCII character stream into a program ROM and a data RAM of the CPU according to a Block RAM interface protocol; the controller module monitors the protocol analysis module and the data analysis module in real time, and sets a download completion signal after the program is downloaded online; and the data sending module sends the message in the message buffer area to the serial port debugging assistant after detecting that the downloading completion signal is valid.
The invention discloses a program online downloading system and method for practical teaching of a computer system based on UART, which is characterized in that: suitable for use in a computer system having the following features:
(1) on a hardware experiment platform (or development board) based on the FPGA, FPGA programmable logic resources are used for realizing a self-designed CPU;
(2) the program ROM or the data RAM of the CPU is realized based on a Block RAM (or Block Memory) Memory inside the FPGA.
Compared with the prior art, the invention has the following advantages: 1. the invention can convert the program machine code into the downloadable ASCII character stream so as to realize program downloading by using a third-party serial port debugging assistant and improve the usability; 2. the invention realizes the on-line downloading system and method of the program for the self-designed CPU based on the FPGA, thereby greatly improving the practical teaching experiment efficiency of the computer system; 3. compared with the program downloading scheme based on JTAG, the program online downloading system and method of the invention only needs to slightly modify the memory interface of the CPU, is simpler and easier to use, and has stronger transportability.
Drawings
FIG. 1 is a schematic diagram of the operating mechanism and the structure of the hardware experiment platform of the UART-based program online downloading system and method of the present invention.
Fig. 2 is a block diagram of a program download IP core of the present invention.
FIG. 3 is a CPU state transition diagram using the UART-based program online download method of the present invention.
Detailed Description
In order to further understand and understand the present invention, the present invention will be further described in detail with reference to the following examples, which are not intended to limit the present invention.
Example 1: as shown in FIG. 1, the program online downloading system for practical teaching of a computer system based on UART comprises an assembler, a COE translator, a UARTCoe tool, a serial port debugging assistant and a hardware experiment platform, wherein the assembler assembles an asm assembler written by a user according to an instruction set architecture of a CPU to form an executable file, the COE translator reads and analyzes the executable file generated by the assembler, extracts code segments and data segments in the executable file, and integrates the code segments and the data segments to form a COE file with a specific format; the coe file is a file designed by Xilinx corporation and having a specific format for initializing a Block RAM memory. The UARTCoe tool reads and parses the. coe file, adding a control information header to the data of the. coe file, generating an ASCII character stream, forming a txt file in a specific format suitable for download. The serial port debugging tool is any third-party tool supporting hexadecimal coding to download ASCII character streams.
The XilinxArtix-7 series FPGA is a device which is provided with the highest performance power consumption ratio structure, the transceiver linear speed, the DSP processing capacity and the AMS integration in a single cost-optimized FPGA and is promoted by Xilinx, and the XilinxArtix-7 series FPGA comprises a MicroBlaze soft processor and a 1066Mb/s DDR3 technical support and can provide the maximum value for various cost-power consumption sensitive applications.
The method for testing by using the system comprises the following steps:
(1) a user uses a corresponding assembler to assemble the compiled asm assembler into an executable file according to the instruction set architecture of the CPU;
(2) the COE translator translates the executable file into machine code conforming to the. COE file format;
(3) the UARTCoe tool counts the number of bytes of the. coe machine code and converts the machine code into an ASCII character stream in txt text form suitable for UART download;
(4) the serial port debugging assistant reads the ASCII character stream in hexadecimal coding and downloads the ASCII character stream to a CPU (central processing unit) on a hardware experiment platform through a UART (universal asynchronous receiver/transmitter) interface;
(5) the program downloading IP core analyzes the ASCII character stream, writes a code segment in the ASCII character stream into a program ROM of the CPU, and writes a data segment in the ASCII character stream into a data RAM of the CPU;
(6) after the program is downloaded, the program downloading IP core sets the program downloading completion signal to be valid, and returns a message of successful program downloading to a user in the serial port debugging assistant through the UART serial communication interface;
(7) the user resets the CPU through the reset button, and the downloaded program starts to run.
The assembler and the serial port debugging assistant are designed and realized by a user or a third party person; the assembler reads an instruction set format table of the CPU, analyzes and translates each assembly instruction of the assembly program to generate a binary machine code, and writes the machine code into a file according to the format of an executable file to form the executable file; the serial port debugging assistant calls a system library function to open a UART serial port according to serial port parameters set by a user, calls the system library function, sends input data of the user to a lower computer through the UART serial port, calls the system library function, receives information of the lower computer through the UART serial port, and displays the information on a software interface.
The COE translator parses each format field of the executable file according to the format of the executable file generated in the step (1), extracts the program segment code data and the data segment code data of the program from the executable file, and writes the extracted program segment code data and data segment code program to a specific address of the. COE file according to the characteristics of the CPU and the format of the. COE file.
Analyzing the coe file by the UARTCoe tool according to the format of the coe file generated in the step (2), counting the number of bytes of the coe file, and forming a data packet header; the UARTCoe tool reads the contents of the. coe file, forms the payload of the packet, and finally writes the formed packet into the.txt file.
The program downloading IP core in the step (5) is integrated into the whole circuit in the form of a packaged IP core, and the Block RAM memory with the data width of 16 bits and 32 bits can be supported through configuration; the IP core receives a clock signal having a frequency of 10MHz as a drive. Since the clock signal frequency of 10MHz is much higher than the frequency of UART synchronization signal, after one character is transmitted or received, it is necessary to wait for several clock cycles before the next character is transmitted or received. In this embodiment, the product of the baud rate and the number of waiting clock cycles is equal to 97920000. For example, if the baud rate is set to 128000bps, after a character is transmitted or received, 765 clock cycles are required to transmit or receive the next character.
As shown in fig. 2, the program downloading IP core designed by the inventor itself includes a protocol analysis module, a data analysis module, a Block RAM interface module, a controller module, and a data transmission module. The protocol analysis module realizes signal synchronization through edge hopping of UART signals and carries out serial-parallel conversion on UART serial data received from a UART RX channel, so that analysis of a UART serial communication protocol is realized, and effective data in UART serial transmission signals are extracted; the data analysis module analyzes the ASCII character stream extracted by the protocol analysis module, extracts control information and data content from the ASCII character stream, and controls the transmitting process of the ASCII character stream data according to the extracted control information; the Block RAM interface module writes data contents in the ASCII character stream into a program ROM and a data RAM of the CPU according to a Block RAM interface protocol; the controller module monitors the protocol analysis module and the data analysis module in real time, and sets a download completion signal after the program is downloaded online; and after detecting that the download completion signal is valid, the data sending module sends the message in the message buffer to the serial port debugging assistant through the UART TX channel.
As shown in fig. 3, in this embodiment, the CPU in the hardware experiment platform is in a reset state after being started. When the experiment participant presses the reset button, the reset signal is valid, and the CPU enters the running state at the moment. At this time, if the program download signal is valid, the CPU will switch from the running state to the programming state. When the program on-line downloading process is finished, the CPU returns to the reset state again and waits for the reset signal to be set. When the experimental participant presses the reset button again, the CPU enters the running state. At this point, the CPU will run a new program.
The above-described embodiments are merely illustrative of the preferred embodiments of the present invention and do not limit the spirit and scope of the present invention. From the above description, the worker can make various changes and modifications without departing from the scope of the technical idea of the present invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (7)
1. The UART-based program online downloading system facing to computer system practice teaching is characterized by comprising five components of an assembler, a COE translator, a UARTCoe tool, a serial port debugging assistant and a hardware experiment platform, wherein the assembler assembles an asm assembler written by a user according to an instruction set architecture of a CPU to form an executable file, the COE translator reads and analyzes the executable file, extracts code segments and data segments in the executable file and converts the code segments and the data segments into a COE file, the COE file is a file with a specific format designed by an Xilinx company and used for initializing a Block RAM memory, the UARTCoe tool reads and analyzes the UARTCoe tool, generates an ASCII character stream to form a txt file with the specific format and suitable for downloading, the serial port debugging tool is any third-party tool supporting sixteen-code downloading character stream, the hardware experiment platform adopts a low-power-consumption FPGA development main chip adopting Xilinx-7 series FPGA, and the hardware experiment platform also comprises a hardware experiment platform memory board card 35, a dial switch and an external basic board card 35 and the like.
2. The program online downloading method for practical teaching of the computer system based on UART is characterized in that: the method comprises the following steps:
(1) a user uses a corresponding assembler to assemble the compiled asm assembler into an executable file according to the instruction set architecture of the CPU;
(2) translating the executable file into machine code conforming to the COE file format using a COE translator self-designed by the inventor;
(3) counting the number of bytes of the machine code coe by using a UARTCoe tool designed by the inventor, and converting the machine code into an ASCII character stream in the form of txt text suitable for UART downloading;
(4) reading an ASCII character stream in hexadecimal coding by using a serial port debugging assistant, and downloading the ASCII character stream to a CPU (central processing unit) on a hardware experiment platform through a UART (universal asynchronous receiver/transmitter) interface;
(5) the ASCII character stream is analyzed by using a program download IP core designed by the inventor, a code segment in the ASCII character stream is written into a program ROM of the CPU, and a data segment in the ASCII character stream is written into a data RAM of the CPU;
(6) after the program is downloaded, setting the program downloading completion signal to be effective by using a program downloading IP core designed by the inventor, and returning a message of successful program downloading to a user in the serial port debugging assistant through a UART serial communication interface;
(7) the user resets the CPU through the reset button, and the downloaded program starts to run.
3. The UART-based program online downloading method for practical teaching of computer systems according to claim 2, wherein: the assembler and the serial port debugging assistant are designed and realized by a user or a third party person; the assembler reads an instruction set format table of the CPU, analyzes and translates each assembly instruction of the assembly program to generate a binary machine code, and writes the machine code into a file according to the format of an executable file to form the executable file; the serial port debugging assistant calls a system library function to open a UART serial port according to serial port parameters set by a user, calls the system library function, sends input data of the user to a lower computer through the UART serial port, calls the system library function, receives information of the lower computer through the UART serial port, and displays the information on a software interface.
4. The UART-based program online downloading method for practical teaching of computer systems according to claim 2, wherein: and (2) the COE translator analyzes each format field of the executable file according to the format of the executable file generated in the step (1), extracts the program segment code data and the data segment code data of the program from the executable file, and writes the extracted program segment code data and data segment code program into a specific address of the COE file according to the characteristics of the CPU and the format of the COE file.
5. The UART-based program online downloading method for practical teaching of computer systems according to claim 2, wherein: the UARTCoe tool analyzes the coe file according to the format of the coe file generated in the step (2), counts the number of bytes of the coe file, and forms a data packet header; the UARTCoe tool reads the contents of the. coe file, forms the payload of the packet, and finally writes the formed packet into the.txt file.
6. The UART-based program online downloading method for practical teaching of computer systems according to claim 2, wherein: in the step (5), the program downloading IP core is integrated into the whole circuit in the form of a packaged IP core, and the Block RAM memory with the data width of 16 bits and 32 bits can be supported through configuration; the program downloading IP core comprises a protocol analysis module, a data analysis module, a Block RAM interface module, a controller module and a data sending module; the protocol analysis module analyzes the UART serial communication protocol and extracts effective data in the UART serial transmission signal; the data analysis module analyzes the ASCII character stream extracted by the protocol analysis module and extracts control information and data content from the ASCII character stream; the Block RAM interface module writes data contents in the ASCII character stream into a program ROM and a data RAM of the CPU according to a Block RAM interface protocol; the controller module monitors the protocol analysis module and the data analysis module in real time, and sets a download completion signal after the program is downloaded online; and the data sending module sends the message in the message buffer area to the serial port debugging assistant after detecting that the downloading completion signal is valid.
7. The UART-based program online download system and method for practical teaching of computer systems according to claim 1 and claim 2, wherein: suitable for use in a computer system having the following features:
(1) on a hardware experiment platform (or development board) based on the FPGA, FPGA programmable logic resources are used for realizing a self-designed CPU;
(2) the program ROM or the data RAM of the CPU is realized based on a Block RAM (or Block Memory) Memory inside the FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010152599.6A CN111431973B (en) | 2020-03-06 | 2020-03-06 | UART-based program online downloading system and method for practical teaching of computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010152599.6A CN111431973B (en) | 2020-03-06 | 2020-03-06 | UART-based program online downloading system and method for practical teaching of computer system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111431973A true CN111431973A (en) | 2020-07-17 |
| CN111431973B CN111431973B (en) | 2023-04-07 |
Family
ID=71547646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010152599.6A Active CN111431973B (en) | 2020-03-06 | 2020-03-06 | UART-based program online downloading system and method for practical teaching of computer system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111431973B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113836531A (en) * | 2021-09-25 | 2021-12-24 | 上海蛮犀科技有限公司 | Detection method for dynamic restoration of mobile application code memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101042815A (en) * | 2007-01-19 | 2007-09-26 | 华南理工大学 | Single chip computer teaching experimental device based on on-line programmable logic device |
| CN107505932A (en) * | 2017-08-17 | 2017-12-22 | 中国科学院光电技术研究所 | DSP remote debugging device and method based on serial communication |
-
2020
- 2020-03-06 CN CN202010152599.6A patent/CN111431973B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101042815A (en) * | 2007-01-19 | 2007-09-26 | 华南理工大学 | Single chip computer teaching experimental device based on on-line programmable logic device |
| CN107505932A (en) * | 2017-08-17 | 2017-12-22 | 中国科学院光电技术研究所 | DSP remote debugging device and method based on serial communication |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113836531A (en) * | 2021-09-25 | 2021-12-24 | 上海蛮犀科技有限公司 | Detection method for dynamic restoration of mobile application code memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111431973B (en) | 2023-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Chowdhury et al. | Platforms and testbeds for experimental evaluation of cognitive ad hoc networks | |
| CN100559331C (en) | The control system of supervisory keyboard-screen-mouse switching device and method thereof | |
| Steiner | Firmata: Towards Making Microcontrollers Act Like Extensions of the Computer. | |
| CN101800910B (en) | Simulation system, PC side simulator and mobile phone side agent client | |
| CN111431973B (en) | UART-based program online downloading system and method for practical teaching of computer system | |
| CN112131162A (en) | Data transmission method, system, device and medium based on USB equipment | |
| KR100230451B1 (en) | Method of transceiving asynchronous serial data of digital signal processor | |
| CN110855996B (en) | Image coding and decoding and network transmission method and device based on FPGA | |
| CN112350795B (en) | Data transmission method and device, storage medium and electronic device | |
| CN101763259A (en) | Method, device and system for setup processing and setup instruction of computer control function | |
| EP1598739A4 (en) | Native compile method, native compile preprocessing method, computer program, and server | |
| CN113285839A (en) | Design method of programmable data plane software switch based on DPDK | |
| US7296187B1 (en) | Hardware debug device having script-based host interface | |
| CN110175139A (en) | A kind of the Universal debugging method and USB device of USB device | |
| Parikh | Raspberry Pi and MQTT Essentials: A complete guide to helping you build innovative full-scale prototype projects using Raspberry Pi and MQTT protocol | |
| CN108737337A (en) | Equipment processing method, device, server and system | |
| CN110548285B (en) | Game communication control method and device, medium and electronic equipment | |
| CN113422756A (en) | Verification data transmission method, rate conversion device and verification data transmission system | |
| KR100663566B1 (en) | Connecting cable for debugging wireless telephone and method thereof | |
| ATA992000A (en) | ARRANGEMENT AND METHOD FOR TRANSMITTING DATA FROM AND TO CNC CONTROLS VIA A STANDARD NETWORK AND A COMPUTER | |
| CN102567070A (en) | Mobile phone software debugging method and simulator for mobile phone software | |
| CN112416843A (en) | Backboard communication equipment, control method thereof and storage medium | |
| KR100750477B1 (en) | Data communication method for real-time monitoring of embedded systems | |
| CN114706800B (en) | High-speed data selection system and method based on FPGA | |
| CN111614752B (en) | Method and device for data transmission |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |