JPS5878236A - Controller for microcomputer - Google Patents

Abstract

PURPOSE:To use effectively an ROM for generation of a control signal to simplify the constitution of a controller, by providing an ROM, which outputs a control signal pattern in accordance with a control timing, and an ROM, which outputs address information at the next timing, in the controller. CONSTITUTION:An instruction is read into an instruction register 7, and an entry address is generated from an entry address generating circuit 13 in accordance with this instruction. This generated entry address is inputted to an address decoder 14 through the first gate 17. At this time, a gate 17 is controlled by a gate switching signal 5, and the second gate 19 is controlled by the signal inverted by an inverter 18. The output of the gate 19 is applied to an address generating ROM15, and an address is generated in accordance with the timing of the output of the decoder 14. Address information from the ROM15 is applied to a control signal generating ROM16, and a control signal pattern is generated from the ROM16, and thus, the constitution of the controller is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer control device.

FIG. 1 is a circuit diagram showing an example of a conventional control device.
~(5) is a control signal generation section, (6) is a timing control signal generation section, ()) is an instruction register, f8) t [91
14 inverters, 1lli, (11) is an OR circuit,
C21 is timing Tl, 'r2---.

There is. Then, the control signal 01 output from this control device
~05 assumes the forces shown in Table 1. In Figure 1, only the control signal generator fl+ that outputs the control signal CI and the timing control signal generator (61 are shown in detail; other control signal generators are shown in detail. The details of parts (21 to (5)) have been omitted.

Considering the control signal itself, when it is an "OO" command, the timing T3. At T4, they are output to CIa+cib, respectively, and in the o1 instruction, timings Tl, T4. At T5, output to Ole, C1d, and Ole, respectively, and "1o" @ timing Tl, T5. '116 respectively Of
f, Olg, C1h, and at timing Tl, T2. T3. T4. 'r6.
'r7 respectively Oli, C1j, elk, C
'l'l.

elm, self. The control signal itself is output from the OR circuit i10+ for each command. The control signals 02 to C5 are also converted to 1 in a similar manner.

The timing control number M generation unit (6) detects the completion of generation of the control signal for one instruction and causes the generation of the control signal for the next instruction to proceed.
is output to the shift register (12) for timing signal generation in the next cycle.
The signal sets υ′, and the timing is T for the next command.
Restart from 1. "ol' instruction, 10# instruction and -I
11a-,, timing 'r5 for orders
．． 'r6. It can be easily understood from the circuit configuration of FIG. 1 that similar operations occur at T7 and T7.

However, in the conventional device described above, as shown in Table 1, for example, the control signal ratio cover pattern of T2 to T4 of the '00° instruction, the control signal output pattern of T3 to T50 of the of instruction, and the control signal output pattern of the P10 instruction are As the control signal output pattern of T4 to T6 changes, each control signal becomes E, for example, control signal Cl.
,' CIa.

01t4 --- Requires a multi-input OR circuit to obtain the OR signal of the output of +C1n, and requires an integrated circuit &li (Engineering C)
However, the size of the chip also increased.

This invention has been made in view of the above points, and is achieved by providing a control signal generation nOM (read-only memory) for generating control signals and an address generation ROM for controlling the address sequence thereof. It is an object of the present invention to provide a control device tube that can be implemented as an IC with a simple structure and a small chip size by effectively utilizing a control signal generation ROM.

FIG. 2 is a circuit diagram showing an embodiment of the present invention, and parts equivalent to those of the conventional example shown in FIG. 1 are designated by the same reference numerals. 03) is an entry address generation circuit that generates an entry address from an instruction code, Cl41 is an address decoder, α5) is an address generation ROM, and 5H is a control signal generation ROM.

0'71 is an entry address generation circuit (the first gate for inputting the entry address from + (support) to the address decoder α→, the column is an inverter, 69) u address generation ROM (the address from +51 is input to the address decoder (
14) is the second gate for entering. In addition, sF
0, which is a gate switching signal for switching between the first goo (i) 07'l and the second goo (19).Next, the operation of this embodiment will be explained. It is assumed that the relationship between instruction codes and control signals is the same as in Table 1 used for the conventional device. First, when an instruction is read into the instruction register (7), the entry address generation circuit Q (to) generates an entry address in accordance with the instruction. The entry address can be set arbitrarily, but in this example, it is selected to be ``0'' for the ``00M'' instruction, ``IJ'' for the ``of'' instruction, ``2'' for the ``10'' instruction, and ``3'' for the 11'' instruction. , this generated entry address passes through the first gate (l?) and enters the address decoder 04). At this time, the gate switching signal 8 is held at 1'', and the first gate (lη) is open, but the second gate α9 is closed by being supplied with the signal °0' by the inverter +119. In the decoder α4), the entry address is rOJ, rlJ, r2J depending on the instruction as described above.

Since it is one of "3", the corresponding address line is selected.

First, the "oo" instruction will be explained. Since the entry address is "0", the address line "0" of address decoder 0< is selected. Then, the control signal generation ROM
A signal with a pattern of [01110] is generated from (le>. As can be seen from Table 1, this is the control! signal output necessary at timing T1 of the '00° command. At the same time, the address From the generation ROM (15), (oxo
o) Generates an address signal of the pattern. This address signal then enters the address decoder 04) through the second gate (19). In other words, at this time, the IJ operation has been completed, so the gate switching signal S is 0.
, the first goo) Q7'l is closed and the second goo) (19) is open. This address decoder (+
Since the address signal input to 4) corresponds to "4", address line "4" is selected. As a result, the control signal generation RoMQ6) outputs (00,101) (7)
(D Q+ signal is generated. This is the control 41@ signal output that is required at timing T2 of the ``oo'' instruction.On the other hand,
At the same time, address generation ROMQ5) sends [010
This address signal corresponds to "5", and this generates an address signal with a pattern of "1" (1 (2)).
) and enters the address decoder 04). At this time L
C1η is closed. The address signal input to the address decoder (141) selects the address line "5". In this way, the control signal output and the next address signal are generated one after another, and the timing T3 At timing T4, a control signal is output [10001] connected to the address line "5", and at timing T4, a control signal is output from the address line "6".
10101) is output. And this timing T
When address line ``6'' is selected for 4, the gate switching signal is output, so the second gate (+9) is closed and the first gate (+71 is opened, allowing a new command to be input). become.

Next, if the incoming new instruction is a ``0nail'' instruction, the entry address ``occurrence @H3'' will generate the entry address ``〕'' as described earlier, which will cause the first goo 1-QfI to be generated. The signal is passed through and sent to address decoder 04), which selects address line "1". Then, the control signal output [0111) necessary for the 'Ol'''' instruction timing T1 is output from the control signal generation ROM Q6j, and the address signal [011
1] is generated from the address generation ROMQfi), and at the same time returns to the gate switching signal 810', and the first gate 07
) and the second gate (19) opens. Then, the address signal enters the address decoder (14), address line "7" is selected, and a necessary control signal output (01110) is generated at timing T2. 'Timing of the of instruction' r3. 'r4. The control signal cover turn required for T5 is the timing T2. of the "oo" command. 'r3. T
By setting the address signal pattern generated from the address generation ROM α6) to [01oo] when the address &l+71 is accessed, the timing T3. of the @01// instruction can be adjusted. 'r4. 'r.

It will be easily understood that the necessary control signal outputs can be obtained sequentially. In this way, the control calculation cover turn for the timing T3+T4+T5 of the '01''Q command can be used as the control calculation cover turn for the timing T2.T3.T4 of the '00° command, without having to separately provide it in the control signal generation ROM (+61). The common pattern at the end can also be used for the PA 10° instruction and the ``11°'' instruction.In the above embodiment, the output of the address generation ROM is 4 bits, and the output of the control signal generation ROM is 6 bits. These can be arbitrarily selected as required.Also, it is clear from the above description that the entry address generation circuit may be omitted and the instruction code may be directly used as the entry address.

As described in detail above, the control device according to the present invention receives address information at each control timing and outputs a control signal pattern corresponding to the timing.
OM and an address generation ROM that outputs address information at the next control timing, the control signal generation ROM is used to generate the same control signal pattern at the end of each command.
Since the same part of M can be shared, the control device can be made smaller and simpler, and when converting to C, the chip size can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional control device, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. In the figure, (7) is an instruction register, O (branch) is an entry address generation circuit, 04] is an address decoder, and (1
6) is address generation Row, Qe) is control signal generation RO
M,αη. (181 is the gate. In addition, the same reference numerals in the figure indicate the same parts or '' indicates the corresponding parts. Agent Shin Kuzuno - (1 other person)

Claims (1)

[Claims] ill An entry address generation unit that outputs entry address information according to the type of instruction, a control signal generation ROM that receives address information at each control timing and outputs a corresponding control signal pattern, and a control signal generation ROM that outputs address information at the next control timing. 1. A control device for a microcomputer, comprising an address generation ROM for outputting, and a gate for switching to input address information from the entry address generation section after the shortest control timing for the instruction.