JPS6081647A - Program control system - Google Patents

Abstract

PURPOSE:To execute branching instruction on the basis of branched address specifying information reducing the number of instruction words and to reduce the storage capacity of a program by forming a branches address storage part to store the branched address information. CONSTITUTION:An instruction word is read out from a program counter 1, set up in an instruction register 3 and analyzed by an instruction analyzing part 4 to execute the instruction. When the instruction is successively executed and an branching instruction is read out, branched address selecting data are outputted to a branched address storing part 5 by an instruction register 3. When the branching instruction is discriminated by the analyzing part 4, an output permission signal 11 is outputted to the storage part 5 so as to allow the storage part to output branched address information 10b. Simultaneously, the analyzing part 4 outputs a load signal 8 to the counter 1 so as to allow the counter 1 to load the information 10b and the branched address information from the storage part 5 is set up in the counter 1 to branch data. Thus, the provision of the storage part 5 reduces the number of instruction words and reduces the storage capacity of the program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a program control system related to execution of a branch instruction of a program.

[Prior Art] Conventionally, branch instructions have been executed by storing the branch destination address included in the instruction word in a program counter. A block diagram of this conventional program reading control section is shown in FIG.

In the figure, 1 is a program counter, 2 is a program storage unit,
3 is an instruction register, and 4 is an instruction analysis section.

When a normal program instruction is executed, the instruction word in the program storage section 2 corresponding to the address information 6 from the program counter 1 is read out and stored in the instruction register 3. The instruction word set in the instruction register 3 is analyzed by the instruction analysis unit 4, and if it is not a branch instruction, the program counter I is incremented by 1. ; Outputs 9 and instructs execution of the command.

When the branch instruction is stored in the instruction register, the instruction analyzer decodes it as a branch instruction and outputs a counter load signal 8 so as to store the branch destination address in the program counter 1. At this time, the branch destination address information 10a is input to the program counter 1 from the instruction register etc., and the program counter 1 is replaced with the branch destination address information, and the next instruction 1ilIi from the program storage unit 2 is input.
is read from the newly rewritten branch destination address, which means that the branch instruction has been executed.

For this reason, all instruction +i/branch destination address information in the program storage unit 2 must be provided, and a large number of bits is required for the instruction word, which in turn increases the storage capacity of the program. Ta.

[Objective] It is an object of the present invention to eliminate the drawbacks of the above-mentioned conventional example and to provide a program control system that can execute a branch instruction using branch destination addressing information with a small number of instruction words.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. S2 is a block diagram of a program address control device according to an embodiment of the present invention.

In the figure, the same components as in FIG. 1 are given the same numbers.

The device of this embodiment is equipped with a branch destination address register tQ section 5 for storing branch destination addresses in the conventional example, and branch destination address information in the program storage section 2 is stored in this branch destination address storage section 5. .

Figure 3 is a diagram schematically showing the flow of Progera 1, in which the program starts from address AJ, addresses C and D.
There is a conditional branch instruction at the address, and the branch destination is address B in both cases. Then, there is an unconditional branch instruction at address E, and the branch destination is A.
In this example, the program is programmed to be executed repeatedly.

The operation of the device of this embodiment will be explained using the case of executing the program shown in FIG. 3 as an example. II.

At the beginning of the program, the program counter contains (A) as an address.
) is set, the instruction word at address (A) is first read out, set in the instruction register 3, analyzed by the instruction analysis section 4, and an instruction to execute the instruction is given.
Since this instruction is not a branch instruction, the program counter is 1.
is incremented by one by the program increment signal 9, and then the instruction at address (A+1) is executed.

When the first program count is counted up and a branch instruction is read out, branch destination address selection data is output from the instruction register to the branch destination address register ta section 5. Further, when the instruction analysis unit 4 determines that it is a branch instruction, the instruction analysis unit 4 outputs an output permission signal 11 to the branch destination address storage unit 5 to output branch destination address information LOb corresponding to the branch destination address selection data. Ru. At the same time, branch destination address information 10b is sent to program counter 1.
A load signal 8 is outputted to load the program counter 1, and the branch destination address information from the branch destination address storage section 5 is set in the program counter 1, and the program is branched.

After that, the program is executed from the branch destination address.

In the case of the program shown in FIG. 3, the branch destination address storage unit 5 stores the branch destination address (A) as shown in FIG.
) and (B) are stored.

In this way, in the case of two branch destinations, in order to read (A) and (B) from the branch destination address storage unit 5, the number of branch destination designation bits in the instruction word can be 1 bit, and the bit “0” is required.
It is sufficient to read out (A) at ゛ and (B) at °°l'''.

Furthermore, in the series of explanations, the branch destination address storage section 5 is controlled to output the branch destination address information 10b by the output permission signal 11 from the instruction analysis section 4, but it may be outputted all the time.

As explained above, when there are few branch destinations due to branch instructions such as sequence control programs, the capacity of the program storage unit and the number of bits of the instruction word can be reduced by reducing the address capacity in the instruction word. .

This program storage section 2 and branch destination address record ta section 5
Of course, it may be used as ROM or RAM.

[Effects] As explained above, according to the present invention, the capacity of the branch destination address information of the instruction word can be reduced, and the storage of address information is particularly important when branching to the same branch destination address from multiple locations. It is possible to provide a program control method that can reduce the area, reduce the storage capacity of a program, and also reduce the number of bits of an instruction word.

[Brief explanation of the drawing]

Figure 1 shows the conventional program reading control section. 9 Valley''; Figure 3

Claims (1)

[Claims] comprising a program address storage means for storing a read address of a program instruction, and a branch destination address storage means for storing a branch destination address from the branch destination address storage means for storing a branch destination address of a program in the program address storage means, A program control method characterized in that a branch instruction is executed based on address information stored in the branch destination address storage means.