JPS6091474A - Exclusive control system for plural processors - Google Patents
Exclusive control system for plural processorsInfo
- Publication number
- JPS6091474A JPS6091474A JP19861583A JP19861583A JPS6091474A JP S6091474 A JPS6091474 A JP S6091474A JP 19861583 A JP19861583 A JP 19861583A JP 19861583 A JP19861583 A JP 19861583A JP S6091474 A JPS6091474 A JP S6091474A
- Authority
- JP
- Japan
- Prior art keywords
- read out
- exclusive control
- instruction
- address
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
イ0発明の分野
この発明は複数の処理装置が同一の主記憶装置を競合す
る時、単一の処理装置にのみ読出/書込アクセスを許可
し、他の処理装置の読出/書込アクセスを待たせる排他
制御方式に系り、特に上記記憶装置の6語に付加された
制御フラグを排他制御用のアクセス禁止表示に使用する
手法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention provides read/write access to only a single processing unit when multiple processing units compete for the same main memory; The present invention relates to an exclusive control method that waits for read/write access, and particularly relates to a method of using control flags added to six words of the storage device to display access prohibition for exclusive control.
口、従来技術
複数の処理装置が同一の主記憶装置に競合アクセスする
場合、どれか一つの処理装置の実行している例えば更新
処理中、他の処理装置はその更新が終るまで同時に更新
することは許されないので、排他制御される。各処理装
置により実行されるプログラムの排他制御を必要とする
例えば更新処理ルーチン毎、又は排他制御を必要とする
例えば更新処理対象のテーブル毎に従来は特定の一語あ
るいは特定の一バイトを排他制御用のアクセス禁止表示
域を定めている。排他の必要なルーチン又はテーブルの
処理開始にはまず上記アクセス禁止表示域にアクセス禁
止表示があるかを検査し、既にアクセス禁止表示があれ
ば、アクセス禁止表示が無くなるまでアクセス禁止表示
があるかの検査を繰返し、アクセス禁止表示が無くなる
と次ステツプ命令に制御の端子命令が用意されており、
以降排他の必要な処理を終えるとアクセス禁止表示を削
去している。1. Prior Art When multiple processing units access the same main memory in a competitive manner, for example, while one of the processing units is executing an update process, the other processing units update at the same time until the update is completed. is not allowed and is therefore subject to exclusive control. Conventionally, exclusive control was applied to a specific word or specific byte for each update processing routine that required exclusive control of the program executed by each processing device, or for each update processing target table that required exclusive control. A prohibited access display area has been established. To start processing a routine or table that requires exclusion, first check whether there is an access prohibition display in the above access prohibition display area, and if there is already an access prohibition display, the access prohibition display is checked until the access prohibition display disappears. Repeat the inspection and when the access prohibition display disappears, a control terminal command is prepared for the next step command.
Thereafter, when the processing that requires exclusion is completed, the access prohibition display is deleted.
ノ1 従来技術の問題点
従来技術では排他制御の必要なルーチン又はテーブル毎
にそれに対応するアクセス禁止表示域を別に用意しなけ
ればならなかりた。又排他制御を必要とするプログラム
は排他制御ルーチン又はテーブル毎に設けられたアクセ
ス禁止表示域を禁止の必要な項目と対応させて記憶し、
選択する必要があった。No. 1 Problems with the Prior Art In the prior art, a separate access-prohibited display area had to be prepared for each routine or table that required exclusive control. In addition, programs that require exclusive control store the access prohibition display area provided for each exclusive control routine or table in correspondence with the items that need to be prohibited.
I had to choose.
二1発明の目的
この発明の目的は排他制御の必要なルーチン又はテーブ
ル毎にそれに対応するアクセス禁止表示域を別に用意せ
ず缶詰の制御フラグビットを利用し、又排他制御用プロ
グラムの作成を簡易とすることを目的とする。21 Object of the Invention The object of the invention is to utilize canned control flag bits without separately preparing a corresponding access prohibited display area for each routine or table that requires exclusive control, and to simplify the creation of exclusive control programs. The purpose is to
ホ1発明の詳細な説明
図はこの発明に基く複数処理装置の排他制御の一実施例
構成図である。図で記憶装置MMはフラグ部FLを各語
檗位に有し、記憶装置MMを除く部分は1つの処理装置
CPUIであり、実際にはここに示された同じ構成の処
理装置が複数存在する。E1 A detailed explanatory diagram of the present invention is a configuration diagram of an embodiment of exclusive control of a plurality of processing devices based on the present invention. In the figure, the storage device MM has a flag part FL at each position, and the part excluding the storage device MM is one processing device CPUI, and in reality, there are multiple processing devices with the same configuration shown here. .
命令実行レジスタICに命令が読出されデコーダDCで
命令が解読され命令実行が終了すると、アドレス算出回
路AI)にて記憶装置MM中のアドレスが決定され、記
憶装置MM中の当該アドレス語の内容量mlが読出バッ
ファRBUFに読出される。ここで同時に当該アドレス
語の制御フラグ部λ
ットFLIが読出され、この時フラグビットFLJ/の
値が“1′であればゲート回路GTが閉じ上記アドレス
内容量miは読出バッファRBUF”には続出・されず
、命令実行レジスターCの命令が再度実行λ
される。他の処理装置が上記フラグビットF’IJの値
を“0#にするとゲート回路GTが開いて記憶装置MM
の内容量miが続出バッファRBUF”に読出され、命
令実行レジスターCに送られ実行される。又フラグビッ
トのオン、オフに対する命令は従来技術と同じくフラグ
ビットのオン、オフ回路SAにて実行される。When an instruction is read into the instruction execution register IC, decoded by the decoder DC, and instruction execution is completed, the address in the memory device MM is determined by the address calculation circuit AI), and the content capacity of the address word in the memory device MM is determined. ml is read into read buffer RBUF. At the same time, the control flag part λ bit FLI of the address word is read out, and if the value of the flag bit FLJ/ is "1', the gate circuit GT is closed and the address content mi is stored in the read buffer RBUF". The instruction in the instruction execution register C is executed again. When another processing device sets the value of the flag bit F'IJ to "0#," the gate circuit GT opens and the memory device MM
The content amount mi is read out to the successive buffer RBUF'' and sent to the instruction execution register C for execution.In addition, instructions for turning on and off flag bits are executed in the flag bit on and off circuit SA as in the prior art. Ru.
へ 発明の効果
複数の処理装置が排他制御により同一記憶装置をアクセ
スする場合、従来の様に特別な排他制御用のアクセス禁
止表示域を確保する必要がな(なり、又その排他処理対
応に設けたアクセス禁止表示域をプログラム作成時に選
択指定する必要がな3−
くなった。特に排他的に実行させたいルーチンにはその
ルーチンの開始命令のフラグ部にアクセス禁止表示の付
加を指定するのみでよく、また排他的に更新したいテー
ブルの項目毎にその語のフラグ部にアクセス禁止表示を
付加することができプ図はこの発明に基づく一実施例構
成図である。Effects of the Invention When multiple processing devices access the same storage device using exclusive control, there is no need to secure a special access-prohibited display area for exclusive control as in the past. It is no longer necessary to select and specify the access-prohibited display area when creating a program.In particular, for routines that you want to execute exclusively, simply specify that the access-prohibited display area be added to the flag section of the routine's start command. An access prohibition indication can be added to the flag section of the word for each item of the table that is desired to be updated frequently or exclusively.
図においてMMは複数処理装置に共有される記憶コーグ
、SAはフラグのオン・オフ回路である。In the figure, MM is a memory code shared by multiple processing devices, and SA is a flag on/off circuit.
4−4-
Claims (1)
にアクセスするマルチプロセッサにおいて、前記複数の
処理装量が同一語を同時アクセスした時、その語の前記
制御フラグビットのオン・オフにより同時アクセスの競
合を排他制御することを特徴とするマルチプロセッサの
排他制御方式。In a multiprocessor in which a plurality of processing units access a storage device that has a control flag for each word, when the plurality of processing units access the same word simultaneously, the control flag bit for that word is turned on and off. An exclusive control method for multiprocessors characterized by exclusive control of access conflicts.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19861583A JPS6091474A (en) | 1983-10-24 | 1983-10-24 | Exclusive control system for plural processors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19861583A JPS6091474A (en) | 1983-10-24 | 1983-10-24 | Exclusive control system for plural processors |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6091474A true JPS6091474A (en) | 1985-05-22 |
Family
ID=16394132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19861583A Pending JPS6091474A (en) | 1983-10-24 | 1983-10-24 | Exclusive control system for plural processors |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6091474A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6266356U (en) * | 1985-10-16 | 1987-04-24 |
-
1983
- 1983-10-24 JP JP19861583A patent/JPS6091474A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6266356U (en) * | 1985-10-16 | 1987-04-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0507208A2 (en) | A data processing system with combined static and dynamic masking of information in an operand | |
JPH0248931B2 (en) | ||
US4901235A (en) | Data processing system having unique multilevel microcode architecture | |
JPS6159554A (en) | Cache memory control circuit | |
US6338134B1 (en) | Method and system in a superscalar data processing system for the efficient processing of an instruction by moving only pointers to data | |
JPS59213084A (en) | Buffer store control system | |
JP2773471B2 (en) | Information processing device | |
US3754218A (en) | Data handling system with relocation capability comprising operand registers adapted therefor | |
US3798615A (en) | Computer system with program-controlled program counters | |
JP2690406B2 (en) | Processor and data processing system | |
JPS6091474A (en) | Exclusive control system for plural processors | |
JPS6355635A (en) | Data processing system | |
JPH0552539B2 (en) | ||
US11580036B1 (en) | Processor with conditional-fence commands excluding designated memory regions | |
JPS60195661A (en) | Data processing system | |
JP2540959B2 (en) | Information processing device | |
GB2036392A (en) | Computer system having enhancement circuitry for memory accessing | |
JP2743947B2 (en) | Micro program control method | |
JPS6237745A (en) | Integrated microprogram control system | |
JPS6224338A (en) | Memory access system | |
JPS6298443A (en) | Data processor | |
JPS59225469A (en) | Common memory exclusive control system | |
ES432949A1 (en) | Data processing system | |
JPH02138623A (en) | Microprocessor for microprogram system with pointer register | |
JPS6298428A (en) | Data processing system |