JPS6298428A - Data processing system - Google Patents

Abstract

PURPOSE:To shorten an operation word length of a 2-operand instruction by providing newly a specified bit or field for showing an instruction which as fixed a destination operated to a specified register, or not, and specifying the destination operand to one of general registers, when its mode has been designated. CONSTITUTION:Next an operation on code designating field OP and a size designating field Sz of an operand, a bit A for designating whether a destination operand is fixed to a specified register or not is provided. In case when '0' is set to this bit A, this format is used as a format to which an effective address designating field EAs and EAd for indicating a position of two operands of a source side and a destination side have been added. On the other hand, in case the bit A is set to '1', a register R0 is regarded as a kind of accumulator and an operation is executed, and the format goes to the same form as a 1-operand instruction. In such a way, the length of an operation word becomes shorter than the case having both of the two operands.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to data processing technology and a technology that is particularly effective when applied to instruction formats in program control systems. This article relates to techniques that are effective when used in instruction configuration methods.

[Background technology] Conventionally, Hrl 68000 (7) manufactured by Hitachi, Ltd.
There are four types of macro instruction sets in a microprocessor: (1) no-operand instructions (instructions that do not require operands), (2) one-operand instructions, (3) two-operand instructions, and (4) register-to-register instructions. It is broadly divided into command formats.

FIG. 2 shows a two-operand instruction (for example, A
The format of an instruction having two operands, a source side and a destination side, as indicated by D D x , D o is shown.

In other words, a 2-operand instruction has an operation code of 1
Indicates the size specification field OP, the size specification field SZ that specifies the size of the operand (bit length such as 8 bits, 16 bits, or 32 bits), and the positions of the two operands on the source side and destination side. The effective address designation field 1-EAL and EA2 were configured.

(Hitachi, Ltd., published September 1982, “Hitachi Microphone o-1 Computer, SEMICONDUCT”ER
DATA BOOK, 8/16-bit Microcomputer, pp. 945-952).

However, when the present inventors conducted a detailed analysis of programs that can be installed in a system using a conventional 68000 series microprocessor, it was found that most registers used as destinations by two-operand instructions are assigned to one specific register. I found out that it is.

U(E) In programs that often use a specific register as a destination, it is troublesome to write the destination address each time a two-operand instruction is issued. By providing the designation field EAd, there is a problem in that the operation word length of a two-operand instruction becomes longer than necessary.

[Object of the Invention] An object of the invention is to provide an instruction format that can shorten the operation word length of a two-operand instruction in a program control system.

The foregoing and other objects and novel features of the invention will become apparent from the description and accompanying drawings herein.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, in an instruction that requires two operands, the destination operand is specified in place of the destination effective address field in an operation word that has an operation code specification field and a source effective address field that indicates the source operand. A new specific bit or field is provided to indicate whether the instruction is fixed to the I register, and when that mode is specified, the destination operand is set to one of the general-purpose registers (for example, data register r). Or address register A. ) makes it unnecessary to specify the destination operand in a two-operand instruction,
This achieves the above objective of being able to shorten the operation word length of a two-operand instruction.

[Embodiment] FIG. 1 shows an example of the format of the new two-operand instruction proposed by the present invention.

That is, in this embodiment, as shown in the figure, following the operation code specification field OP and operand size specification field Sz, it is specified whether or not the destination operand is to be fixed to a specific register. Bit A (hereinafter referred to as A
(referred to as "Pill") is provided. When the A bit is set to 0', as shown in Figure 1 (A), instruction format 1 is sent in the same way as the conventional two-operand instruction format (see Figure 3). The format is such that effective addressing fields EAs and EAd are added to indicate the locations (registers) of the two operands on the source side and the destination side.

On the other hand, if the A bit is set to '1', the destination operand is, for example, data register D.
. or address register A. The command is fixed to one of the general-purpose registers (R,) and executed. In other words, an instruction like EA, ΦEA2 → EA2 is EA■R1
→Ro, the operation is executed while the register R is regarded as a kind of accumulator.

Therefore, when the A bit is set to "1", the format of the two-operand instruction is as shown in Figure 1 (R).
It has the same form as a one-operand instruction. Therefore, the length of the operation word is shorter than when it has both operands.

As a result, the description of a program containing many two-operand instructions becomes simple, the length of the entire microprogram is shortened, and memory usage efficiency is increased.

Note that when the contents of register Rx other than register R8 are used as the second operand (destination), the contents of registers R and x are written to register I in advance. You should move to .

Next, an example of the hardware configuration of a microprocessor that enables execution of a 2-operan 1-instruction configured in the format shown in 1-2 will be described with reference to FIG.

The microprocessor of this embodiment includes a microb [1 gram control force type control section]. In other words, the LSI chip that constitutes a microprocessor contains a micro ROM (read read memory) that stores micro programs.
only memory) 1 is provided. Micro ROM
1 is accessed by the microaddress decoder 5. Micro instructions constituting a micro program are sequentially read out from the micro ROMI.

The microaddress decoder 5 is supplied with a code of a macroinstruction fetched into an instruction register 2 such as an FTFO (first-in-first-out) memory through a multiplexer 3 and a microprogram counter 4. When such a microinstruction is decoded by the microaddress decoder 5, the first instruction of a series of microinstructions for executing the macroinstruction is read from the microROMI and latched into the microcontrol register 6.

A part of the microinstruction code latched in the microcontrol register 6 is sent as a control signal to the execution unit 7 consisting of ALU etc. and the multiplexer 3 as a selection signal 5.
) is supplied to a multiplexer control circuit 8 which outputs the same. Also, the other part of the microinstruction code (code in the next address field) is sent to multiplexer 3.
supplied to Then, the multiplexer 3 is controlled by the selection signal from the multiplexer control circuit 8, and instead of the macro instruction in the instruction register 2, one of the next 1-address codes of the micro instruction is sent to the micro address data 1 via the micro program counter 4. −
It is supplied to Da 5. As a result, the next microinstruction is read from the microROM 1.

When a series of microinstructions are stored in consecutive microaddress areas in the microROMI, each microinstruction is sequentially stored in the microROM by incrementing the microprogram counter 4.
It is read from 1.

Furthermore, in this embodiment, in order to support the execution of a new format two-operand instruction as shown in FIG. is provided. A flag AF is provided in the multiplexer control circuit 8 and is set and reset in response to the A pin] in the operation word.

When a two-operand instruction with the A bit set to II I II is fetched into instruction register 1 and fed to microaddress decoder 5 to read the corresponding first microinstruction, the microinstruction code sets flags A, F. is set. When the flag AF is set to "1", the multiplexer control circuit 8 replaces the next address of the microinstruction in the instruction register 2 or the microcontrol register 6 by
The multiplexer 3 is controlled to supply the microaddress generated by the address generator 9 to the microaddress decoder 5. In response, a microinstruction for processing is read from the microROM 1 with the destination operand being the register R6.

As a result, in this embodiment, even if the instruction itself has a format as shown in FIG. 1(B), which formally does not have a destination operant.

At the microprogram level, it is executed as an instruction with two operans.

In the above embodiment, the operation code specification field OP and the source side effective address specification field /L/
By providing the A bit in addition to F E A s, the destination execution address specification field EAd can be omitted, so that a two-operand instruction whose destination operand is specified in register R8 can be executed by a one-operand instruction. I explained what I did. However, the present invention is not limited thereto; for example, the A bit and the entire source-side effective addressing field E A s can be focused on, and this can be set to a specific value (for example, rl, 1, 1, etc.). IJ), it is possible to execute a specific two-operand instruction in which both the source and destination operands are fixed at specific addresses.

A two-operand instruction in which both the source and destination operands are fixed is, for example, data in the first address TO8 ()-7 stack point of the stack area, and data in the next address NO3 (next of stack point). Perform calculations with the data of
Put it in stack point TO8 TO8ONO8
−+TO8 command or R80T OS→”r o
An instruction such as s can be considered.

In this way, we add one bit to the n-bit source effective addressing field EAs, and when it reaches a particular value, we add one bit to the n-bit source effective addressing field EAs, By configuring the system so that a two-operand instruction is executed, it is possible to eliminate the need to specify any operands for a particular instruction. Shit, by using the entire r n + I J as the source-side effective addressing field EAs, the number of registers or the type of addressing mode that can be specified by this field can be determined using n bits of the source-side effective addressing field EAs. It will be possible to increase it compared to the case.

Furthermore, r n + 1. as in −Lia. It is also possible to focus on, for example, 4 bits of the J-bit field, and to execute a specific two-operand instruction with fixed operands when the bits reach a specific value.

[Effect] In an instruction that requires two operands, in the operation word that has an operation code specification field and a source-side effective address specification field indicating the source operand, a destination address is specified instead of the destination-side effective address specification field. A new specific bit or field is added to indicate whether the instruction has its operand fixed to a specific register, and when that mode is specified, the destination operand is set to one of the general-purpose registers (for example, data register D).
. Or address register A. ), this eliminates the need to specify the destination operand in a 2-operand instruction.
The operation word length of operand instructions can be shortened.

-12= As a result, the macro program becomes shorter and memory usage efficiency is improved.

Hereinafter, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the Examples described in (-), and can be modified in various ways without departing from the gist thereof. Needless to say. For example, in Figure 1 (A
), (B) may be formatted such that an extension field specifying a displacement d (offset value) is added to the execution address specification field of each operand depending on the addressing mode.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to microprocessors, which is the field of application that forms the background of the invention, but this invention is not limited thereto, and can be applied to computers and It can be used in general program-controlled data processing systems such as minicomputers.

[Brief explanation of drawings]

FIGS. 1A and 1B are explanatory diagrams showing examples of the format of an instruction to 2 operans 1 according to the present invention, respectively, and FIG.
FIG. 3 is an explanatory diagram showing the format of an operand instruction. FIG. 3 is a block diagram showing an example of the configuration of a microprocessor that can execute a two-operand instruction according to the present invention. , S
z... Operan 1 size specification field, EAs
...Source side execution address specification field, EAd
...Destination side execution address specification field, A...Specific bit (A bit), 1...
Micro ROM, 2...Instruction register (F"T F
O), 3...Multiplexer, 4...Micro program counter, 5...Micro address decoder, 6...Micro control register, 7
...Execution unit, 8...Multiplexer control circuit, AF...Flag. Figure 1A Figure Z

Claims (1)

[Claims] 1. An instruction having an operation code specification field and an effective address specification field indicating the position of an operand, a specific bit indicating whether at least the second operand is a fixed instruction. Alternatively, a data processing system characterized by having an operand instruction provided with a specific field. 2. The above-mentioned specific field is composed of a field common to the above-mentioned effective address specification field or a part thereof,
Claim 1, characterized in that the first and second operands are executed as fixed instructions when the field is set to a specific state.
Data processing system as described in Section.