JPS6224338A - Memory access system - Google Patents

Abstract

PURPOSE:To obtain the data on the bus width at a high speed by storing the data on the continuous addresses into a data register in the form of an array by reading continuously the continuous addresses of a memory, therefore reading those continuous addresses in plural times. CONSTITUTION:The contents of addresses 0-3 are read out of a memory 1 and used. In such a case, a microprocessor sets the address 0 to be read out first to an address register 2. Then the lower bits of the register 2 are decode by a decoder 4 by a reading indication and only the output 0 is turned on out of those decoding outputs 0-3. Thus a gate 60 is opened to a part D0 of the 4-bit area obtained by dividing a data register 3 of the 16-bits width. Then the read data is written to the part D0 with control of a write gate 30. When a reading indication is given again, the read data is written to a part D1 in the same way. These actions are repeated for storage of data on the addresses 0-3 into parts D0-D3 of the register 3. In such a way, data obtained for each bus and the microprocessor can use immediately these data.

Description

[Detailed Description of the Invention] [Summary] When reading memory with a bit width different from the microprocessor bus width and performing processing in microprocessor bus units, the lower bits of the memory address are decoded,
The value allows selection and control of the location in the data register where read data is to be stored, making it possible to obtain bus-width data at high speed by reading consecutive addresses multiple times. .

[Industrial Field of Application] The present invention relates to a memory access method when reading a memory element by a microprocessor, and more specifically, to a memory having a bit number configuration different from the bit number of a microprocessor bus. It relates to memory access methods for reading and using devices.

[Prior Art] Recently, microprocessors have been increasingly used to construct functional circuits, and in such cases, the number of bits of the microprocessor's bus and the number of bits of ROM (read-only memory) are important. They often have different configurations.

When a microprocessor reads out a memory element with a bit number configuration different from the number of bits of the bus and performs data processing on a microprocessor bus basis, conventional technology uses the data read from the memory element to be stored within the microprocessor. It was necessary to load the data into the arithmetic register of the bus, use the register shift function of the arithmetic register, and edit the data for each bus before use.

FIG. 4 is a diagram illustrating a conventional example, and shows an example of processing when the microprocessor bus width is 16 bits and the memory bit number is 4 bits.

■Load data A read from the memory at the first address into the calculation register in the microprocessor, ■Shift the data in the calculation register by 12 bits and save it to another register, ■Add 1 to the first address. Load the data B read from the memory at the specified address into the arithmetic register, ■ shift the data in the arithmetic register by 8 bits, ■ logical OR with the saved data in ■ and save it, ■ further +1 Load the data C read at the specified address into the arithmetic register, (1) shift the data in the arithmetic register by 4 bits, (2) perform a logical OR with the saved data (2), and save it again, (2) further +1. The data D read at the specified address is
Load it into the operation register and perform a logical OR with the data of [phase] saved ■.

[Problems to be Solved by the Invention] According to the above-mentioned conventional technology, the data editing process is performed under microprogram control, so there is a problem that the process is complicated and takes time.

The present invention aims to solve these problems and provide a new memory access method capable of high-speed read processing.

Measures for Solving Problem c] FIG. 1 shows a block diagram of the principle of the memory access method of the present invention.

In FIG. 1, 1 is the memory to be read, and 2 is the address that stores the address to access memory l.
It is a register.

3 is a data register connected to the microprocessor bus. A decoder 4 decodes a part of the lower bits of the address register 2, and its decode output is used to control the data cent of the data register 3.

When the microprocessor reads data stored in the memory 1, the microprocessor first sets the address to be read in the address register 2.

The microprocessor then reads memory 1,
° Issue an instruction to set data register 3.

The lower several bits of the address set in address register 2 are input to decoder 4 and decoded.

Reference numeral 5 denotes a data selection circuit which selects in which part of the data register 3 the readout output of the memory 1 is set based on the decoded output of the decoder 4.

Reference numeral 6 denotes a convex control circuit for controlling writing of the read output of the memory 1 into the data register 3.

Thereby, when a read instruction for the memory 1 is issued, the read data output is set to a selected part of the data register 3.

If the above operation is performed multiple times while incrementing the contents of the address register by 1, the data register 3 will contain data at consecutive addresses in the memory l.

[Operation] When data is read from a memory whose bit width is different from the bit width of the microprocessor bus and data processing is performed for each microprocessor bus, the data is stored in the memory l.
The data are stored in consecutive addresses, and when read out, the data are read out sequentially from consecutive addresses and stored in a predetermined position in the data register 3, as described above.

The bit width of the microprocessor bus is N1.゛If the number of bits in the memory is M, it is necessary to read consecutive addresses in the ratio of N and M, N/M=, and to select the storage location in the data register 3, 2x= K, determined by X
bit is required. That is, the storage location is selected and controlled using the lower X bits of the address.

By providing a relatively simple circuit as shown in Figure 1, it is possible to easily and quickly process data compared to conventional microprogram control using the shift function of a microprocessor's arithmetic register. Can be read.

In Fig. 1, data from another circuit is shown as an input to the data register 3 in addition to the output of the memory l, but this data is input from another circuit having the same data width as that of the microprocessor. data, which in this case is set in data register 3 at the same time.

[Example] The present invention will be described in more detail below with reference to Examples shown in FIGS. 2 and 3.

FIG. 2 is a block diagram of an embodiment of the present invention, with 16
An example will be shown in which a microprocessor with a data width of 4 bits reads the contents of a ROM with a data width of 4 bits and uses it as 16 bit data.

FIG. 3 is a diagram illustrating selection of a storage location of a data register.

In FIG. 2, the same reference numerals as in FIG. 1 indicate the same objects.

The operation of this embodiment will be described below with reference to FIGS. 2 and 3.

(2) When the microprocessor wants to read and use the contents of addresses 0 to 3 of memory 1, the microprocessor first writes the address "0" to be read into address register 2.

■When a read instruction is issued from the microprocessor, the lower two bits of address register 2 are decoded by decoder 4, and of the decoded outputs 0.1.2.3, only 0 becomes "on". , the 16-bit wide data register 3 is divided into four parts each with 4 bits 6
The data gate 50 to the Do portion of the J[ area is opened, the clock gate 60 is opened, controlling the write gate 30, and the read data is written to the Do portion.

■Address register 2 contains ROM? Equipped with an address increment function 21 after accessing the IN area,
The address is incremented by +1 and the address register indicates address 1.

■When a read instruction is issued again, only l of the decoder outputs is turned on, and the data gate 51 and clock gate 61 to the D1 portion of the data register 3 are opened, and the write gate 31 is controlled to read out the data. The data is D1
written in the section.

At this time, the data in the DO portion that has already been stored remains unchanged.

(2) When the above processing is repeated and reading is performed up to address 3, the data at addresses 0 to 3 are read out and stored in the Do, D+, D2 and D3 portions of the data register 3, respectively.

■For 16-bit data from other sources, data
The gates 50, 51, 52, 53 are all open and one clock allows the data register 3 DOLDl, D2
．． They are simultaneously stored in the D3 portion.

By performing the above operations, the data stored in consecutive addresses in units of buses is stored in the data register 3, and can be immediately used by the microprocessor.

[Effects of the Invention] As explained above, according to the present invention, registers and registers of a microprocessor can be improved by adding relatively simple hardware.
Compared to the conventional method of editing using a microprogram using a shift function, data can be obtained extremely easily and at high speed, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a diagram illustrating selection of a storage position of a data register, and FIG. 4 is a diagram illustrating a conventional example. It is. In the drawing, l is memory, 2 is address register, 3
is a data register, 4 is a decoder, 5 is a data selection circuit, 6 is a clock control circuit, 21 is an address incrementer, 30 to 33 are write gates, 50 to 53 are data gates, 60 to 63 are AND gates, DO, D+, D2. D3 each indicates a data register portion. 3 bucks leather 4 inches

Claims (1)

[Scope of Claims] When reading a memory (1) having a configuration of a bit number different from the bit number of a bus of a processor, the memory (1) has a configuration of a bit number that is the same as the number of bits of a bus of a processor;
Data register (3) that stores read data from
a decoder (4) that decodes a part of the lower bits of the address held in the address register (2); and a decode output of the decoder (4) to read out the data from the memory (1). Register (3)
a data selection circuit (5) that selects a storage location in the data register (3) of the read data in the memory (1) by the decoded output of the decoder (4);
a clock control circuit (6) for controlling storage in the memory (1); and by reading consecutive addresses of the memory (1),
A memory access method characterized in that the data register (3) is configured to store read data of the consecutive addresses side by side.