JPS6057604B2 - Register selection control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a register selection control method that allows the data length of an address register to be reduced.

In the conventional register selection method, the data length n is determined so as to satisfy the relationship N≦2n, where N is the number of registers and n- is the data length of the address register.

By the way, there are registers with a data length of 32 bits, 16 bits, 8 bits, etc.
For example, when writing data to a 16-bit register,
Data is prepared in a 32-bit data register, but since data is written to a 16-bit register, a Don' and Care bit portion is generated in the data register. SUMMARY OF THE INVENTION An object of the present invention is to provide a register selection control method that can reduce the data length of an address register by effectively utilizing the care bit portion of data and registers. Therefore, the register selection control method of the present invention selects an address register, a data register, a register having a data length shorter than the data length of the data register, and a register having the same data length as the data register. In a system that has multiple registers, the selection of a register with the same length as the data length of the above data register is performed using only the above address and register data. The present invention is characterized in that the selection of a register having a short data length is performed using data in the address register and part of data in the data register. Hereinafter, the present invention will be explained with reference to the drawings. The figure is a block diagram of one embodiment of the present invention, in which 1 is an address register, 2 is a data register, 3 to 5 are decoders, Ro to Rj2 are registers, and G.

Gj2 to Gj2 respectively indicate gates. Register R. The data length of R2 is, for example, 32 bits,
The data length of registers Rio to Ri2 is, for example, 16 bits, and the data length of registers Rjl to Rj2 is, for example, 8 bits. The data length of data register 2 is 32 bits. Registers RiO to Ri2 constitute the first register group, and register R
jO to Rj2 constitute the j-th register group. The contents of the address register 1 are decoded by the decoder 3, and a logic "1" signal is generated at any one of the 0th to jth output terminals according to the contents.

When logic "1" is output to the 0th output terminal, the gate G.
opens and register R. is selected, and when the first output terminal becomes logic "1", gate G1 opens and register R1 is selected, and when the second output terminal becomes logic "1", register R2
is selected and the first output terminal becomes logic "1", the register group at the first address is selected, and the j-th output terminal becomes logic "1".
Then, the jth output terminal is selected. Selection inside the first register group is performed using bits other than the data section of data register 1. For example, when the gate Gi is open, bits other than the data part are . Al. L"
If it is 0, this code is decoded by the decoder 4, the gate GiO is opened and the register RiO is selected,
If the part other than the data part shows the numerical value 44r゛, the decoder 4 opens the gate Gil and selects the register Ril, and if the part other than the data part shows the numerical value ゜゜2゛, the decoder 4 opens the gate Gi2. Register Ri
2 is selected. Selection within the jth register group is performed in a similar manner. Data is written to the registers in the first register group as follows.

(1) Place the write data and the address within the group in data register 2.

(■) Place a code specifying the first register group in address register 1.

(■) Execute write processing.

Further, data is read from the registers in the first register group as follows.

(a) Place the address within the group into data register 2. (b) Place the code specifying the first register group in address ●register 1.

(c) Execute read processing.

Writing/reading to/from registers in the j-th register group is performed in the same manner.

As is clear from the above description, the register selection control method of the present invention can reduce the data length of address registers, and when a device including these registers is made into a unit or LSI, the number of pins is reduced compared to the conventional method. Effects such as reduction in the amount of hardware can be obtained.

The reason why the number of pins can be reduced is as follows. Register "RO or Rj2 decoder 3, 4, 5 and gate G
When iO to Gj2 are formed by one LSI, the number of address signal lines extending from the address register 1 to the above-mentioned LSI can be reduced, so the number of pins of the LSI can be reduced. This effect becomes more pronounced as the number of registers having data lengths smaller than the maximum data length increases. Decoders 3, 4, and 5 can be constructed with a relatively small number of elements.

[Brief explanation of drawings]

The figure is a block diagram of one embodiment of the present invention. 1...address register, 2...data register, 3 or 5...decoder, RO
Or Rj2...Lujista, GO or Gj2...
···Gate.

Claims (1)

[Claims] 1. A system having a plurality of registers consisting of an address register, a data register, a register having a data length shorter than the data length of the data register, and a register having the same length as the data length of the data register. In , the selection of a register with the same data length as the data length of the above data register is performed using only the data of the above address register, and the selection of a register with a data length shorter than the data length of the above data register is performed. A register selection control method, characterized in that selection is performed using data in the address register and some data in the data register.