ES432949A1 - Data processing system - Google Patents

Data processing system

Info

Publication number
ES432949A1
ES432949A1 ES432949A ES432949A ES432949A1 ES 432949 A1 ES432949 A1 ES 432949A1 ES 432949 A ES432949 A ES 432949A ES 432949 A ES432949 A ES 432949A ES 432949 A1 ES432949 A1 ES 432949A1
Authority
ES
Spain
Prior art keywords
elements
words
memory
instruction
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES432949A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES432949A1 publication Critical patent/ES432949A1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions

Abstract

A data processing system that includes a computer with a memory to store different instruction and data words, and with a processor that can access each of those words to control the execution of the instruction cycles of each one of said instruction words, characterized in that the memory (MEM) includes at least two storage elements (MEMO, MEM1), each of which stores different words. Said CPU processor includes modifiable register elements (BNK) that can indicate, at least, for one (F; F or I) of said instruction cycles (F, I, A, B) during which one of said elements of storage must be accessed, the identity of these storage items. Said processor includes elements (TLC) that take into account the condition of the registration elements for addressing a word from memory. (Machine-translation by Google Translate, not legally binding)
ES432949A 1973-12-17 1974-12-16 Data processing system Expired ES432949A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7317281A NL7317281A (en) 1973-12-17 1973-12-17 DATA PROCESSING SYSTEM.

Publications (1)

Publication Number Publication Date
ES432949A1 true ES432949A1 (en) 1976-11-16

Family

ID=19820218

Family Applications (1)

Application Number Title Priority Date Filing Date
ES432949A Expired ES432949A1 (en) 1973-12-17 1974-12-16 Data processing system

Country Status (6)

Country Link
BE (1) BE823300A (en)
DE (1) DE2458707A1 (en)
ES (1) ES432949A1 (en)
FR (1) FR2254830B1 (en)
GB (1) GB1484380A (en)
NL (1) NL7317281A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1483442A (en) * 1975-10-09 1977-08-17 Standard Telephones Cables Ltd Computing machine including a directly addressable memory arrangement
US4158227A (en) * 1977-10-12 1979-06-12 Bunker Ramo Corporation Paged memory mapping with elimination of recurrent decoding

Also Published As

Publication number Publication date
GB1484380A (en) 1977-09-01
FR2254830B1 (en) 1979-02-23
FR2254830A1 (en) 1975-07-11
BE823300A (en) 1975-06-13
NL7317281A (en) 1975-06-19
DE2458707A1 (en) 1975-06-19
AU7589574A (en) 1976-06-03

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970930